JP3144133B2 - TTL output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TTL output circuit, and more particularly to a TTL output circuit having a high output impedance mode function.

[0002]

2. Description of the Related Art In recent years, as the performance of electronic equipment has been improved, the speed and density of digital signal processing circuits such as general-purpose logic devices such as TTL and CMOS have been improved. For this reason, an attempt has been made to connect a plurality of logical devices to the same wiring in a bus line and to output signals from each device to the bus line in accordance with an operation mode to share the wiring. At this time, the output impedance of the device on which operation is stopped adversely affects the driving capability of the device on which operation is performed, and fluctuations in output signal levels, distortion of operation waveforms, and the like become problems. Therefore, when outputting a signal from one device, a TTL output circuit having a function of a high output impedance mode capable of switching off an output circuit of another device and switching an output to a high impedance has been required.

An example of a conventional TTL output circuit will be described below with reference to FIG. 3, reference numerals 1 to 3 denote power supply terminals, 4 and 5 denote input terminals to which differential digital signals are input, 6 denotes an output terminal, 7 denotes a current source, 10, 11, and 14.
16 and 19 are transistors, 20 to 23 are resistors, 2
Reference numerals 6 and 27 denote diodes, and reference numeral 28 denotes switching means.

In a conventional TTL output circuit, a differential circuit is formed by connecting the emitters of the transistors 10 and 11 to each other, and resistors 23 and 22 are connected to their collectors. The resistor 22 is connected to the power supply terminal 1 for high voltage,
3 is connected to the power terminal 3 for low voltage. Transistor 1
The current source 7 is connected to the emitter common connection point of 0 and 11, and a differential digital signal is input to the bases of the transistors 10 and 11 from the input terminals 5 and 4. Darlington-connected transistors 14 and 15 are connected to the collector of transistor 11
And the output terminal 6 is connected to the emitter output.
The resistor 20 is connected between the base and the emitter of the transistor 15 to prevent leakage and secure a switching speed. An emitter follower circuit composed of a transistor 16 is connected to the collector of the transistor 10, and the output of the transistor 10 drives a common-emitter output transistor 19. The collector of the transistor 19 is connected to the emitter of the transistor 15, and the transistor 15 and the transistor 19 are alternately turned on to perform a switching operation with low impedance. And transistor 1
A diode 26 connected in reverse series between the collectors of 0 and 11;
27 is connected, and an operation mode is switched by opening and closing a switch means 28 connected between the intermediate connection point and the ground power supply terminal 2.

The operation will be described below. First, in the normal operation mode, when the switch means 28 is in an open state, a high level is input to the input terminal 4 to which the differential digital signal is input, and a low level signal is input to the input terminal 5 as well. Since the transistor 11 is turned on and the transistor 10 is cut off, the current of the current source 7 flows to the resistor 22, and the collector of the transistor 11 goes low and the collector of the transistor 10 goes high. In such a state, the transistors 14 and 15 are cut off, and the transistors 16 and 19 are turned on. Therefore, the voltage of the output terminal 6 is at a low level, that is, the saturation voltage between the collector and the emitter of the transistor 19 (about 0.2 V).

Conversely, when a low-level signal is input to the input terminal 4 and a high-level signal is input to the input terminal 5, the transistor 10 is turned on and the transistor 11 is cut off. , The current of the current source 7 is the resistance 2
3, the collector of the transistor 11 is at a high level,
The collector of the transistor 10 goes low. In such a state, the transistors 14 and 15 are turned on, and the transistors 16 and 19 are cut off. Therefore,
The voltage at the output terminal 6 is at a high level, that is, a voltage lower than the voltage at the power supply terminal 1 by the sum of the base-emitter voltages of the transistors 14 and 15 (approximately 3.6 V when the voltage at the power supply terminal 1 is 5 V). And when the load is light,
A voltage gradually lowering the voltage of the power supply terminal 1 by the voltage between the base and the emitter of the transistor 14 (the voltage of the power supply terminal 1 is
V, it approaches approximately 4.3V).

With the above operation, the level of the differential digital signal input from the input terminals 4 and 5 is converted into a voltage level equivalent to TTL and output to the output terminal 6. When the switch means 28 connected to the diodes 26 and 27 is turned on, the base potential of the transistors 14 and 16 becomes equal to the forward diode voltage of the diodes 26 and 27 (about 0.7 V). Therefore, the transistors 14, 15 and the transistors 16, 19 are cut off. Output terminal 6
Are all cut off, the output terminal 6 becomes high impedance.

[0008]

However, in the above-described conventional example, when the switch 28 is turned on to enter the high output impedance mode, the TTL output terminal 6 is connected to an external bus line, and Other circuits connected to the same wiring are at high level voltage (external circuit is C
Output about 5V for MOS logic circuit)
While the base potential of the transistor 14 is about 0.7 V, the emitter potential is about 5 V, and the transistor 1
The voltage applied between the base and the emitter is about 4.2V.
Reverse bias.

On the other hand, in order to realize a high-speed operation of the circuit,
It is necessary to use a transistor having a fine structure with a small diffusion length. However, if a reverse bias is applied between the base and the emitter of this type of transistor for a long time, the breakdown voltage and h
It is known that _FE gradually deteriorates. Such deterioration of characteristics is more remarkable as the reverse bias voltage is higher, and the bias between the base and the emitter is higher than the reverse breakdown voltage BV.
_It cannot be used near _EBO . The base-emitter bias voltage that can withstand actual use
1/2 of the emitter breakdown voltage _BVEBO (typically about 6V)
The experimental results have been obtained with the size (about 3 V) as the limit.

As is evident from the experimental results, applying a 4.2 V reverse bias between the base and the emitter of the transistor 14 requires the characteristics (h _FE and breakdown voltage) of the transistor.
Gradually deteriorates, and there is an inconvenience that it cannot be used for a long time, and there is a problem in reliability.

The present invention solves the above-mentioned conventional problems, and provides a TTL output circuit which ensures high reliability and can operate at high speed even when switching to a circuit operation in a high output impedance mode. The purpose is to:

[0012]

To achieve the above object, a TTL output circuit according to a first aspect of the present invention provides a TTL output circuit in which a fixed output current of a first current source is supplied to a common emitter connection point. One differential current switch and a second current source that outputs zero output in the normal mode and outputs an output current equivalent to the first current source in the high output impedance mode are connected to the common emitter connection point. A second differential current switch, a double-balanced differential current switch in which two input terminals of the first and second differential current switches are connected in parallel and two output terminals are cross-connected, and a power supply terminal The main current paths of the first and second transistors are connected in series between the first terminal and the ground terminal, and the base of the first transistor on the high potential side is coupled to one output terminal of the double balanced differential current switch. , The second on the low potential side A totem-pole output circuit in which the base of the transistor is coupled to the other output terminal of the double-balanced differential current switch; an output terminal connected to the emitter of the first transistor; and an input terminal connected to the output terminal And a Darlington-connected emitter follower circuit, wherein the base input of the first transistor is clamped by the emitter output of the emitter follower circuit in the high output impedance mode.

A TTL output circuit according to a second aspect of the present invention includes a first differential current switch in which a fixed output current of a first current source is supplied to a common emitter connection point, and a zero output in a normal mode. A second differential current switch having a second current source for outputting an output current equivalent to the first current source in the high output impedance mode connected to the common emitter connection point; A double-balanced differential current switch in which two input terminals of a differential current switch are connected in parallel and two output terminals are cross-connected to each other, and a first transistor and a second transistor connected between a power supply terminal and a ground terminal. The main current paths are connected in series, the base of the high potential side first transistor is coupled to one output terminal of the double balanced differential current switch, and the base of the low potential side second transistor is connected to the double balanced type differential current switch. Dynamic current A source follower circuit using a totem-pole type output circuit coupled to the other output terminal of the switch, an output terminal connected to the emitter of the first transistor, and a MOS transistor having a gate input connected to the output terminal In the high output impedance mode, the base input of the first transistor is clamped by the source output of the source follower circuit.

[0014]

According to the configuration of the first aspect of the invention, the high output impedance mode is set, all the transistors connected to the output terminal are cut off, and the internal voltage is lower than the voltage applied from the outside of the output terminal. Then, the base potential of the first transistor for output is clamped to a potential (about 1.4 V lower than the potential of the output terminal) by the conduction of the Darlington-connected emitter follower circuit, and the base-emitter of the first transistor is Reverse bias voltage is limited to low voltage.

According to the configuration of the second aspect, the high output impedance mode is set, all the transistors connected to the output terminal are cut off, and the internal voltage is lower than the voltage applied from the outside of the output terminal. When M
By the conduction of the source follower circuit of the OS-type transistor, the base potential of the first transistor for output is clamped to a potential (about 1 V lower than the potential of the output terminal),
The reverse bias voltage between the base and the emitter of this transistor is limited to the threshold value VT (about 1 V) of the MOS transistor. Further, since all the transistors connected to the output terminal except the MOS type transistors are cut off, a high output impedance can be realized in the high output impedance mode.

[0016]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, elements denoted by the same reference numerals as in FIG. 4 have the same functions, and a detailed description thereof will be omitted. 7, 8 are current sources, 9 is a switch, 1
Reference numerals 0 to 19 are transistors. The differential digital signal referred to here is a signal that oscillates in opposite phases to each other, specifically, a digital signal having a low signal level such as ECL, and a signal having a voltage amplitude of about 100 mV to 300 mV.

FIG. 1 shows a first differential current switch including transistors 10 and 11 having emitters connected to each other, and transistors 14 and 15 having emitters connected to each other.
And a second differential current switch composed of a base input terminal and a base input terminal such that output current increase / decrease directions of the first and second current switches are complemented with each other. Output terminals are connected alternately. A first current source 7 having a fixed current value is connected to a common emitter connection point of the first differential current switch, and a current value is varied to a common emitter connection point of the second differential current switch. The second current source 8 is connected. This second current source 8
A current level equivalent to the current value of the first current source and zero,
In this case, a switch 9 is provided in series with the second current source 8 in order to facilitate understanding of the description of the switching operation. The two output terminals of the double-balanced differential current switch have one end of a first resistor 22 connected to the power supply terminal 1 on the high potential side and the other end connected to the power supply terminal 3 on the low potential side. 1 resistance 22
And two input terminals are connected to input terminals 4 and 4, respectively.
5 respectively. One end of the high-potential-side resistor 22 is connected to the base of the first emitter-follower transistor 14,
One end of the low potential side resistor 23 is connected to the base of the second emitter follower transistor 16. Further, an output transistor 15 is connected between the power terminal 1 and the ground power terminal 2.
19 in series, and the output transistor 15 on the high potential side
The emitter of the transistor 14 for the first emitter follower is connected to the base of the transistor 14 and the emitter of the transistor 16 for the second emitter follower is connected to the base of the output transistor 19 on the low potential side. A Darlington-connected emitter-follower circuit in which the output terminal 6 is connected to the emitter of the output transistor 15, the input terminal is connected to the output terminal 6, and the emitter output is connected to the first emitter-follower transistor 14, 6 outputs a TTL signal level output signal.

The operation of this embodiment will be described below.
First, in the normal output mode, the switch 9 is open, and the transistors 12 and 13 are both cut off regardless of the state of the complementary digital signal input terminals 4 and 5. At this time, when a high-level signal is supplied to the complementary digital signal input terminal 4 and a low-level signal is also supplied to the terminal 5, the transistor 11 is turned on and the transistor 10 is cut off. And the collector of the transistor 11 is low level,
Goes high. In such a state, the transistors 14 and 15 are cut off, and the transistors 16 and 19 are turned on. Therefore, the voltage of the output terminal 6 becomes low level, that is, the saturation voltage between the collector and the emitter of the transistor 19 (about 0.2 V).

Conversely, when a low-level signal is applied to the input terminal 4 of the differential digital signal and a high-level signal is applied to the input terminal 5, the transistor 10 is turned on and the transistor 11 is turned on.
Is cut off. Therefore, all the current of the current source 7 flows through the resistor 23, and the collector of the transistor 11 goes high and the collector of the transistor 10 goes low. In such a state, the transistors 14, 15
Is turned on, and the transistors 16 and 19 are cut off. Therefore, the voltage at the output terminal 6 is at a high level, that is, a voltage lower than the voltage at the power supply terminal 1 by the sum of the base-emitter voltages of the transistors 14 and 15 (approximately 3.6 V when the voltage at the power supply terminal 1 is 5 V). . However, when the load resistance is large, operation is possible only by the driving capability of the transistor 14, and the voltage is gradually lower than the voltage of the power supply terminal 1 by the voltage between the base and the emitter of the transistor 14 (when the voltage of the power supply terminal 1 is 5V, about 5V). 4.3V). As described above, the differential digital signal input from the input terminals 4 and 5 is converted into a voltage amplitude corresponding to the TTL output level and output to the output terminal 6.

When the switch 9 is closed, the transistors 14 and 15 perform a switching operation in accordance with the level of the differential digital signal input from the input terminals 4 and 5, and the current of the current source 8 is supplied to the resistor 22 or 23. Flows. That is, when a high-level signal is supplied to the input terminal 4 and a low-level signal is also supplied to the input terminal 5, the transistor 12 is turned on and the transistor 13 is cut off. The current flows to the resistor 23, and the collector of the transistor 12 becomes low level. At this time, the transistor 11 is conducting as described above,
Since the transistor 10 is cut off, the current of the current source 7 flows to the resistor 22 and the collector of the transistor 11 becomes low level. Conversely, when a low level signal is applied to the complementary digital signal input terminal 4 and a high level signal is applied to the terminal 5, the transistor 13 is turned on and the transistor 12 is cut off.
2, the collector of the transistor 13 becomes low level. At this time, as described above, since the transistor 10 is conducting and the transistor 11 is cut off, the current of the current source 7 flows to the resistor 23 and the transistor 1
The collector of 0 goes low. With the above operation, the resistance 2
A current flows through both 2 and 23, and the terminal voltage becomes low level in both cases. Therefore, the transistors 14, 15 and the transistors 16, 19 are cut off. Accordingly, all the transistors connected to the TTL output terminal 6 are cut off, so that the TTL output terminal 6 is in the high impedance mode.

On the other hand, in the high impedance mode, the TTL output terminal 6 is connected to an external bus line, and another external circuit connected to the same bus line outputs a high-level voltage (external voltage). When the circuit is a CMOS logic circuit, about 5 V) is output, and the TTL output terminal 6
When the voltage becomes V, the current of the current source 7 or the current source 8 flows through the resistor 22 and the transistors 14 and 15 are cut off. Flows through the transistor 18 so that the base potential of the transistor 14 does not drop below it. That is, transistor 1
The base potential of the transistor 14 connected to the emitter 8 becomes a voltage (about 3.6 V) lower than 5 V by twice (about 1.4 V) the base-emitter voltage of the transistor. Therefore, in any case, transistor 1
The base-emitter reverse bias voltage of the transistor No. 4 does not become larger than twice (about 1.4 V) the base-emitter voltage of the transistor.

As described above, according to the first embodiment of the present invention, the high output impedance mode is set, and all the transistors (14, 15, 19) connected to the output terminal 6 are cut off. Even if the internal voltage is lower than the voltage applied from the outside of the output terminal 6, the base potential of the first emitter-follower transistor 14 is changed to the third potential by the conduction of the third emitter-follower circuit (17, 18) in Darlington connection. And the reverse bias voltage between the base and the emitter of the first emitter follower transistor is limited to a low voltage (up to about 1.4 V). Is done. Therefore, deterioration of the _hFE and the breakdown voltage of the transistor 14 can be prevented, and the reliability of the circuit can be ensured for a long time.

However, in the first invention, even if the base input of the Darlington-connected emitter follower circuit for clamping the base potential of the transistor 14 operates with a very small current and maintains a high input impedance, The value is finite, and if the number of the same type of output circuits commonly connected to the bus line increases, the current cannot be ignored and may adversely affect the DC potential of the bus line and the switching operation.

The second invention is a high output impedance
It is another object of the present invention to further increase the impedance of the output terminal 6 in the mode as compared with the first aspect of the invention and eliminate the influence of the internal impedance.

Next, an embodiment of the second invention will be described with reference to the drawings. FIG. 2 shows the configuration of the present embodiment. 2, the elements corresponding to the elements in FIG. 4 are denoted by the same reference numerals. 7, 8 are current sources,
9 is a switch, 10 to 16, 19 are transistors, 24
Is a MOS transistor. In this embodiment, the bipolar transistors 17 and 1 of the first invention are used.
The Darlington-connected emitter follower circuit 8 is replaced by a MOS transistor 24, and the base potential of the transistor 14 is clamped by a source follower circuit.

The TTL of the present embodiment configured as described above
The operation of the output circuit will be described below with reference to FIG. The normal operation mode is the same as that of the first embodiment described above, and the description thereof is omitted.

When the switch 9 is closed to set the high output impedance mode, the current of the current source 8 flows through the resistor 22 or 23 in response to the differential digital signal input from the input terminals 4 and 5. That is, the input terminal 4
When a high level is applied to the input terminal 5 and a low level signal is applied to the input terminal 5, the transistor 12 is turned on and the transistor 13 is cut off, so that the current of the current source 8 flows through the resistor 23, The collector goes low. At this time, since the transistor 11 is conducting and the transistor 10 is in the cutoff state as described above, the current of the current source 7 flows to the resistor 22 and the collector of the transistor 11 becomes low level. Conversely, when a low level signal is supplied to the complementary digital signal input terminal 4 and a high level signal is also supplied to the terminal 5, the transistor 13 is turned on and the transistor 12 is cut off, so that the current of the current source 8 is supplied to the resistor 22. Flow, transistor 1
Collector 3 goes low. At this time, as described above, the transistor 10 is conducting, and the transistor 1
Since 1 is in the cutoff state, the current of the current source 7 flows to the resistor 23, and the collector of the transistor 10 becomes low level. With the above operation, a current flows through both of the resistors 22 and 23, and the terminal voltage becomes low level. Therefore, the transistors 14, 15 and 16, 19 are cut off. As described above, all the transistors connected to the output terminal 6 are in the cutoff state, and the output impedance viewed from the outside of the output terminal 6 becomes almost infinite.

When the operation state of the TTL output circuit is set to the high output impedance mode, the output terminal 6 is connected to an external bus line, and the output terminal 6 is connected to the external bus line connected to the same bus line. Is a high level voltage (about 5 when the external circuit is a CMOS logic circuit).
V) and the TTL output terminal 6 becomes 5V,
When the current of the current source 7 or the current source 8 flows through the resistor 22, the bases and emitters of the transistors 14 and 15 are cut off, and the base potential of the transistor 14 decreases to a potential at which the MOS transistor 24 conducts, the remaining current becomes M
The current flows to the OS-type transistor 24, and the base potential of the transistor 14 does not drop below it. That is, MOS
The base potential of the transistor 14 connected to the source of the transistor 24 is a voltage (about 4 V) lower than 5 V by the gate-source voltage (about 1 V) of the MOS transistor.
V). Therefore, in any case, the reverse bias voltage between the base and the emitter of the transistor 14 becomes
It cannot be higher than the threshold voltage (gate-source voltage) of the MOS transistor 24. This threshold voltage is about 1 V, and the BV of the bipolar transistor is
_Since it is sufficiently smaller than 1/2 of _EBO (6 to 7 V), highly reliable circuit operation can be guaranteed. Moreover, the impedance of the gate electrode of the MOS transistor 24 connected to the output terminal 6 is very high, which may be called an infinite impedance, and there is a possibility that the impedance of the output terminal 6 decreases in the high output impedance mode. Not at all.

As described above, according to the embodiment of the second invention, the TTL output circuit is set to the high output impedance mode, and the output terminal 6 to which a plurality of logic circuits are connected becomes higher than the internal operating voltage. Also, the source follower circuit including the MOS transistor 24 whose gate electrode is connected to the output terminal 6 clamps the base potential of the transistor 14 with the source potential. As a result, the reverse bias voltage between the base and the emitter of the transistor 14 is limited by the threshold voltage (approximately 1 V) of the MOS transistor, so that the reliability of the output circuit can be improved and the influence of the load current on the bus line can be completely suppressed. A TTL output circuit having a high output impedance mode not provided can be realized.

[0031]

According to the TTL output circuit of the present invention, when operating in the high output impedance mode, the reverse bias voltage of the first emitter follower transistor is reduced to a low voltage by the threshold voltage of the transistor constituting the follower circuit. Limited, greatly reducing the deterioration of transistor characteristics, increasing the reliability of the circuit, increasing the impedance seen from the output terminal side, and stopping the operation of the output circuit even if the same type of circuit is commonly connected to the bus line The effect of the internal impedance can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a TTL output circuit according to the first invention;

FIG. 2 is a block diagram of one embodiment of a TTL output circuit according to the second invention;

FIG. 3 is a configuration diagram of a conventional TTL output circuit.

[Explanation of symbols]

 1-3 power supply terminal 4,5 differential digital signal input terminal 6 output terminal 7,8 current source 9,28 switch 10-19 transistor 20-23 resistor 24 MOS type transistor 25 logic fixing means 26,27 diode

Claims (2)

(57) [Claims] 1. A first differential current switch in which a fixed output current of a first current source is supplied to a common emitter connection point, and a zero output in a normal mode and a high output impedance mode. A second differential current switch having a second current source that outputs an output current equivalent to the first current source connected to a common emitter connection point; and a first differential current switch and a second differential current switch. A double-balanced differential current switch in which two input terminals are connected in parallel and two output terminals are cross-connected, and main current paths of first and second transistors are connected in series between a power supply terminal and a ground terminal. The base of the first transistor on the high potential side is coupled to one output terminal of the double balanced differential current switch, and the base of the second transistor on the low potential side is connected to the double balanced differential current switch. Switch A totem pole type output circuit coupled to the other output terminal of the first transistor, an output terminal connected to the emitter of the first transistor, and a Darlington connection emitter follower circuit having an input terminal connected to the output terminal. Wherein the base input of the first transistor is clamped by an emitter output of the emitter follower circuit in a high output impedance mode.
Output circuit. 2. A first differential current switch, wherein a fixed output current of a first current source is supplied to a common emitter connection point, and a zero output in a normal mode and a high output impedance mode. A second differential current switch having a second current source that outputs an output current equivalent to the first current source connected to a common emitter connection point; and a first differential current switch and a second differential current switch. A double-balanced differential current switch in which two input terminals are connected in parallel and two output terminals are cross-connected, and main current paths of first and second transistors are connected in series between a power supply terminal and a ground terminal. The base of the first transistor on the high potential side is coupled to one output terminal of the double balanced differential current switch, and the base of the second transistor on the low potential side is connected to the double balanced differential current switch. Switch A source-follower circuit using a totem-pole output circuit coupled to the other output terminal of the first transistor, an output terminal connected to the emitter of the first transistor, and a MOS transistor having a gate input connected to the output terminal A TTL output circuit, wherein a base input of the first transistor is clamped by a source output of the source follower circuit in a high output impedance mode.