JP3035969B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device such as a GaAs MESFET (Schottky field effect transistor) and a method for manufacturing the same.

[Prior Art] GaAs MESFETs have good microwave characteristics and are used as microwave FETs for high output. For example, Transactions on Electron Devices ("IEEE TRANSACTIONS ON ELECTRON DEVICE VOICE
LED-29 NO.11 NOVEMBER 1982 P.1772-1777 ")
There is a MESFET shown in the literature. This MESFET is manufactured by self-alignment using a SAINT process which is a replacement gate process.

Also, United States Patent (Patent N)
umber: 4,642,259) source-side self-aligned gate process “SOURCE-SIDE SELF-ALIGNED G
“ATE PROCESS” shows a MESFET having a structure having an offset gate electrode and a manufacturing process thereof.

[Problems to be solved by the invention]

However, in a FET manufactured by using the SAINT process shown in the above conventional transaction, a high-concentration impurity layer (n ⁺ layer) is adjacent to a gate electrode and a channel layer. Therefore, the withstand voltage performance between the drain and the gate is deteriorated, and the Schottky gate withstand voltage and the drain withstand voltage are reduced.

Further, the FET having the offset gate structure disclosed in the above-mentioned conventional U.S. Patent has a first drawback that it is difficult to control the recess structure. Second, there is a disadvantage that the manufacturing process is long. Third, similarly to the FET using the SAINT process, there is a disadvantage that the Schottky gate breakdown voltage and the drain breakdown voltage decrease because the n ⁺ layer is adjacent to the channel layer.

In general, a GaAsIC requires a Schottky gate breakdown voltage and a drain breakdown voltage of 8 to 10 V from the requirement of compatibility (commonness) with the SiIC. A high-output microwave band FET is required to withstand a voltage of about 20V.

[Means for solving the problem]

In order to solve the above problem, a compound semiconductor device of the present invention has an impurity layer formed on a surface portion of a semiconductor substrate and an impurity layer formed so as to sandwich a channel layer formed by the impurity layer. First and second lightly doped layers having a higher concentration, and an impurity concentration higher than that of the first lightly doped layer, formed on the first lightly doped layer side at a position receded by a predetermined distance from an end of the channel layer. The first high-concentration impurity layer and the second lightly-doped layer have a higher impurity concentration than the second lightly-doped layer formed at a position separated from the end of the channel layer by a distance larger than the predetermined distance. A second high concentration impurity layer, a source electrode formed in ohmic contact with the first lightly doped layer, and a source electrode formed in ohmic contact with the second lightly doped layer. And the drain electrode, is characterized in that a Schottky contact with the gate electrode formed on the channel layer. According to another aspect of the present invention, there is provided a method of manufacturing a compound semiconductor device, comprising: forming an impurity layer in a surface portion of a semiconductor substrate; Forming a second high-concentration impurity layer, and in the region between the first high-concentration impurity layer and the second high-concentration impurity layer on the impurity layer, A dummy gate is formed at a position where the distance is greater than the distance from the first high-concentration impurity layer, and a first lightly doped layer having an impurity concentration higher than the impurity layer and lower than the high-concentration impurity layer is formed using the dummy gate as a mask. Forming a second lightly-doped layer having a higher impurity concentration than the impurity layer and a lower impurity concentration than the high-concentration impurity layer on the second high-concentration impurity layer side; Light A source electrode is formed in ohmic contact with the doped layer, a drain electrode is formed in ohmic contact with the second lightly doped layer, and the dummy gate is removed. A gate electrode is formed by Schottky contact.

[Action]

The second lightly doped layer increases the distance between the high-concentration impurity layer on the drain side and the gate electrode without increasing the resistance between the gate and the drain, and the channel formed between the electrodes has a high impurity concentration. It is formed at a position away from the layer.

It is manufactured by a simple process using self-alignment and established lithography and implantation techniques.

〔Example〕

FIG. 2 is a sectional view showing a manufacturing process of a GaAs MESFET according to one embodiment of the present invention.

Ion implantation is selectively performed on the semi-insulating semiconductor substrate 1 made of GaAs using a photolithography technique to form an impurity layer. Here, part of the impurity layer functions as a channel (hereinafter, referred to as a channel layer 2). At this time, the dopant is a donor such as ²⁹ Si, and the channel layer 2 is formed in an n-type. The channel layer 2 may not be formed by ion implantation, but may be formed by an epitaxial growth technique. Further, Si ions are selectively implanted by using a photolithography technique, and the first n ⁺ layer 3a (first high concentration impurity layer) and the second n ⁺ layer
3b (second high concentration impurity layer) is formed (FIG. 4A)
reference). The ion implantation for forming the first n ⁺ layer 3a and the second n ⁺ layer 3b is performed by bare implantation on the semiconductor substrate 1 at an acceleration voltage of 100 to 200 keV.

Next, SiN is formed on the semiconductor substrate 1 by plasma CVD.
The film 4 is deposited. In some cases, the SiN film 4 does not need to be deposited by an annealing method performed later. That is, the SiN film 4 is unnecessary when the annealing is performed by arsine annealing, and the SiN film 4 is required when the annealing is performed by Cap annealing. Next, an AZ photoresist material or the like is dropped on the SiN film 4 and applied by a spin coat method so as to have an appropriate thickness to form a resist layer 5. Further, a blocking film 6 such as SiO ₂ or polysilicon (poly-Si) for blocking the dopant is formed to an appropriate thickness on the resist layer 5 by a sputtering device (see FIG. 2B).

Next, the blocking film 6 is patterned using a photolithography technique, and the blocking film 6 is formed by reactive ion etching.
Is selectively removed. Further, the resist layer 5 is removed by reactive ion etching to form an undercut dummy gate 7 (see FIG. 3C). This dummy gate 7 has a distance from the second n ⁺ layer 3b to the first n ⁺ layer 3a.
It is formed at a position that is larger than the distance from.

Next, Si ions are implanted through the SiN film 4 using the dummy gate 7 formed in the shape of the letter "T" as a mask, and the first n 'layer 8a (the first lightly doped layer) and the A second n 'layer 8b (second lightly doped layer) is formed.
As a result of the formation of the first n 'layer 8a and the second n' layer 8, as compared with the distance from the end of the channel layer 2 to the first n ⁺ layer 3a, the end of the channel layer 2 From the second n ⁺ layer to 3b
The distance between them becomes large (see FIG. 4D). In this case, the ion implantation is performed at an acceleration voltage of 50 to 100 keV and a dose of 0.5.
Performed at ~ 3.0 × 10 ¹³ (pieces / cm ² ). In this ion implantation, the implantation amount is larger than when the channel layer 2 is formed, and smaller than when the first n ⁺ layer 3a and the second n ⁺ layer 3b are formed. Also, the acceleration voltage is higher than when the channel layer 2 is formed,
It is lower than when the first n ⁺ layer 3a and the second n ⁺ layer 3b are formed. Therefore, the first n 'layer 8a and the second n' layer 8b are deeper than the channel layer 2 and have a higher impurity concentration, and the first n ⁺ layer 3a and the second n ⁺ Shallower than layer 3b and
The impurity concentration decreases. Note that it is possible to select the threshold voltage and the transmission conductance of the formed FET depending on the value of each ion implantation condition.

Next, an SiO ₂ film 9 is deposited on the dummy gate 7 by a sputtering method (see FIG. 3E). After that, the dummy gate 7 is removed by a slight etching and a lift-off method, and an opening 10 as an inversion pattern is formed in the SiO ₂ film 9 (see FIG. 6F). The opening 10 is formed at a position where the distance from the second n ⁺ layer 3b is larger than the distance from the first n ⁺ layer 3a. At this stage, an annealing process is performed to activate the implanted Si ions.

Next, the SiO ₂ film 9 is selectively removed by photolithography and reactive ion etching, and the SiN film 4 is further removed by plasma etching. The source electrode 12 is formed in ohmic contact with the first n 'layer 8a exposed by this removal, and the drain electrode 11 is formed in ohmic contact with the second n' layer 8b (see FIG. 3G). . The drain electrode 11 is formed near a protruding region on the second n 'layer 8b formed so as to protrude in a region sandwiched between the first n ⁺ layer 3a and the second n ⁺ layer 3b. In addition, each of these electrodes 11 and 12 is
Are arranged symmetrically with respect to the center, and are arranged at positions symmetrical with respect to a gate electrode to be formed later.

Next, the MESFET having the structure shown in FIG. 1 is formed by removing the SiN film 4 exposed in the opening 10 by plasma etching and making a Schottky contact with the channel layer 2 exposed after the removal. Is obtained.

Therefore the MESFET is formed apart dummy gate 7 from the second n ⁺ layer 3b, a second n ⁺ layer 3b of the drain electrode 11 side
The distance between the gate electrode 13 and the first
Is longer than the distance between the n ⁺ layer 3a and the gate electrode 13. In the case of this embodiment, the length is 0.15 μm or more. The distance between the drain electrode 11 and the gate electrode 13 is the same as the distance between the source electrode 12 and the gate electrode 13, and the distance between the source electrode 12 and the gate electrode 13. Second n ⁺ layer 3b
A bit far from. Therefore, a channel formed between the electrodes is formed at a position away from the second n ⁺ layer 3b. Therefore, the withstand voltage performance between the gate electrode 13 and the drain electrode 11 is improved, and the Schottky gate withstand voltage and the drain withstand voltage are improved.

Further, since the second n 'layer 8b having an appropriate concentration and depth is provided between the channel layer 2 and the second n ⁺ layer 3b on the drain side, the series resistance _RD between the gate and the drain is reduced. It decreases, transmission conductor scan g _m increases. This transfer conductance g _m is expressed by the following equation, where the intrinsic transfer conductance in a normal MESFET is g _{m0 ′} and the series resistance between the gate and the source is R _S.

g _m = g _m0 / {1 + _RS · g _m0 + (R _S + R _D ) · g _{m0 か ら From} this equation, it is understood that the smaller the gate-drain resistance R _D , the smaller the conductance g _m .

Further, the manufacturing process of the MESFET in the present embodiment uses the lithography technology and the implantation technology established in the prior art, and further uses the self-alignment technology using the dummy gate 7 in the manufacturing process. The FET can be easily manufactured with a small number of manufacturing processes, and the obtained F
ET yield rate is higher.

〔The invention's effect〕

As described above, according to the present invention, the distance between the high-concentration impurity layer on the drain side and the gate electrode is increased without increasing the resistance between the gate and the drain by the lightly-doped layer, that is, without reducing the transfer conductance. Are formed longer. Further, a channel formed between the electrodes is formed at a position away from the high-concentration impurities. Therefore, it is possible to improve the Schottky gate breakdown voltage and the drain breakdown voltage without lowering the performance of the device. Therefore, the requirement for compatibility with SiIC is achieved.

Also, the device is manufactured by a simple process using self-alignment, and by established lithography and implantation techniques. Therefore, the device can be easily manufactured by a short manufacturing process, and the yield can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a MESFET according to one embodiment of the present invention, and FIG. 1. GaAs semiconductor substrate, 2. Channel layer (n-layer), 3a
... The first n ⁺ layer, 3b... The second n ⁺ layer, 4.
... Dummy gate, 8a first n ′ layer, 8b second n ′ layer, 9 SiO ₂ film, 11 drain electrode, 12 source electrode, 13 gate electrode.

Claims (1)

(57) [Claims] An impurity layer is formed on a surface portion of a semiconductor substrate, and first and second high-concentration impurity layers having a higher impurity concentration than the impurity layer are formed in different regions of the impurity layer. The second high-concentration impurity layer in a region on the layer between the first high-concentration impurity layer and the second high-concentration impurity layer;
Forming a dummy gate at a position where the distance from the high-concentration impurity layer is larger than the distance from the first high-concentration impurity layer, and using the dummy gate as a mask to be higher than the impurity layer and higher than the high-concentration impurity layer. First with low impurity concentration
Forming a lightly doped layer on the side of the first high concentration impurity layer, and forming a second lightly doped layer having an impurity concentration higher than the impurity layer and lower than the high concentration impurity layer by using the second high concentration impurity layer. Forming a source electrode in ohmic contact with the first lightly doped layer, forming a drain electrode in ohmic contact with the second lightly doped layer, removing the dummy gate, and then removing the impurity layer. A method for manufacturing a compound semiconductor device, comprising: forming a gate electrode in Schottky contact with a position where the dummy gate is formed.