JP3033642B2 - Firmware storage device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer system, and more particularly, to an arrangement for storing system firmware.

[0002]

BACKGROUND OF THE INVENTION Personal computer systems in general, and IBM personal computers in particular, are widely used to provide computing power to many areas of today's society. Personal computer systems typically include a system processor, a display monitor, a keyboard, one or more diskette drives, fixed disk storage, an optional pointing device such as a "mouse", and an optional printer. Can be defined as a desktop, floor-standing or portable computer having These systems are designed primarily to provide independent computing power to a single user or a small group of users, and are cheaply priced for purchase by individuals or businesses. An example of such a personal computer system is IBM's PERSONAL C
OMPUTER (hereinafter abbreviated as IBM PC), PER
SONAL COMPUTER XT (hereinafter referred to as IBM
XT), PERSONAL COMPUTER
AT (hereinafter abbreviated as IBM AT) and IBM PE
RSONAL SYSTEM / 2 (hereafter IBM PS /
2) Models 25, 30, 50, 55, 57, 6
It is commercially available under the trademarks 0, 65, 70, 80, 90, 95.

[0003] These systems can be broadly classified into two families. The first family, commonly referred to as Family 1 models, uses a bus architecture exemplified by IBM AT computers and other "IBM compatible" computers. The second family is Family 2
IBM PS / 2 models 50 to 9
5 uses IBM's Micro Channel bus architecture. Family 1 and Family 2
The bus architecture used for is well known in the art.

Beginning with IBM PC, the earliest personal computer system in the Family 1 model family, throughout the Family 2 model family, the system processor was selected from Intel "86 Family" processors (ie, microprocessors). Was. In
The tel86 family of processors includes Intel C
8088, 8 commercially available from the corporation
086, 80286, 80386 and 80486 microprocessors. The architecture of the Intel 86 family of processors provides an upwardly compatible instruction set that helps protect software investments in previous processors of the 86 family. This upward compatibility preserves the foundation of software applications and is one of the major factors that contributed to the great success of IBM PC and its successors.

[0005] The IBM PC and IBM XT are available from IBM
It was the first model in the M personal computer family and used an Intel 8088 processor. I
The next major change in BM personal computer systems is the IBM AT, which is an Intel 80
286 processor. The PS / 2 series used multiple Intel processors. PC and XT
A similar system to Int's PS / 2 Model 30
This version used el8086. PS / 2
Models 50 and 60 both used an Intel 80286 processor. The Intel 80386 processor is used for some versions of the IBM PS / 2 model 70 and for the IBM PS / 2 model 80. IBM
Other versions of PS / 2 model 70 and PS /
Two models 90XP486 and 95XP486 are available from In
A tel80486 processor is used. One of the common features of all these systems is the use of Intel86 family processors. Various well-known software operating systems on the market
A system, such as a DOS or OS / 2 operating system, can operate on various processors of the Intel86 family.

[0006] Processors in the Intel86 family support various "modes". Intel
The basic mode of the 86 family of processors is "real"
Mode. Real mode is the only mode of operation for 8088 and 8086 processors. In real mode,
One megabyte of address space is supported. 808
No protection mechanism is available for the 8 and 8086 processors. 80286 supports both real mode and "protected" mode of operation. As the name "protected" implies, protected mode provides protected mode operation. This protection is to prevent one application from interfering with the operation of another application or operating system. 80286
Provides extended addressability compared to the 8088 and 8086 by allowing up to 16 megabytes of memory to be directly addressed. To maintain backward compatibility, 80286 operates in real mode to
8 or 8086 real modes can be emulated. 80386 and 80486 further provide the ability to address up to 4 gigabytes of physical memory,
It extends the architecture of the Intel86 family. 80386 and 80486 also support "virtual 86" mode operation. The virtual 86 mode is a mode that supports the operating characteristics of the real mode within the overall framework of the protected mode environment. While this virtual 86 mode is useful because it offers a very high level of compatibility with applications running under the DOS operating system, it must now operate in a fully protected mode operating system.

It has also been recognized that the goal of achieving software and hardware compatibility in the earliest personal computer systems of the Family 1 model family, such as the IBM PC, will be very important. It had been. To achieve this goal, a separation layer of system resident code, also referred to as "microcode," has been established between hardware and software. This code provides an operational interface between the user's application programs and operating system and the hardware device, eliminating the need for the user to worry about the characteristics of the hardware device. As a result, this code evolves into a basic input / output system (BIOS), allowing new hardware devices to be added to the system and
Programs can now be separated from the specificity of hardware devices. The importance of BIOS was immediately evident. This frees the device driver from dependence on a particular hardware device and provides the device driver with an intermediate interface to the device.
The BIOS is an integral part of the computer system and resides on the system planar board of the system unit to control the movement of data into and out of the system processor and is stored in read-only memory (ROM) for the user. Shipped. For example, the original IBM PC
BIOS has 8 of the ROMs resident on the planar board.
K bytes (kilobytes or “K bytes”
4 bytes). In addition to ROM, the planar board contained a system processor, main random access memory (RAM), and other components, which were fixed substantially flush with the board. The ROM also contained a power-on self-test (POST) program used for testing and initializing the computer system. The entire code resident in the computer system ROM is called "system firmware"
Or just came to be called "firmware". Therefore, the firmware includes a POST portion and a BIOS portion. BIOS was sometimes defined to include POST.

In introducing new models of the personal computer family, firmware must be updated and extended to support new hardware devices, such as input / output (I / O) devices. As expected, the memory size required for firmware has begun to increase. For example, IBM PERSONALCO
With the introduction of MPUTER AT, the firmware has increased to require 32K bytes of ROM. I with micro-channel architecture
With the introduction of BM PERSONAL SYSTEM / 2, a very novel BIOS, called Enhanced BIOS or ABIOS, was developed. However, to maintain software compatibility, BIOS for Family 1 models
Was required to be included in the Family 2 model group. Family 1 BIOS has come to be called compatible BIOS or CBOIS. Accordingly, BIOS has evolved to include more than one type of BIOS, such as a compatible basic input / output system (CBIOS) and an enhanced basic input / output system (ABIOS). The current architectural definition of a personal computer system allows for a system firmware address space of up to 128 Kbytes.

At present, with the development of new technologies, personal computer systems are becoming more and more sophisticated,
It is being enhanced more frequently. As technology is changing rapidly and new I / O devices are being added to personal computer systems, implementing changes and enhancements to firmware has become a significant issue in the development cycle of personal computer systems. Was. In addition, maintenance of the firmware of the computer system located at the user site is also a problem.

A personal computer system is linked to a network (eg, a local area network).
Form a network or LAN, allowing users to exchange information, share input / output devices, and to access certain direct access storage devices (DASs), such as certain fixed disk storage devices.
D) can be used. Usually L
The AN includes “client” and “server”.
A client is a computer system that typically has no DASD other than a single diskette drive. The server includes a DASD for providing storage to a group of clients of the local area network;
It is a computer system. Clients may need to change, update, extend or maintain firmware.

As a result of these problems and requirements, and the desire to change firmware as soon as possible during the development cycle, the ability to change firmware with minimal disruption to the operation of personal computer systems. Is needed. In order for a personal computer system to be commercially viable and acceptable to consumers, new I / O devices can be added and costs should be kept to a minimum, so firmware can be easily changed. Is an essential factor in the successful sale of personal computer systems. Traditionally, in personal computer systems, system
At least a part of the firmware has been stored in the ROM. See, for example, U.S. Patent Application 398865. A major disadvantage of ROMs is that once a ROM is manufactured, its contents cannot be changed. For example, P
If the OST program code must be changed, the ROM must be physically changed. ROM
Has traditionally been socketed to allow for ROM replacement. However, on-site (ie, customer site) ROM replacement is time consuming and therefore expensive.

The ROM is electrically erasable and reprogrammable (ie, modifiable) non-volatile random access memory.
It is known to replace access memory (eg, flash memory) and store a POST or BIOS in it. For example, the Intel Corporation publication, "Memory Products 1991, Intel Order No. 210830,
ISBN 1-55512-117-9 ", Chapter 6 (Flash Memories, Chapter 6
See pages 1 to 6-420). This replacement allows the firmware to be easily changed.

However, it is necessary to efficiently maintain the integrity of the system firmware and at the same time, to make it possible to easily change the system firmware.

[0014]

SUMMARY OF THE INVENTION It is a primary object of the present invention to efficiently ensure the integrity of system firmware while allowing for easy firmware changes.

Another object of the present invention is to provide a personal computer.
Modifying the firmware of a computer system, while ensuring that the system has sufficient firmware to remain operational.

Another object of the present invention is to provide a personal computer.
The purpose is to allow automatic selection from multiple firmware banks in a computer system.

[0017]

SUMMARY OF THE INVENTION The present invention provides the above-described needs,
Developed to overcome requirements and problems. According to the present invention, an apparatus for storing firmware includes a plurality of non-volatile, changeable electronic memory devices electrically connected in a circuit arrangement in parallel with each other, and electrically connected to the memory device. Control means for controlling the memory device to enable reading and writing of firmware to one of the memory devices automatically selected. Each memory device can include the same or different versions of firmware. The redundant memory of the present invention ensures firmware integrity by write-protecting at least one of the memories. The present invention is an improvement of the invention disclosed in Japanese Patent Application No. 4-267959 filed by the same applicant.

[0018]

The following detailed description is of the best mode currently contemplated for carrying out the invention. This description should not be construed as limiting,
It has been done for the purpose of illustrating the general principles of the invention.

Referring now to the drawings, and more particularly to FIG. 1, there is shown a personal computer system 100 utilizing the present invention. The personal computer system 100 includes a system unit 102 having a suitable enclosure or casing 103, an output device or monitor 104 (such as a conventional video display),
An input device such as a keyboard 110, an optional mouse 112, and an optional output device such as a printer 114 are provided. Finally, the system unit 102
One or more mass storage devices, such as a diskette drive 108 and a hard disk drive (hard file) 106, may be included.

System unit 102 is responsive to input devices. A system unit 102 and optional input / output devices, ie, hard disk drives 106,
Diskette drive 108, keyboard 110, and monitor 104 can be connected to other system unit 102B in well-known fashion to form a local area network (LAN) as shown in FIG.
Usually, such other system unit 102B (client) does not include the hard disk drive 106 or the diskette drive 108. Of course, those skilled in the art will appreciate that other common input / output devices may be connected to and interact with system unit 102 or other system unit 102B.

In normal use, the personal computer system 100, as a server in a LAN, is designed to provide independent computing power to a small group of users or a single user so that individuals or small businesses can purchase it. The price is cheaper. In operation, processor 202 (FIGS. 3 and 5) functions under an operating system such as the IBM OS / 2 operating system or the DOS operating system. The operating system is loaded and stored in the system unit 102 in a conventional manner. Operating systems typically utilize a BIOS interface between input / output devices and the operating system. The BIOS, which is part of the firmware, is divided into optional modules by function (FIG. 18).
Please refer to). The BIOS provides an interface between the hardware device and the operating system so that a programmer or user can program his computer without detailed working knowledge of the specific hardware device. For example, BIOS
Allows a programmer to program a diskette drive without detailed knowledge of the diskette drive hardware. Thus, many diskette drives designed and manufactured by different companies can be used in the personal computer system 100. This not only reduces the cost of the system, but also allows the user to choose from a large number of diskette drives. BIOS is "IBM P
ersonal System / 2 and Personal Computer BIOS Interf
aceTechnical Reference 1988 ", which is more clearly defined.

(Integrated Planar) Referring to FIG. 3, a block diagram of the integrated planar 200 of the system unit 102 is shown. The integrated planar 200 includes a printed circuit board (PCB) 201 on which a plurality of input / output bus connectors 232 having input / output slots and a high-speed CPU local bus under the control of a bus control unit 214. The processor 202 connected to the memory control unit 256 by 210 is mounted or connected. The memory control unit 256 further includes a volatile random access memory (RAM) 2
64 is connected to the main storage device. Intel 803
86, Intel 80486, or any other suitable processor 202 can be used. System power connector 20
5 is attached to the PCB 201 and connected to a power supply (not shown) that supplies necessary power to the personal computer system 100.

The CPU local bus 210 (comprising address elements, data elements, and control elements)
02, interconnecting the optional math assist coprocessor 204, the optional cache control mechanism 206, and the optional cache memory 208. A system buffer 212 is also connected to the CPU local bus 210. The system buffer 212 itself
It is connected to a slower system bus 216 (compared to CPU local bus 210). System bus 2
Reference numeral 16 includes an address element, a data element, and a control element. The system bus 216 is connected to the system buffer 21.
2 and the input / output / buffer 228. The system bus 216 further includes a bus control unit 214
And a direct memory access (DMA) control unit 22
Connected to 0. DMA control unit 220 includes a central arbiter 224 and a DMA control mechanism 222.
I / O buffer 228 provides an interface between system bus 216 and I / O bus 230. Oscillator 207 is connected as shown and provides an appropriate clock signal to firmware subsystem 242. This preferred embodiment is based on the IBM well known in the art.
It will be appreciated by those skilled in the art that the present invention may be implemented on a Micro Channel bus in a PS / 2 computer system, but the alternative bus architecture may be used.

A plurality of I / O bus connectors 232 having slots for receiving adapter cards (not shown) are connected to the I / O bus 230. The adapter card may be further connected to input / output devices or memory (eg, hard disk drive 106). Although two I / O bus connectors 232 are shown for convenience, additional I / O connectors can be easily added to meet the needs of a particular system. An arbitration bus 226 couples the DMA control 222 and the central arbiter 224 to the I / O bus connector 232 and the diskette control 246. A memory control unit 256 is also connected to the system bus 216. The memory control unit 256 includes a memory control unit 258, an address multiplexer 260, and a data buffer 2
62 are included. The memory control unit 256 is further connected to a main storage device such as a random access memory represented by the RAM 264. Memory control mechanism 25
8 from the processor 202 to a particular area of the RAM 264 and from a particular area of the RAM 264 to the processor 20.
2 includes a logic circuit for performing address mapping. Personal computer system 100
Is shown with a base one megabyte of RAM 264, but it should be understood that additional memory can be interconnected by optional memory modules 266, 268, 270, as shown in FIG.

The buffer 218 is connected to the system bus 216
And a planar input / output bus 234. The planar input / output bus 234 includes an address element, a data element, and a control element. Along the planar input / output bus 234,
Display adapter 236 (used to drive optional monitor 104), clock 250, non-volatile RAM 2
48 (hereinafter referred to as NVRAM), serial adapter 24
0 (a common term used in place of "series" is
"Asynchronous" and "RS232"), parallel adapter 2
38, multiple timers 252, diskette adapter 2
Various I / O adapters and other peripheral components are coupled, such as 46, keyboard / mouse control 244, interrupt control 254, and firmware subsystem 242, which is the essence of the present invention. In accordance with the present invention, the firmware subsystem 242 includes a plurality (eg, 2
And non-volatile rewritable electronic memory devices. Each memory device stores a POST program and a BIOS program. POST includes the bank inspection / selection program section of the present invention. The firmware subsystem 242 and the remaining essential elements of the present invention are described below with respect to FIGS.

The clock 250 is used for time calculation. NVRAM 248 is used to store system configuration data. That is, NVRAM 248 holds values that describe the current configuration of personal computer system 100. NVRAM 248 holds, for example, information describing adapter card initialization data, fixed disk or diskette capacity, memory capacity, and the like. Further, these data are always stored in the NVRAM 248 when the configuration program is executed. This configuration program may be a conventional configuration program provided on a system reference diskette included with the IBM PS / 2 computer system. The system reference diskette may be referred to as a self-diagnostic diskette, a maintenance diskette, or a service diskette. The purpose of the configuration program is to store values representing the configuration characteristics of the personal computer system 100 in the NVRAM 248 and to save the values even when the system is turned off. NVRAM may be a low power CMOS memory with battery backup.

The keyboard / mouse control mechanism 244 includes:
Port A 278 and port B 280 are connected. Using these ports, a keyboard 110 and a mouse 112 can be connected to the personal computer system 10.
Connect to 0. A serial connector 276 is coupled to the serial adapter 240. Optional devices such as a modem (not shown) can be coupled to the system via this serial connector 276. A parallel connector 274 is connected to the parallel adapter 238. A device such as the printer 114 can be connected to the parallel connector 274. The diskette control mechanism 246 includes the diskette connector 28
2 are connected. Diskette connector 282 is 1
Used to connect one or more diskette drives 108.

Planar Board According to an alternative embodiment of the personal computer system 100, the integrated planar 200 is replaced by a planar board 300 (FIG. 4) and a processor card 400 (FIG. 5). Processor
The card 400 is detachably mounted on the planar substrate 300 and is electrically connected to the planar substrate 300. The same element numbers as those in FIG. 3 correspond to the same elements in FIGS. 4 and 5. Referring to FIG. 4, the planar substrate 30
0 comprises a printed circuit board (PCB) 301 upon which various components interconnected by wires or circuits within the PCB are mounted (eg, surface mounted). Such components include a suitable commercially available edge connector 302, into which the edge connector 416 of the processor card 400 is inserted when the processor card 400 is removed from the planar board 300. It can be mounted and electrically connected. Also, multiple single
Attach the in-line memory module (SIMM) connector 306 to the PCB 301 and
08A and 308B are connected to form a main storage device or main RAM of the system. Also, one or more input / output bus connectors 232 (or expansion connectors)
Attached to 301 connects various expansion adapters and options that are added to or incorporated into personal computer system 100. For example, the hard disk drive 106 is connected to the input / output bus connector 23.
2 can be connected to an adapter card (not shown) having a disk control mechanism. Each I / O bus connector 232 is preferably a commercially available connector of a type compatible with the Micro Channel architecture described above.

The interrupt control mechanism 25 connected to the port A 278 as a keyboard connector and the port B 280 as a mouse connector is provided on the planar board 300.
4 and a keyboard / mouse control 244, a diskette control 246 connected to a diskette connector 282, and a serial adapter 240 and a parallel connector connected to a serial connector 276 for connecting various input / output devices to the system. A parallel adapter 238 connected to 274 is also attached. To connect to a power supply (not shown) that supplies the necessary power to the system,
System power connector 205 is attached to PCB 301. NVRAM 248 and clock 250 are also PCB
Attached to 301. Also, on the PCB 301,
Also mounted are various oscillators (not shown) for providing timing signals, and buffers 342 and 344 (all not shown) for isolating portions of the circuit in a well-known manner.

The wiring of the PCB 301 interconnects the various components as shown, but includes the memory bus 310 (including the lines 324-338), the address bus 322, the data bus 320, and the control bus 318. )channel·
It is divided into three groups of buses 312 and other signal lines, including interrupt lines 314 and 316, all of which are connected via edge connectors 302 and 416 to P
It is connected to the corresponding wiring of CB401. A planar function bus 319 branches from the channel bus 312.

(Processor Card) Referring to FIG. 5, a processor card 400 removably mounted on a planar substrate 300 is shown. Processor card 400 includes a printed circuit board (PCB) 401
, On a PCB 401, a processor 202, an optional numerical coprocessor 204, an optional cache control mechanism 206, an optional cache memory 208, a DMA control unit 220, a bus control unit 214, and a memory control unit. A variety of commercially available components are attached (e.g., surface mounted), including 256, the firmware subsystem 242 and the parity check units 402, 404 of the present invention. The processor 202 is preferably a high performance type such as Intel 80486, which has a 32-bit data path and provides 32-bit addressing capability. of course,
Intel 80386 and similar processors can also be used. The remaining components are selected in a conventional manner to be compatible with such a processor. A plurality of buffers 406, 408, 410, 412, 414 are connected as shown. These buffers provide selective isolation or connection between circuits so that different portions can be used simultaneously to move data between, for example, processor 202 and cache memory 208, while input / output units and memory Enabling another data to be transferred between the banks 308A, 308B. All of the above components
Appropriate electrical connections are made to each other by a printed circuit in PCB 401 that terminates at edge connector 416.
The edge connector 416 is connected to the planar substrate 3 shown in FIG.
00, so that the planar board 300 and the processor card 400
Can be electrically and mechanically interconnected.

The wiring circuit of the PCB 401 includes a data line 4
20, a local bus 418 including an address line 422 and a control line 424 is included. Local bus 418
Interconnects the processor 202 to an optional numerical co-processor 204, an optional cache control mechanism 206, and an optional cache memory 208, as shown in FIG. The remaining circuit lines generally have
An interrupt line 316, a channel bus 312, and a memory bus 310 are included. Channel bus 312 includes control bus 318, data bus 320, and address bus 322. Memory bus 310 includes multiplexed memory address lines 324, 332, a row address strobe (RAS) line 328 for memory bank 308A, and a memory bus.
RAS line 336 for bank 308B, column address strobe (CAS) line 338, data bus A line 326,
Data bus B line 334 and parity check or E
Includes line 330 used for error checking using CC checking. Oscillator 207 is connected as shown and provides an appropriate clock signal to firmware subsystem 242. For simplicity, reset, ground, power on, and some other lines have been omitted from FIGS. 3, 4, and 5.

Personal computer system 1 having planar board 300 and processor card 400
During normal operation of the processor card 400, the processor card 400 is electrically and mechanically connected to the planar board 300, and is typically in a plane oriented generally perpendicular to the processor card 400.

(Firmware Subsystem) The system firmware performs a power-on self test (POST).
And a basic input / output system (BIOS) program. POST is a set of instructions that are executed when the system is first powered up. POS
The execution of T is performed by the personal computer system 10.
Critical for initialization of 0. Without POST, the system would not be able to use the operating system or other programs (eg, an update utility,
Program) cannot be loaded. A BIOS is a set of instructions that facilitates the transfer of data and control instructions between the processor 202 and an input / output device.

Referring now to FIG. 6, a block diagram of the firmware subsystem 242 according to the present invention is shown. In this figure, two memory banks, memory bank 0 502 and memory bank 1
504 is managed by the control device 505. Controller 505 controls the reading and writing of firmware from and to memory bank 0 502 and memory bank 1 504. The firmware subsystem 242 is connected to appropriate address, data, and control lines as shown in FIG. 3 or FIG. The memory bank 0 502 and the memory bank 1 504 are electrically connected in a parallel circuit arrangement to each other, and are also connected to the control device 505 as shown in FIG. This controller is
Memory bank 0 502 and memory bank 1 504
The selected one is always write-protected. Preferably, the complete firmware (ie, POST and BIOS required for the operation of the computer system) is stored in memory bank 0 502 and memory bank 1 504, respectively. POST contains a code part according to the invention. Such a code portion is shown in FIG.
Is a bank inspection / selection routine shown in steps 702 to 728 of FIG. The bank update code is part of the firmware update utility program (FIG. 17), but initially resides, for example, on a diskette (not shown). Receiving the diskette in diskette drive 108 allows the bank update code to be properly loaded into system unit 102. Further, the system unit 10
2 is connected as a server in the LAN as shown in FIG. 2, the client can appropriately load the update code from the system unit 102 which is a server. Such an update code causes a reprogramming of the selected memory bank 0 502 or memory bank 1504 with the updated firmware. Therefore, controller 505 operates in response to at least a signal generated by the bank test / select code or the bank update code.

FIG. 7 shows the firmware subsystem 2
FIG. 42 is a diagram showing 42 in more detail. Firmware subsystem 242 includes a plurality of (eg, two) in-circuit reprogrammable (ie, rewritable) non-volatile memory devices, memory bank 0 502 and memory
Bank 1 504 is included. Memory device or memory bank 0 502 and memory bank 1
504 is "Intel Memory Products 1991" No. 6-55
Intel28F010 on pages 6-80
It consists of semiconductors in the form of flash memory devices and the like. Intel 28F010 flash memory is
Provides 128 kilobytes of data storage capacity. The control device 505 in FIG. 6 includes signals WRSEL 508 and WAE 51
0, WRGATE 512, ALTBANK 514, FS
Input lines corresponding to EL516, SWR518, BSP520 and signals CE1522, CE0524, OE52
6, enable logic device 500 having output lines corresponding to WE 528, PVE 530, DC-DC converter 507 and switch 506, which are voltage generating mechanisms, and various input signals (WRSEL 508, WA) on input lines.
E510, WRGATE512, ALTBANK51
4, FSEL 516, SWR 518, BSP 520) (FIG. 7). These input signals are
As will be appreciated by those skilled in the art to which this specification pertains, bank inspection and selection codes, bank update codes, BS
Occurs in the P signal generator 600 or various hardware. Enable logic device 500 includes, for example,
This is a logic device “PAL16R8D” commercially available from Advanced Micro Devices, Inc. (AMD). At any given time, only active memory banks 0 5
02 or memory bank 1504. The enable logic of the enable logic device 500 determines which bank is active (active bank). Switch 506 is connected to memory
It controls a DC-DC converter 507 (converts + 5V to + 12V), which supplies a programming voltage Vpp to bank 0 502 and memory bank 1 504. Switch 506 is, for example, a transistor device “2N3904” available from Motolora, Inc. The DC-DC converter 507 is, for example, an Intern
a device "NMF0512S" commercially available from ational Power Sources, Inc. Memory bank 0
502 and memory bank 1 504 are connected to address and data lines, and WRSEL 508, WAE 510,
WRGATE512, ALTBANK514, FSEL
516, SWR 518 are connected to control lines in some manner well within the skill of the art (see FIG. 3 or 5). Parallel memory bank 0
502 and memory bank 1 504 can be permanently fixed to the PCB 201 and 401 substrates. This is because these memory banks can be reprogrammed as is, unlike the ROMs of previous computer systems with socket insertion. BSP 520 and P which are output lines of BSP signal generation mechanism 600
ROCESSOR RESET 604 will be discussed later with respect to FIG.

It should be noted that subsystems using only one memory bank of the Intel 28F010 flash memory are more susceptible to disabling. By its structure, a flash memory device cannot be reprogrammed without first being completely erased. flash·
If the computer system loses power while erasing memory or before reprogramming can be completed, a critical initialization program (PO
ST) is likely to be lost. Without POST, the system would not be able to "boot" and thus be unable to load and execute updates that would update the firmware in only one memory bank.

With continued reference to FIG. 7, a more detailed description of the enable logic device 500 will be provided. The enable logic device 500 has a write select bit or a write select signal (WRSEL) as an input. WRSEL
The signal is a bit obtained from the I / O control port and is used to enable writing to the selected memory bank 0 502 or memory bank 1 504. The control port used to supply the WRSEL signal is, for example, the memory control unit 2 of FIG. 3 or FIG.
It is a standard input / output port resident in 56. The control port is accessed using the "OUT" instruction of the Intel 86 family processor, which is well known in the art. WR
When SEL 508 is logic 0, writing is allowed. This WRSEL bit is under direct program control. Direct program control refers to steps 800-810 of the update utility program (see FIG. 17).
Is understood to be controlled by a program code, such as the bank update code of step No. and steps 702 to 728 of the bank inspection / selection code.

The write authority enable (WAE) bit (signal) 510 is a protection feature that prevents the bank from being reprogrammed. For example, the controller 505 can include a signal generation mechanism 534 (FIG. 8). The signal generating mechanism 534 comprises, for example, a three-position key switch and a source of appropriate potential (both not shown). One position of this switch is the OFF or Disabled position. The second position of this switch is ON,
No maintenance authority. The third position is ON with maintenance authority. Maintenance authority can be considered to be equivalent to "service mode" operation. In other words, this is the mode in which only qualified computer service technicians are allowed to perform certain tasks. The signal WAE will be enabled (eg, to a logic 0) by the switch only when the switch is in the maintenance authorized ON position. This allows the general user to use memory bank 05
02 and the contents of the firmware in memory bank 1 504 cannot be changed. Of course, WAE
510 can be controlled in a number of ways, and switches are just one example. The WAE signal may also be controlled by other logic in the computer system, which may include a programmed I / O port. In systems that do not wish to support this additional level of protection, the WAE signal will always be enabled.

Continuing with the discussion of the enable logic device 500, the write gate (WRGATE) 512 is
Or a hardware generated timing signal (active low) received from the memory control unit 256 of FIG. WRGATE is based on the aforementioned I
As described in the ntel28F010 flash device specification, and as shown in FIGS. 25 and 26,
Memory bank 0 502 and memory bank 1 504
To control the pulse width of the write enable signal (WE) 528 for writing to the memory. Alternate bank bit (ALTBANK) 51
4 selects an alternate bank when reading or writing (logic 0 = alternate bank). An alternative bank is BSP52
0 is the bank not selected. ALTBA
NK 514 is the memory control unit 2 of FIG. 3 or FIG.
56 and under direct program control. The bank selection / protection signal (BSP) 520 is shown in FIG.
As will be described in more detail with reference to FIGS. 15 through 15, this signal indicates which bank is the "base" bank,
Determine if bank or default bank (logic 0 = memory bank 0 502). The firmware select signal (FSEL) 516 becomes active when any firmware address is decoded during a read or write cycle. FSEL 516
Received from hardware, such as the memory control unit 256 of FIG. 3 or 5, and is active low. System read / write signal (SWR) 518 is a hardware generated timing signal that is high during a system write cycle and low during a read cycle. The SWR 518 is received from hardware such as the memory control unit 256 of FIG. 3 or FIG. Signal WR
GATE 512, FSEL 516, and SWR 518 are timing or control signals generated by hardware and are well understood in the art related to this specification.

Programming voltage enable output signal (PVE) 5 on the output line of enable logic device 500
30 controls the operation of the switch 506. PVE53
When 0 enables switch 506, DC-DC converter 507 is enabled and a +12 on line 532 is enabled.
V programming voltage Vpp is applied to memory bank 0 50
2 and memory bank 1 504. DC-DC
Converter 507 is connected to a source of potential (+ 5V) that is easily obtained within system unit 102. P
When the VE 530 disables the switch 506,
Memory bank 0 502 or memory bank 15
Writing to 04 is not successful. Intel28F010
Flash memory devices require + 12V to enable the reprogrammable or rewritable functions of the device.

The chip enable signals (CE1, CE
0), the output enable signal (OE) and the write enable signal (WE) are the input signals to the Intel 28F010 flash memory devices of memory bank 0 502 and memory bank 1 504. Tip ・
The enable 0 signal (CE0) 524 and the chip enable 1 signal (CE1) 522 are connected to the memory bank 0 50
2 and memory bank 1504 to determine which will be active. Each chip enable signal activates the control logic, input buffer, decode, and sense amplifiers of the device, as shown in FIG. 23, contained within the elements of the flash device. Output enable (OE) 526 is an input signal common to both memory bank 0 502 and memory bank 1 504 and enables reading of the active bank. The output enable (OE) activates the data output signal of the device during a read cycle. Write enable (WE) 528 is an input signal common to both memory bank 0 502 and memory bank 1 504;
Decide whether to allow data writing and when to allow it. The write enable signal controls writing to the control registers and arrays of the active bank.
Both of these signals (OE and WE) are gated inside the flash memory by the CE0 and CE1 signals. Therefore, reading and writing can only be performed on the active bank.

The enable logic device 500 is defined by the following set of equations used in the enable logic device 500 or other physical implementation (not shown). In the notation below, an underscore "_" is purely for the reader and means that the signal is active low. The notation used on the right side of the expression is that "!" Is a logical NOT, "&" is a logical AND, and "#" is a logical OR. "
! "Means active low when used on the left side of the equation. That is, when the value on the right becomes active, the signal on the left becomes active low. The formula is as follows:

! PVE_ =! WRSEL_ &! WAE! CEO_ =! FSEL_ &! BSP_ & ALTBANK_ #! FSEL_ & BSP_ &! ALTBANK_! CE1_ =! FSEL_ & CE0_! OE_ =! FSEL_ &! SWR_! WE_ =! FSEL_ & SWR_ &! ALTBANK_ &! WRSEL_ &! WAE &! WRGATE_

Although the above five equations fully describe the operation of enable logic device 500, it will be helpful to show some example calculations.

Example 1 Read operation for default (base) power-on bank (bank 0) (see row 1 of FIG. 9): First: SWR = 0, WRSEL = 1, WAE = 0, FSEL = 1, BSP = 0, ALTBANK = 1, W
RGATE = 1 Next: PVE = 1, CE0 = 1, CE1 = 1, OE = 1, WE = 1 Next: To start the read operation, FSEL = 0. SWR =
Since it is 0, a read operation is performed. Next: PVE = 1, CE1 = 1, WE = 1, CE0 = 0, OE = 0 After that, the data is valid until FSEL becomes 1.

Example 2 Write Operation for Bank 1 with Bank 1 Update Allowed (See Row 4 of FIG. 9): First: SWR = 0, BSP = 0, WRSEL = 1, WAE = 0, FSEL = 1, ALTBANK = 0, W
RGATE = 1 Next: PVE = 1, CE0 = 1, CE1 = 1, OE = 1, WE = 1 Next: WAE = 0, WRSEL = 0, then: PVE = 0 At this point, the system is designated Wait for the +12 V Vpp voltage (line 532) to stabilize during the time delay. Next: The processor 202 starts a write cycle of the desired data. Next: WRGATE = 0, SWR = 1, FSEL = 0 Next: CE0 = 1, WE = 0, PVE = 1, CE1 = 0, OE = 1 At this point, data is written until WRGATE becomes 1. It is.

See FIGS. 24, 25 and 26 for graphs of the waveforms of the various signals used to read from and write to a single flash memory device, eg, memory bank 1 504. I want to be. Further, the input signal BS to the enable logic device 500
See the table in FIG. 9 which shows the read and write conditions for memory bank 0 502 and memory bank 1 504 depending on P, ALTBANK, WAE.

Referring again to FIG. 7, memory bank 0
502 and memory bank 1 504 need not be physically separate parts. One part representing the logical function of the two banks, memory bank 0502 and memory bank 1 504, can be implemented as a single device. This part can be remounted for purposes such as cost reduction and board space reduction.

The BSP signal generator 600 of FIG. 7 determines which of memory bank 0 502 and memory bank 1 504 will be the “base” bank, cold start bank or default bank. .
The BSP signal generator 600 also includes a "timeout" function or means. The timeout function is P
Together with OST, it works to select the base bank. When the personal computer system 100 is first powered up, the BSP signal generator 600
By default, for example, memory bank 0 502
Is automatically selected as the base bank. POST is
If this setting is not "accepted" during a predetermined period of time, the hardware of the BSP signal generator 600 automatically changes the base bank selection to memory bank 1 504 and restarts the processor 202. . If the firmware in the current bank passes a validity check, such as a checksum (which must yield a predetermined value), the PO
ST states that the firmware is "acceptable".
ble) ". POST accepts BSP settings by canceling the timeout used to automatically execute a new selection. The timeout means will be described in more detail with respect to FIGS. 10, 11 and 13. This automatic reselection allows
The computer system 100 operates in memory bank 0
It is now possible to recover from an invalid firmware image in 502 or apply a write-protect setting to memory bank 1504 to
2 can be updated.

Referring now to FIG. 10, BSP 520
A schematic diagram of a BSP signal generator 600, which is a device that automatically generates signals, is shown. BSP signal generation mechanism 6
00 is a plurality of (for example, four) input lines (LOCK B
SP606, CANCELTIMEOUT608, PO
WER ON RESET610, CLOCK612)
And a plurality of (for example, two) output lines (BSP520, PSP
ROCESSOR RESET 604). Input line LOCK BSP606, CANCEL TIMEOU
T608, POWER ON RESET610, CL
OCK612 and output line PROCESSOR RESET
604 is suitably electrically connected to the control elements or lines of the planar I / O bus 234 (FIG. 3) or the local bus 418 (FIG. 5). The BSP signal generation mechanism 600
Various input signals LOCK BSP, CANCELTIM
EOUT, POWER ON RESET, CLOCK
Is also included. Two output signals, BSP52
0 and PROCESSOR RESET 604 are controlled by an automatic set / reset control device 602 as shown. The BSP 520 signal indicates to the enable logic device 500 of FIG. 7 which of the two available firmware banks should be selected as the “base” bank, cold start bank or default bank. PROCESSOR RESE
The T604 signal is connected to a control element or control line 424 of the planar input / output bus 234. PROCESSOR
The RESET 604 signal, when driven active,
The output signal indicates that the system processor 202 must be reset, but the rest of the computer system must not be reset. When the system processor 202 is reset, the processor 202 restarts execution from a defined location in the firmware subsystem 242. The automatic set / reset control device outputs signals LOCKBSP 606, C
ANCEL TIMEOUT608, POWER ON
RESET 610 and CLOCK 612 are input.
After a system reset, CANCEL TIMEOU
The T608 signal and the LOCK BSP606 signal are logic 0
Need to be LOCK BSP606 signal and CA
The NCEL TIMEOUT 608 signal is provided by the control portion of the memory control unit 256 and is under direct program control.

The LOCK BSP 606 has the current power-on
During the cycle, lock the BSP 520 output signal to the state in which it is currently defined. Once locked,
The BSP 520 signal cannot be changed unless the power to the automatic set / reset control device 602 is turned off and then turned on again. The locking of the BSP 520 signal is to ensure that only one of memory bank 0 502 and memory bank 1 504 can be changed during a single power-on session. This lock provides an additional level of system integrity. After locking the BSP520 signal,
The choice is fixed as to which bank becomes the “base” bank and is write protected. After the "base" bank has been selected, the non-base bank is the replacement bank. The CANCEL TIMEOUT 608 signal is
Cancel all currently active timeout sequences. This time-out sequence automatically changes the bank selection (via the BSP signal) and automatically restarts the processor, thus restarting the system initialization once again with a different bank of firmware. Provide a means. A valid POST cancels the timeout before it occurs, preventing a different bank from being selected. Invalid POS
T does not and cannot cancel the timeout, so the timeout means will select another valid firmware bank.
The POWER ON RESET 610 signal is an input generated from a system power supply (not shown). POWER
The R ON RESET 610 signal is driven active when the system power supply reaches the specified potential and remains active for a specified time so that all computer system components can be initialized. afterwards,
The POWER ON RESET 610 signal goes inactive and remains inactive unless system power is interrupted. Power supplies and their operation are common and well known. The CLOCK 612 signal is generated by an oscillator 207 running at a fixed frequency. A typical value for the frequency of CLOCK 612 is, for example, 25 megahertz.

FIG. 11 shows a preferred embodiment of the automatic set / reset control device 602 in more detail. The automatic set / reset control device 602 includes, for example, a BSP lock control logic circuit 614, a timer (counter) logic circuit 616, a toggle
A latch 618 and a reset pulse generation circuit 620 are included. Automatic set / reset control device 602
Internal signals are ENDRESET 605, INTERN
AL RESET 624, TIMEOUT 626, and RESTART 622. END RESET60
5 is an output of the reset pulse generation circuit 620,
Timer (counter) indicates completion of processor reset activity
Notify the logic circuit 616. INTERNAL RES
ET 624 is the output of the timer (counter) logic circuit 616 and, when active, the BSP lock control logic circuit 616
14 is used to initialize to a known state. TI
MEOUT 626 is the output of the timer (counter) logic, which when active, indicates to the BSP lock control logic 614 that a timeout has occurred and that a firmware restart sequence is required. RESTART 622 is the output of BSP lock control logic 614, which when active, causes toggle latch 618 to toggle the BSP 520 signal,
Therefore, it is a signal for generating PROCESSOR RESET 604.

In FIGS. 12, 13, 14 and 15, the system ground, which is logic 0, is connected to GROUND (GN
D), the system power supply which is logic 1 is indicated by Vcc. Referring to FIG. 12, the BSP lock control logic circuit 6
A schematic block diagram of 14 is shown. The BSP lock control logic 614 includes two standard J- @ K flip-flops 638 and 640 and one NOT gate (inverter) 642. Instead of the conventional overline notation indicating NOT or inversion, the notation is preceded by an overline "@". These elements, J- @ K flip-flops 638 and 640, and inverter 64
2 are connected as shown. The first J- @ K flip flop is POWER ON RESET 610
After the signal passes through inverter 642, POWER
Cleared by the ON RESET 610 signal. This initializes its Q output to a logic zero state. The J input is connected to the Vcc terminal to establish a logic 1 state, and the ￣K input is the feedback input from the Q output.
Connected to the loop. Therefore, POWER ON
Immediately after RESET 610, the $ K input goes to a logic zero state. According to the truth table of the J- @ K flip-flop (FIG. 27), after this state has been established at the J and @K inputs, the Q output upon receipt of a positive going transition of the LOCK BSP 606 signal. Is toggled, and thus Q changes to the 1 state. Further examination of the truth table for this J-￣K flip-flop shows that in this new state (J = 1, ￣K = 1), the Q output goes high even if there is a subsequent transition on the LOCK BSP 606 line. You can see that it is kept. Therefore, this J- @ K flip-flop 638 changes its state to (J = C) only by receiving an active input at its clear (CLR) input.
1, ￣K = 1) cannot be changed. This CLR input is
Derived directly from the POWER ON RESET 610 signal. Also note that the ￣Q output of this flip-flop follows as a logical inversion of the Q output. The ￣Q output of the first J-￣K flip-flop 638 is connected to the J input of the second J-￣K flip-flop 640. This J-￣K flip flop 64
A $ K input of 0 is connected to a logic high Vcc terminal, similar to a "preset" (PRE) input. Clock (C
LK) input is connected to the TIMEOUT 626 signal;
The clear (CLR) input is INTERNA as described above.
L RESET624 Connected to the signal line. Q output is
This is the signal START 622.

In operation, the J- @ K flip-flop 640 is initialized as a result of the INTERNAL RESET 624 signal. This establishes a logic zero state Q output (RESTART 622). J
The -￣K flip-flop 640 then asserts the clock input (TIMEOUT62) in one of the following two forms:
Respond to 6). If the J input is 1 (this is normal after a power-on reset), the rising edge of the TIMEOUT 626 signal will force the Q output to a logic 1 state, as shown in the truth table. This is another device,
Indicates that the state of RESTART 622 is active. However, if the J input is 0 at the time of the rising edge of the TIMEOUT 626 signal, the Q output remains at the current state 0.

These two flip-flops are shown in FIG.
2, the following operation of the BSP lock control logic 614 is established.

After TIMEOUT 626 transitions from low to high after POWER ON RESET 610 and before the LOCK BSP 606 transitions from low to high (0 to 1), a RESTART 622 is indicated.
All transitions of TIMEOUT 626 following the low to high transition of LOCK BSP 606 are ignored. L
R after OCK BSP 606 low to high transition
A POWER ON RESET 610 is required to make a low to high transition on the ESTART 622 line.

By this operation, LOCK BSP60
6 TIMEOUT as long as the signal remains inactive
It is established that the 626 signal can generate a RESTART 622 state. However, after the LOCK BSP signal transitions from low to high, POWER ON RE
The REST 622 line can no longer be activated unless the SET 610 signal resets the BSP lock control logic 614. The BSP lock control logic circuit 614 includes, for example, a J- @ K flip-flop 6
Texas Instruments SN74A for 38 and 640
Texas Instrume for LS109A and inverter 642
Includes commercially available standard TTL components such as nts SN74ALS04. Of course, equivalent logic circuits using other logic implementations, whether discrete circuits or VLSI components, may be utilized.

Referring now to FIG. 13, TIMEOU
A schematic block circuit diagram of a timer (counter) logic circuit 616 for generating a T626 signal is shown. This circuit comprises separate 8-bit binary resettable synchronous up counters 630, 632, 634, 636
And one two-input NOR gate 628. The four counters are connected in a standard cascade arrangement and tied together to act as a single 32-bit counter. NOR gate is POWERON
Combine the RESET 610 signal with the END RESET 605 signal. The output of this logic NOR is the INTERNAL RESET 624 signal used to reset the counter in timer (counter) logic 616 and is also the output of timer (counter) logic 616.
The counters 630, 632, 634, 636
Initialized to 0 by the RNAL RESET 624 signal via the respective 8-bit counter lines S0 and S1. Two additional inputs of these counters, @ENT
And $ ENP must be low to gate the counter on. @ENT input of each stage is CA
Connected to the NCEL TIMEOUT 608 signal. C
ANCEL TIMEOUT 608 effectively controls whether the counter is counting or not. The $ ENT inputs of the upper three stage counters 630, 632, 634 are connected to the previous stage ripple carry out (RCO). ￣ By combining ENT and RCO, a four-stage cascade connection is completed.

After exiting the reset state, these counters are stored in CL in standard binary counter format.
The output is incremented at the speed of OCK612. Thus, the least significant bit (or least significant bit LSB) is toggled at half the rate of the CLK clock input. Output bit Q
A is the least significant bit, QB is the next digit bit, and so on, bit QH is the most significant bit. Each higher bit is toggled at half the rate of the next lower bit. This operation is typical of a standard digital binary counter and is well known in the art.

TIMEOUT 626 uses this counter
Since it is connected to the 28th output bit of the array, 2 ²⁷ −
Goes active after one input clock. With 25 MHz CLOCK 612, TIMEOUT6
The output of 26 goes active in about 5.37 seconds. 5.3
The selection of 7 seconds is discussed in further detail with respect to FIG. At any point during the count operation, CAN
When the CEL TIMEOUT 608 input goes to a logic high level, the counting operation is postponed. The use of this signal is also discussed with respect to FIG. The timer (counter) logic circuit 616 includes, for example, four Texas Inst
ruments SN74ALS867 counter and one Texas
Instruments SN74ALS02 4x2 input NOR
Standard TTL components such as gates are included. Although these components are commercially available, equivalent logic circuits can be created from other logic implementations, whether discrete circuits or VLSI components, as is well known in the art. The counters shown here are synchronous, but this property is not critical either. For example, a ripple counter or other timing device may have a similar TIMEOUT
626 outputs can be generated. TIMEOUT 626 generated by the timer (counter) logic circuit 616
A specific count duration or signal duration of the signal,
Depending on the application, other counter outputs or combinations of counter outputs can be selected to achieve the desired results.

Referring now to FIG. 14, a schematic block diagram of the logic device of toggle latch 618 is shown. The logic device for toggle latch 618 includes standard J
-￣K flip-flop 646 and inverter 648 are included. As used herein, the J-￣K flip-flop is wired for toggle mode operation. The J input is connected to the Vcc node to establish a logic one input,
The K input is connected to GND to establish a logic 0 state. J- @ K flip flop 646 is POWER
It is cleared by a signal that is NOT of R ON RESET610. Therefore, the Q output (BSP 520 signal) is set to 0 after each power-on reset sequence.
Initially set to The toggle operation is performed by the RESTART 62
Occurs whenever a low-to-high (logic 0 to logic 1) transition occurs on two inputs. With this transition,
The Q output (BSP 520) is toggled to a logically opposite state. The logic device of the toggle latch 618 includes, for example, the Texas Instrument for the J- @ K flip-flop.
Includes standard TTL components such as Mentor's SN74ALS109A and Texas Instruments' SN74ALS04 for inverter 648. These parts are commercially available. Also, whether it is a discrete circuit or a VLSI component,
Obviously, equivalent logic circuits can be created from other logic implementations.

Referring now to FIG. 15, a schematic block diagram of the reset pulse generation circuit 620 is shown.
The logic circuit of the reset pulse generation circuit 620 is RES
When a signal due to the high state of the TART 622 input is received, a fixed width output pulse (PROCESSOR RES) is output.
ET604) is generated. Reset pulse generation circuit 6
20 includes, for example, a standard counter known in the art. The reset pulse generation circuit 620 also
For example, it includes an 8-bit resettable synchronous up counter 650. Counter 650 is clocked by the CLOCK 612 signal, as described above. RES
The TART 622 input, when low, clears this counter to zero counts. Thereby, the QF output E
Note that ND RESET 605 is also cleared to a low state. When RESTART 622 is high, this counter is enabled to count up.
This counter starts counting when the RESTART 622 input goes high. 2 ⁴ after the clock (16 clocks), QE output (PROCESSOR RESET
604) goes high. This output remains at this high state for an additional 16 clocks. After a total of 32 clocks, the QE output goes low and the QF output, END,
RESET 605 goes high. END RESET6
Recall that 05 notifies the timer (counter) logic 616 of FIG. 11 of the completion of the processor reset activity. The logic circuit of the reset pulse generation circuit 620 includes, for example, Texas Instruments S for a counter.
Standard TTL components such as N74ALS867 are included.
This part is commercially available. It is also apparent that other logic implementations, whether discrete circuits or VLSI components, can be used to implement equivalent logic circuits, as is well known in the art.

(Explanation of Operation) Next, four cases explaining the operation of the firmware subsystem 242 will be discussed. The first case 1 is the same program
The personal computer system 100 includes memory bank 0 502 and memory bank 1 504, two firmware banks containing code images (ie, identical firmware). This is a typical case when the personal computer system 100 is manufactured. Referring now to the flowchart of FIG. 16, the initialization of the personal computer system 100 will be described, but only those activities related to the operation of the firmware subsystem 242 will be discussed. Case 1
Describes the normal activities that take place in a properly configured system. First, the personal computer system 100 is powered on and the processor 202 begins an attempt to retrieve program code from a predetermined address in memory bank 0 502. The processor 202 obtains the program code from memory bank 0 502 because the firmware is mapped into this predetermined address space and memory bank 0 502 is the default active bank at power-on. Since Case 1 describes a correctly configured system, processor 202 may be able to access memory bank 0 502
Succeeded in obtaining the POST program code from.
POST performs some preliminary initialization at step 700, such as checking the status of processor 202.
The type and scope of this early test is a matter of design choice.

After the early initialization in step 700, P
The OST checks the BSP bit in step 702,
Check if it is locked. A locked BSP indicates that the system is already powered on and is simply re-entering POST. If the BSP is locked, bank selection has already been completed and POST proceeds to step 730. However, since Case 1 describes a normal power-on sequence, the BSP lock check in step 702 should show that the BSP is not locked. Next, POST reloads memory bank 0 502
Check for validity. In step 704, the memory
The validation for bank 0 502 may be a checksum procedure (which must yield a predetermined value). For example, an 8-bit running sum of each byte in the firmware image can be calculated and compared to 0, and if it is found to be 0,
The firmware image is considered valid. Another form of validation is a cyclic redundancy check (CR
C). If any validation is used, the type is a well-known design choice.

If the firmware in memory bank 0 502 is found to be invalid,
ST stops and the automatic set / reset control device 60
Two logic circuits toggle to memory bank 1 504,
Wait for the processor 202 to restart. If memory bank 0 502 is found to be valid, POST
In step 706, the timeout is canceled. POST
Cancels the timeout by setting CANCEL TIMEOUT 608, but this is done via an I / O port that is directly under program control. The timeout value of 5.37 seconds is POST
Has been selected to start execution from reset, check the validity of the firmware bank, and if necessary, cancel the timeout. Next, POST checks in step 708 whether the contents of NVRAM are valid. Again, a checksum or other procedure can be used to verify that the data stored in NVRAM is valid. If, at step 708, the contents of the NVRAM are found to be invalid, a configuration error exists (step 720) and the system proceeds to step 716, where the BSP signal is locked. The BSP signal is locked by setting the LOCK BSP 606 bit, which is done via an I / O port that is directly under program control.

If the contents of the NVRAM are found to be valid at step 708, a check is made as to whether the updated phase indicator (described in detail below) stored in the NVRAM is a value of zero. If the update phase indicator is found to be 0 in step 710, POST initializes a small section (64K) of system RAM and returns to memory bank 050.
The portion of code 2 corresponding to steps 712, 714, 728 is copied into that small section of system RAM. POST in memory bank 0 502 then:
Control transfers to POST for this small section in system RAM. Next, the PO in the system RAM shown in FIG.
The ST code determines in step 712 that memory bank 1
Check 504 for validity. Memory bank 15
If 04 is not valid, there is a firmware bank error (step 728) and POST proceeds to step 716 to lock the BSP signal. Step 71
If memory bank 1 504 is valid at 2, then at step 714, memory bank 0502 and memory bank 1
Compare 504 version code. This version comparison can be, for example, a version number, sequence number, or data value comparison. The nature of the version tracking means is a well-known design choice. One useful version code is all IB
This is a date included in a fixed position near the end of the firmware image adopted in the M personal computer.

If the firmware in memory bank 1 504 is found to be newer than the firmware in memory bank 0 502, this is also the firmware bank
Error (step 728). This is an error because the Update-Phase indicator was not in a state that allowed the firmware in memory bank 1 504 to be newer than the firmware in memory bank 0 502. If it is determined in step 714 that memory bank 1 504 is not newer than the firmware in memory bank 0502, in step 716 the BSP signal is locked and step 730
The POST proceeds to system initialization. Step 71
Once the BSP signal is locked at 6, the BSP signal will not be changed during the rest of the computer system operation.
The BSP signal can be changed again when the system is turned off and then turned on.

Case 2 is a case where the firmware of the memory bank 0 502 is destroyed or determined to be invalid by POST. Memory bank 0 502, such as when the update operation was interrupted by a power outage
If the firmware does not include the program code, the timeout cancellation of step 706 is not performed. As a result, the automatic set / reset control device 602 automatically selects memory bank 1 504 and automatically resets the processor 202. If memory bank 0 502 contains some POST code but is not totally valid, steps 700, 702, 704 and 718 described above are performed.

Case 3 is a case where the firmware of the memory bank 1 504 is destroyed or determined to be invalid by POST. In this case, step 70
0, 702, 704, 706, 708, 710, 71
2, 728, 716, 730.

Since Case 4 relates to the update phase indicator, the outline of the update operation will be described before proceeding to Case 4. Update is 2
Occurs in two basic phases. Phase A is for memory bank 1
The phase at which the firmware of 504 is updated, and the phase B is the phase at which the firmware of the memory bank 0502 is updated. The update phase indicator stored in NVRAM is used to track the progress of the update procedure and the PO
Used by both ST and updates. When the update phase indicator equals 0, the system is not currently performing an update operation. When the update phase indicator equals 1, the update program has completed programming memory bank 1 504 with the new firmware. When the update phase indicator equals 2, POST has locked memory bank 1 504 and memory bank 0 50
2 is ready to accept updates.

The operation of the update procedure will be described with reference to FIG. Understanding FIG. 17 will help explain FIG. 16 and the remaining Case 4. When running, the update program checks at step 800 whether the contents of the NVRAM are valid. If the contents of the NVRAM are not valid, the user is instructed to modify the NVRAM at step 812, after which the update procedure can continue. N
The VRAM "fix" can be achieved by running a well-known setup program distributed on the reference diskette of all PS / 2 systems. The setup program is, for example, "IBM Per
sonal System / 2 Hardware Interface Technical Refere
nce Architectures ", pages 1-54. If the contents of the NVRAM are invalid, the update program ends at step 822. At step 800, the NV
If the contents of the RAM are found to be valid, step 80
At 2, check whether the update phase indicator has a value of 0. If the update phase indicator is 0, the update program can proceed to step 804, where the alternative bank is reprogrammed. Thereafter, the update program sets the update phase indicator to 1 in step 806,
Indicates that phase A (described above) has been completed. Thereafter, the update program provides the user with a personal
Instruct the computer system 100 to power off and then on, stop at step 810, and wait for the user to power off the system.

Returning to FIG. 16, case 4 will now be described. If the update phase indicator is equal to one, steps 700, 702, 704, 706, 708 are performed as previously described. At step 710, it is determined that the updated phase indicator is other than zero, and control proceeds to step 722. Step 722 checks whether the updated phase indicator has a value of one. In this case, the update phase indicator is 1, so
At step 724, the update phase indicator is set to a value of two. The POST then starts and stops the timeout device at step 726 and waits for the computer system to be restarted by toggling the BSP 520 bit. After the system is reset and POST is restarted, steps 700, 702, 704, 706, 7
08 and 710 are executed again. In step 722,
The update phase indicator is not equal to one, so that control transfers to step 716 and the BSP is locked, thus:
Memory bank 1 504 is established as write protection and memory bank 0 502 is established as a replacement bank.

Referring again to FIG. 17, the update program is executed again. This is because the update phase indicator requires further update processing. When POST determines that an update procedure is in progress, it requires a boot with a system reference diskette to complete the update operation. At step 800, the contents of the NVRAM are found to be valid. At step 802, the updated phase indicator is checked, but since the updated phase indicator is two,
It is determined that it is not 0. Next, at step 816, the updated phase indicator is checked for a value of two and found to be two.
If the update phase indicator is not 2, the process proceeds to step 814, where the update phase indicator is reset to 0 and the update procedure is restarted. If the update phase indicator equals 2 in step 816, the process moves to step 818, where an alternate bank, currently memory bank 0 502, is programmed with the firmware image. Next, at step 820, the update phase indicator is set to 0 to indicate that the update phase is complete. Thereafter, the update program ends at step 822. There is no need to restart the computer system at this point. Because memory bank 1 504
Is the same as the firmware of the memory bank 0 502. Memory bank 0 502 stores B after the next power-on cycle.
The bank is selected by the SP520 signal. Finally, the proper coding of all of the steps shown in FIGS. 16 and 17 is well within the skill of the art to this specification.

Firmware Subsystem 2 of the Present Invention
42 is also useful during the development of the computer system. Using firmware in an erasable programmable read-only memory (EPROM) requires that each firmware revision be programmed or "burned" into the EPROM. The procedure for burning an EPROM involves first placing the correct type of EPROM in a special erasing device and then erasing by UV exposure. The time required for erasing the EPROM is not fixed, but may take 10 minutes or more. Thereafter, the erased EPROM must be placed in another special device called an EPROM programmer. Then, the new firmware program code is transferred to this EPR
It must be loaded into the OM programmer, which is often a time consuming operation. Then, EPR
The OM programmer must be instructed to transfer or burn the loaded firmware code to the EPROM device. This operation takes an additional 10 minutes or more. Thereafter, the EPROM device must be removed from the EPROM programmer and inserted into the system under test. To insert a new EPROM, the old EPROM currently in the system must be removed. The process of removing and inserting these devices sometimes causes hardware damage. The firmware subsystem 242 of the present invention typically takes less than 15 minutes to complete the reprogramming of the alternate bank,
It should be understood that it is available in a system development environment and is a significant improvement over the state of the art EPROM.

While the present invention has been described, it will be appreciated by those skilled in the art that various changes may be made in details without departing from the spirit, scope and teachings of the invention.
For example, while the preferred embodiment uses an Intel processor and an IBM PS / 2 Micro Channel bus for illustrative purposes, the invention may be implemented with other processors or other bus types. Similarly, those skilled in the art will recognize that many elements of the invention can be implemented in hardware or software. Therefore,
The invention is limited only as specified by the appended claims.

[Brief description of the drawings]

FIG. 1 illustrates a typical personal computer system.

FIG. 2 illustrates a typical local area network.

3 is a schematic block diagram of an integrated planar substrate for the computer system of FIG.

FIG. 4 is a schematic block diagram of an alternative planar board for the computer system of FIG.

FIG. 5 is a schematic block diagram of a processor card for use with the alternative planar board of FIG.

FIG. 6 is a schematic block diagram of a firmware subsystem according to the present invention.

FIG. 7 is a schematic block diagram of the preferred embodiment of the present invention shown in FIG.

FIG. 8 is a block diagram of a generation circuit for generating a write right enable (WAE) signal.

FIG. 9 shows the read mode and the write mode of the device of FIG.
It is a table shown in association with main control input signals (BSP, ALTBANK, WAE).

FIG. 10 shows a BSP of an enable logic device of the control means.
Produces a signal at the input, the PROC of the system processor
A device for generating a signal at the ESSOR RESET input,
It is a schematic block diagram.

FIG. 11 is a more detailed schematic block diagram of the signal generation mechanism of FIG.

FIG. 12 is a more detailed schematic block diagram of the BSP lock control logic of FIG. 11;

FIG. 13 is a more detailed schematic block diagram of the timer (counter) logic circuit of FIG.

FIG. 14 is a more detailed schematic block diagram of the toggle latch of FIG. 11;

FIG. 15 is a more detailed schematic block diagram of the reset pulse generation circuit of FIG. 11;

FIG. 16 is a flowchart of a power-on procedure applied to the firmware subsystem.

FIG. 17 is a flowchart of a system firmware change procedure.

FIG. 18 is a memory map of exemplary firmware stored in the memory device of FIG.

FIG. 19 is a flow chart of erasing the Intel 28F010 flash memory.

FIG. 20 is a flowchart of erasing the Intel 28F010 flash memory.

FIG. 21 is a flowchart of programming of Intel 28F010 flash memory.

FIG. 22 is a flowchart of the programming of the Intel 28F010 flash memory.

FIG. 23 is a block diagram of an Intel 28F010 flash memory.

FIG. 24 is a diagram showing signal waveforms of a read operation of the Intel 28F010 flash memory.

FIG. 25 is a diagram showing signal waveforms of an erasing operation of the Intel 28F010 flash memory.

FIG. 26 is a diagram showing signal waveforms of a programming operation of the Intel 28F010 flash memory.

FIG. 27 is a truth table for a J-ΔK flip-flop device, specifically, Texas Instruments SN74ALS109A.

[Explanation of symbols]

 242 Firmware subsystem 248 Non-volatile RAM (NVRAM) 500 Enable logic device 502 Memory bank 0 504 Memory bank 1 506 Switch 507 DC-DC converter 600 BSP signal generation mechanism 602 Automatic set / reset control device 614 BSP lock control logic Circuit 616 Timer (counter) logic circuit 618 Toggle latch 620 Reset pulse generation circuit

Continued on the front page (72) Inventor Richard Bearkovski United States 33444, Hummingbird Drive, Delhi Beach, Florida 1401 (72) Inventor Ralph Mari Vigan United States 33486, Boca Raton, Florida, South West 19th Street 1380

Claims (2)

(57) [Claims] 1. A computer system, comprising:
Stores different versions of firmware in two memories
Firmware storage method for redundant storage in banks
(A) one of the two memory banks;
While the other memory bank is selected, write the other memory bank
(B) first selecting one of the two memory banks
(C) not selected in the first selection step
Validity of firmware stored in a failed memory bank
And (d) the memo selected in the first selection step.
Of the firmware stored in the rebankversion
Was not selected in the first selection step
Of the firmware stored in the memory bankVersion
NAnd generating the comparison result; and (e) according to the comparison result, the two memory banks
Select one of the firmware stored in
(F) the memo selected in the second selecting step
Using firmware stored in the rebank
Computer system and start the computer within a predetermined time.
The computer system does not operate properly
In the second selection step, it was not selected
Select memory bank, then reset processor
Performing the steps of:
Firmware storage method. 2. A computer system, comprising :
Stores different versions of firmware in two memories
A firmware storage device that stores data redundantly in banks.
I, (a) one of the memory-Bains said two memory banks
While the other memory bank is selected, write the other memory bank
(B) a first means for selecting one of the two memory banks
And selecting means, main that is not selected in (c) said first selection means
Check the validity of the firmware stored in the memory bank.
Means for Ekku, memory selected in; (d) first selection means
Update the firmware version stored in the bank to
The memory bank not selected by the first selecting means.
Link with the firmware version stored in the link
Means for generating the comparison result; and (e) the two memory banks according to the comparison result.
Select one of the firmware stored in
A second selection means for, memory selected in (f) said second selection means
Computer using firmware stored in the bank.
Start the data system and within a predetermined time,
If the data system does not operate properly,
A memory not selected by the second selecting means;
Means for selecting a bank and then resetting the processor
And a computer system file characterized by including
Firmware storage.