JP3017133B2 - Level shifter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved level shifter circuit.

[0002]

2. Description of the Related Art A semiconductor integrated circuit can easily have a free circuit configuration depending on the application and the like, and an optimum power supply voltage is selected. Further, the diversification of power supply voltages has been progressing, for example, a low power consumption section and a high speed operation section are incorporated in the same system.

Therefore, when an arbitrary device is configured by combining a plurality of semiconductor integrated circuits, input signals to be processed by the integrated circuits in different power supply systems,
The level of the output signal that has been subjected to signal processing in the integrated circuit greatly differs depending on each circuit. Usually, circuits are directly connected depending on required characteristics and manufacturing conditions. Therefore, level adjustment is performed using a level shifter circuit between the circuits.

A conventional level shifter circuit will be described. FIG. 5 is a diagram showing an example of a conventional level shifter circuit, and FIGS. 6 and 7 are waveform diagrams of each node of the conventional level shifter circuit.

[0005] IN is an input terminal, OUT is an output terminal, VD
D1 is a first power supply, VSS is a second power supply and is a ground power supply,
DD2 is a third power supply, INV11 and INV12 are inverters, 11 and 12 are P-channel MOS transistors,
13 and 14 are N-channel MOS transistors;
1, 152, 153 and 154 are nodes. here,
VDD1 has the same potential as the power supply of the circuit that generates the input signal to the input signal IN, and has a lower potential than VDD2. For example, VDD1 supplies a potential of 2.0V, and VDD2 supplies a potential of 5.0V.

FIG. 5 shows a circuit configuration of a conventional level shifter circuit.
This will be described below. First, an inverter INV11 for shaping the waveform of an input signal is provided at the input terminal IN, and the inverter INV11 is provided.
11 for generating an inverted signal at the output terminal
Connect NV12. Then, a complementary signal is formed by the output signal of each inverter. Further, the gates and drains of the two P-channel MOS transistors 11 and 12 are crossed, and the drains are connected to the drains of N-channel MOS transistors 13 and 14 whose sources are grounded.

The aforementioned complementary signal is input to the gates of the two N-channel MOS transistors 13 and 14, and the drains of the P-channel MOS transistors 11 and 12 and the N
An N-channel MOS transistor 1 in which an inverted signal of an input signal is connected to a gate among two contacts commonly connected to the drains of the channel-type MOS transistors 13 and 14.
4 is connected to the output terminal OUT.

At this time, the inverters INV11, INV11
A level shifter circuit can be realized by connecting VDD1 to 12 and connecting VDD2 to the sources of the two crossed P-channel MOS transistors.

Next, the operation will be described with reference to the waveform diagrams of the respective nodes in FIGS. The input signal is VSS
Level (hereinafter abbreviated as L level) and VDD1 level (hereinafter abbreviated as H level). First, the state of each node and transistor when the input signal IN is at the L level will be described.

The node 153 goes high, the node 154 goes low, and the N-channel MOS transistor 14
Is OFF, N-channel MOS transistor 13 is ON
And the node 151 goes to the L level, the P-channel MOS transistor 12 turns ON, and the node 152 goes to the VDD2 level (hereinafter abbreviated to the HH level).
The P-channel MOS transistor 11 is turned off,
The output signal OUT becomes HH level.

When the input signal IN is at the H level, the state of each node and transistor is L level at the node 153, H level at the node 154, the N-channel MOS transistor 14 is ON, and the N-channel MOS transistor is ON.
The transistor 13 is turned off, the node 152 becomes L level, and the P-channel MOS transistor 11
N, the node 151 goes to the HH level, the P-channel MOS transistor 12 turns off, and the output signal OUT goes to the L level.

Next, a change in the potential of each node and a change in the state of the transistor when the input signal IN changes from the H level to the L level will be described with reference to FIG.

The node 153 changes from L level to H level, the node 154 changes from H level to L level,
N-channel MOS transistor 13 is turned on from OFF
And the N-channel MOS transistor 14 is turned on.
To OFF.

At this time, node 151 is a P-channel type M
The OS transistor 11 receives the potential of the node 152 and
Since the transition from N to OFF is delayed with respect to the transition of the N-channel MOS transistor 13, the voltage value gradually decreases with the transition of the N-channel MOS transistor 13 to ON, and the P-channel MOS transistor 12 is turned from OFF to ON. The node 152 changes from the L level to the HH level, and the P-channel MOS transistor 11
The signal changes from N to OFF, and the output signal OUT changes from L level to HH level.

A change in the potential of each node and a change in the state of the transistor when the input signal IN changes from the L level to the H level will be described with reference to FIG.

The node 153 changes from H level to L level, the node 154 changes from L level to H level,
N-channel type MOS transistor 13 is turned off from ON
And the N-channel MOS transistor 14
The state changes from F to ON.

At this time, the node 152 is a P-channel type M
The OS transistor 12 receives the potential of the node 151 and
Since the transition from N to OFF is delayed with respect to the transition of the N-channel MOS transistor 14, the voltage value gradually decreases with the transition of the N-channel MOS transistor 14 to ON, and the P-channel MOS transistor 11 changes from OFF to ON. The node 151 changes from the L level to the HH level, and the P-channel MOS transistor 12
The signal changes from N to OFF, and the output signal OUT changes from HH level to L level.

That is, in the conventional level shifter circuit, as described above, the N-channel MOS transistors 13 and 14 are turned ON at the potential of VDD1,
The transition of the P-channel MOS transistors 11 and 12 to the OFF state is performed by receiving the potentials of the nodes 151 and 152, which are the drains of the N-channel MOS transistors 13 and 14 turned on at the potential of the VDD1, at the gates. The P-channel type MOS transistors 11 and 12 are
Until transition to the FF state, the nodes 151 and 152
It is determined by the ON resistance values of the channel type MOS transistors 11 and 12 and the N channel type MOS transistors 13 and 14, and the smaller the resistance value of the N channel type MOS transistors 13 and 14, the more easily the nodes 151 and 152 shift to L level. , P-channel MOS transistors 11 and 12
Easily transition to the OFF state, and the transition of the output signal OUT becomes faster.

[0019]

The above-mentioned conventional level shifter circuit has been developed in accordance with the diversification of the number of power supplies.
And the voltage value of VDD2 is increasing. Then, there is a problem that the transition of the output signal OUT is delayed.

The reason is as follows. The transition of the potential of the node 151 or 152 is as follows. First, the N-channel MOS transistor 13 or 14 is turned on, and the P-channel MOS transistor connected to the drain of the turned-on N-channel MOS transistor 13 or 14.
It is determined by the resistance division of the ON resistance value of the transistor 11 or 12 and the potential of the node 151 or 152 turns on the P-channel MOS transistor 11 or 12 to determine the output.
The lower the ON resistance value of the S transistors 13 and 14 is, the easier it is to determine the potential of the node 151 or 152. However, when VDD1 becomes a low voltage, the N-channel MOS transistor 1 transitions to the ON state at the potential of VDD1.
3 and 14 have a large ON resistance value, and have a P-channel type MO.
The difference between the ON resistances of the S transistors 11 and 12 increases, and the transition of the levels of the nodes 151 and 152 determined by the resistance division is delayed, and the output of the level shifter is delayed.

An object of the present invention is to provide a circuit in which when the difference between the voltage values of VDD1 and VDD2 becomes large, the H level of the nodes 151 and 152 becomes high.
It is an object of the present invention to provide a level shifter circuit that controls a transition to an H level or a transition to an L level to speed up the transition of the output signal OUT.

[0022]

In order to achieve the above object, the present invention provides a first inverter connected to an input terminal, which is supplied with a voltage of a first power supply and shapes a waveform of an input signal. A second inverter supplied with a power supply voltage and generating an inverted signal is connected to an output terminal of the first inverter, and a second power supply is connected to sources of first and second MOS transistors of the first conductivity type. And a first and a second of the first conductivity type.
The gate and drain of the MOS transistor are crossed, and the drains of first and second MOS transistors of the second conductivity type, the sources of which are grounded, are connected to the respective drains, and the output terminal of the first inverter is connected to the output terminal of the first inverter. The gate of the first MOS transistor of the second conductivity type is connected to the second MOS transistor.
, The gate of a second MOS transistor of the second conductivity type is connected to the output terminal of the inverter, and the drains of the first and second MOS transistors of the first conductivity type are connected to the first and second MOS transistors of the second conductivity type. In a level shifter circuit having, as an output terminal, the side connected to the drain of the second MOS transistor of the second conductivity type, of the two contacts commonly connected to the drains of the two MOS transistors, the voltage of the first power supply is changed. And an input connected to the output of the second inverter, and an output connected to the first capacitor of the first conductivity type through the first capacitor.
A third inverter connected to the gate of the OS transistor; a first power supply voltage; an input connected to the output terminal of the first inverter; and an output connected to the first conductive element via the second capacitor. And a fourth inverter connected to the gate of the second MOS transistor of the type.

According to the present invention, P
The gate of the channel MOS transistor is positively pressurized, the gate of the P-channel MOS transistor to be turned on is positively depressurized, and the resistance of the N-channel MOS transistor connected to the drain of the P-channel MOS transistor is increased. It assists the transition of the resistance value of the P-channel MOS transistor with respect to the value.

More specifically, P which determines the state of the output
It has a capacitor for increasing or decreasing the gate potential of the channel type MOS transistor by the Miller effect, and an inverter having a delay value for effectively applying the pressure increasing or decreasing by the Miller effect of the capacitance.

[0025]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are circuit diagrams showing an embodiment of the level shifter circuit of the present invention.
6 is a waveform diagram of each node of the level shifter circuit.

IN is an input terminal, OUT is an output terminal, VD
D1 is a first power supply, VSS is a second power supply and is a ground power supply,
DD2 is a third power supply, 1 and 2 are P-channel MOS transistors, 3 and 4 are N-channel MOS transistors,
C1, C2 are capacities, 100, 101, 102, 103,
104 and 105 are nodes.

A first embodiment of the present invention will be described with reference to FIG.

The basic circuit configuration is the same as that described in the prior art. The difference is that the inverters INV3 and INV4 are provided with VDD1 for branching complementary signals generated from input signals and providing a minute delay value.
Connect. Then, the output terminals of the inverters INV3 and 1NV4 and the two P-channel MOS transistors 1 and 2
2 is connected to the second gate via capacitors C1 and C2.

At this time, the connection between the capacitors C1 and C2 is also connected to nodes 100 and 101 which are the contacts between the drains of the two N-channel MOS transistors 3 and 4 and the drains of the two P-channel MOS transistors 1 and 2. ing.

Here, the minute delay value of the inverters INV3 and INV4 is adjusted to the timing at which the potentials of the nodes 100 and 101 become unstable, and the delay value of the level shifter is efficiently increased by the coupling effect of the capacitors C1 and C2. It has a value to speed up.

Next, a second embodiment of the present invention will be described with reference to FIG.

The difference from the first embodiment is that the inverters INV3 and INV4 are connected in series to one of the complementary signals generated from the input signals, and the coupling of the capacitors C1 and C2. Inverter I for speeding up the delay value of the level shifter more efficiently by the effect
It is an example of a connection method for realizing the delay values of NV3 and INV4.

The state of each node and transistor will be described below with reference to the waveform diagrams of each node in FIGS. The input signal is such that the first signal is the L level of the VSS level and VD.
It changes between H levels of D1 level. First, the state of each node and transistor when the input signal IN is at the L level will be described.

Node 104 is at H level, node 105 is at L level, node 103 is at L level, and node 102 is at H level.
Level, and the N-channel MOS transistor 4
The FF and N-channel MOS transistor 3 are turned on, the node 100 is at L level, and the P-channel
The S transistor 2 is turned on, the node 101 is at the HH level, and the P-channel type MOS transistor 1 is
F, and the output signal OUT becomes HH level.

The state of each node and transistor when the input signal IN is at the H level will be described.

Node 104 is at L level, node 105 is at H level, node 103 is at H level, and node 102 is at L level.
Level, and the N-channel MOS transistor 4
The N- and N-channel MOS transistors 3 are turned off, the node 101 is at L level, and the P-channel
The S transistor 1 is turned ON, the node 100 is at the HH level, and the P-channel MOS transistor 2 is
F, and the output signal OUT becomes L level.

Next, referring to FIG.
A change in the potential of each node and a change in the state of the transistor when the level changes from the L level to the L level will be described.

The node 104 changes from L level to H level, the node 105 changes from H level to L level,
The N-channel MOS transistor 3 changes from OFF to ON, and the N-channel MOS transistor 4 changes from ON to OFF.

At this time, the node 100 is a P-channel type M
OS transistor 1 is turned on in response to the potential of node 101
From OFF to the OFF state, the voltage value gradually decreases as the N-channel MOS transistor 3 changes to ON, and the P-channel MOS transistor 2 changes from OFF to O.
The node 101 changes from L level to HH level, the P-channel MOS transistor 1 changes from ON to OFF, and the output signal OUT changes from L level to HH level.

At this time, the node 103 changes from the H level to the L level with a delay after the transition of the node 104, thereby changing the potential at one end of the capacitor C2, and the other end is connected due to the coupling effect of the capacitor. By lowering the potential of node 100, the transition of P-channel MOS transistor 2 to ON is assisted.

The node 102 changes the potential at one end of the capacitor C1 from the L level to the H level with a delay after the transition of the node 105, and changes the potential at one end of the capacitor C1 due to the coupling effect of the capacitor. By boosting the potential of 101, the transition of the P-channel MOS transistor 1 to OFF is assisted.

Further, with reference to FIG. 4, a change in the potential of each node and a change in the state of the transistor when the input signal IN changes from the L level to the H level will be described.

The node 104 changes from H level to L level, the node 105 changes from L level to H level,
The N-channel MOS transistor 4 changes from OFF to ON, and the N-channel MOS transistor 3 changes from ON to OFF.

At this time, the node 101 is a P-channel type M
OS transistor 2 is turned on in response to the potential of node 100
From OFF to later than the transition of the N-channel MOS transistor 4, the voltage value gradually decreases with the transition of the N-channel MOS transistor 4 to ON,
The P-channel MOS transistor 1 changes from OFF to ON, the node 100 changes from L level to HH level, and the P-channel MOS transistor 2 changes from ON to OF.
The output signal OUT changes from L level to HH level.

At this time, the node 103 changes from the L level to the H level with a delay after the transition of the node 104 to change the potential at one end of the capacitor C2, and the other end is connected due to the coupling effect of the capacitor. By boosting the potential of the node 100, the transition of the P-channel MOS transistor 2 to OFF is assisted.

Further, the node 102 changes the potential at one end of the capacitance C1 by transitioning from the H level to the L level with a delay after the transition of the node 105, and the other end is connected due to the coupling effect of the capacitance. By lowering the potential of the node 101, the transition of the P-channel MOS transistor 1 to ON is assisted.

That is, when the potentials of the nodes 100 and 101 are in an unstable state due to resistance division of the P-channel MOS transistors 1 and 2 and the N-channel MOS transistors 3 and 4, one ends of the capacitors C1 and C2 are connected to the nodes. 1
The transition of the output signal OUT is accelerated by changing the direction of the output signal OUT in the same direction as that of the transition of 00 and 101 to assist the transition of the P-channel MOS transistors 1 and 2.

The capacitances C1 and C2 are formed of a capacitor capable of manufacturing a semiconductor such as a gate capacitance and a wiring capacitance of a transistor. For example, it is easily formed by using the channel capacitance between the WELL and the gate, the capacitance between the gate and the diffusion layer, the capacitance between the same-layer wirings, and the capacitance between the different-layer wirings.

Although the embodiment of the present invention has been described with reference to the drawings, the present invention is not limited to this embodiment, and various modifications can be made without departing from the spirit of the present invention. Implementation is possible. For example, the inverter INV
The present invention also includes a case where a plurality of stages 3 and the inverter INV4 are connected in cascade, and the delay amount is set according to the number of stages.

[0051]

As described above, according to the present invention, the node 1
VDD1 and VDD, where 00 and 101 tend to be unstable
In a level shifter that requires an operation with a large potential difference between the capacitors C1 and C2 and the inverters INV3 and INV4
Assists the transition so that the nodes 100 and 101 become stable, thereby speeding up the level shifter circuit.

Here, VDD1 is 2 V, VDD2 is 5 V
When designing the level shifter circuit, the dimensions of each MOS transistor are, for example, the inverter INV
1, INV2, INV11, and INV12 have L = 0.5 μm and W = 1
6 μm, L = 0.5 for N-channel type MOS transistor
um, W = 16 um, and the P-channel MOS transistors constituting the inverters INV3 and INV4 have L = 0.8
um, W = 5 um, L = 0.5 um, W = 5 um for N-channel type MOS transistors, L = 0.8 um, W = 5 for P-channel type MOS transistors 1, 2, 11, and 12
um, N-channel MOS transistors 3, 4, 13,
14 is L = 0.8 um, W = 10 um, capacity C1, C2
Is 0.02 pF. When the delay values of the conventional level shifter circuit and the level shifter circuit of the present invention are compared with each other, simulation results show that the conventional example is 5.3 NS, whereas the present invention has a delay value of 4.0 NS and about 25% of the delay value. Has the effect of speeding up.

[Brief description of the drawings]

FIG. 1 is a level shifter circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a level shifter circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a waveform diagram of each node in FIGS.

FIG. 4 is a waveform diagram of each node in FIGS.

FIG. 5 is a conventional level shifter circuit diagram.

FIG. 6 is a waveform chart of each node in FIG. 5;

FIG. 7 is a waveform chart of each node in FIG. 5;

[Explanation of symbols]

1, 2, 11, 12 P-channel MOS transistors 3, 4, 13, 14 N-channel MOS transistors 100 to 105, 151 to 154 Nodes INV1, INV2, INV3, INV4, INV1
1, INV12 Inverter C1, C2 Capacity IN Input terminal OUT Output terminal VDD1, VDD2 Power supply VSS Ground power supply

Claims (7)

(57) [Claims] 1. A level shifter circuit having an output section in which one end and a gate of two first conductivity type MOS transistors are cross-connected to each other, using a normal signal and an inverted signal generated from an input signal. A level shifter circuit comprising means for pulling up or pulling down the gates of two first conductivity type MOS transistors. 2. A first inverter, which is supplied with a voltage of a first power supply and shapes a waveform of an input signal, is connected to an input terminal.
A second inverter supplied with a power supply voltage and generating an inverted signal is connected to an output terminal of the first inverter;
The second power supply is connected to the sources of the first and second MOS transistors of the first conductivity type, the gate and the drain of the first and second MOS transistors of the first conductivity type are crossed, and each drain is connected to each drain. Connecting the drains of the first and second MOS transistors of the second conductivity type whose source is grounded, connecting the gate of the first MOS transistor of the second conductivity type to the output terminal of the first inverter; A second MOS transistor of a second conductivity type is connected to an output terminal of the second inverter;
Of the two contacts that connect the gates of the transistors and commonly connect the drains of the first and second MOS transistors of the first conductivity type and the drains of the first and second MOS transistors of the second conductivity type , A second of the second conductivity type
In the level shifter circuit having an output terminal connected to the drain connected to the drain of the MOS transistor, the voltage of the first power supply is supplied, the input is connected to the output terminal of the second inverter, and the output is connected via the first capacitor. A third MOS transistor connected to the gate of the first MOS transistor of the first conductivity type.
, A voltage of a first power supply, an input connected to the output terminal of the first inverter, and an output connected to the second MOS transistor of the first conductivity type through a second capacitor. And a fourth inverter connected to the gate. 3. A level shifter according to claim 2, wherein a delay amount is set by the dimensions of said third inverter, said fourth inverter, and said first and second capacitors. circuit. 4. The level shifter circuit according to claim 2, wherein the third inverter and the fourth inverter are cascade-connected in a plurality of stages, and a delay amount is set according to the number of stages. 5. A first inverter, supplied with a voltage of a first power supply and shaping the waveform of an input signal, is connected to an input terminal.
A second inverter supplied with a power supply voltage and generating an inverted signal is connected to an output terminal of the first inverter;
The second power supply is connected to the sources of the first and second MOS transistors of the first conductivity type, the gate and the drain of the first and second MOS transistors of the first conductivity type are crossed, and the respective drains are connected to the respective drains. Connecting the drains of the first and second MOS transistors of the second conductivity type whose source is grounded, connecting the gate of the first MOS transistor of the second conductivity type to the output terminal of the first inverter; A second MOS transistor of a second conductivity type is connected to an output terminal of the second inverter;
Of the two contacts that connect the gates of the transistors and commonly connect the drains of the first and second MOS transistors of the first conductivity type and the drains of the first and second MOS transistors of the second conductivity type , A second of the second conductivity type
In the level shifter circuit having an output terminal connected to the drain connected to the drain of the MOS transistor, the voltage of the first power supply is supplied, the input is connected to the output terminal of the second inverter, and the output is connected via the first capacitor. A third MOS transistor connected to the gate of the first MOS transistor of the first conductivity type.
And a first power supply voltage, an input of which is connected to an output terminal of the third inverter, and an output of which is connected to the second MOS transistor of the first conductivity type via a second capacitor. And a fourth inverter connected to the gate. 6. The level shifter circuit according to claim 5, wherein the delay amount is set by the dimensions of a third inverter, a fourth inverter, and the first capacitance and the second capacitance. 7. The level shifter circuit according to claim 5, wherein the third inverter and the fourth inverter are cascaded in a plurality of stages, and a delay amount is set according to the number of stages.