JP3008382B2 - PAL signal conversion circuit and PAL video signal generation method using the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PAL synchronous conversion circuit and a PAL using the same.
The present invention relates to a video signal generation method.

Conventional technology The NTSC standard adopted by Japan and other countries for the television standard system
(National Television System Committee) method, PAL (Phase Alt) adopted by European countries such as West Germany
eration line) method. These systems differ in the standard of the synchronization signal as follows.

Therefore, an encoder that generates R, G, B analog color signals or color video signals from image data always needs a synchronization signal. Therefore, conventionally, it was necessary to separately prepare an encoder for the NTSC system and an encoder for the PAL system.

The present invention relates to a PAL synchronous conversion circuit for generating a PAL color video signal by diverting an NTSC video color encoder and a PAL video signal generation using the same. It provides a method.

Means for Solving the Problems A synchronization conversion circuit for PAL according to the present invention includes a clock pulse generation circuit for generating a clock pulse for PAL, and a horizontal clock for generating a horizontal synchronization signal for PAL by dividing the clock pulse for PAL. Synchronization signal generation circuit, vertical synchronization signal generation circuit that divides PAL clock pulse to generate PAL vertical synchronization signal, frequency divider circuit that divides PAL clock pulse by a predetermined number, PAL
And a selector for selectively outputting a clock pulse for use and a divided clock pulse output from the divider circuit, and a period in which the selector selects the divided clock pulse is within a vertical retrace period. Means for controlling the selector, wherein the dividing ratio of the dividing circuit and the period for selecting the divided clock pulse in the selector are set so as to convert the NTSC vertical scanning period to the PAL vertical scanning period. Is what is being done.

A PAL video signal generation method using a PAL synchronization conversion circuit according to the present invention is configured to divide a given original clock signal to create a horizontal synchronization signal and a vertical synchronization signal, and to convert given image data into R signals. Video color encoder for NTSC, which converts analog color signals of G, B,
Image data reading means for reading out image data at a position on the screen represented by the horizontal synchronizing signal and the vertical synchronizing signal given from the video color encoder from a memory and giving the image data to the video color encoder;
And from the video color encoder above
An R, G, B encoder for converting R, G, B color signals into a PAL video signal is used. The output clock pulse of the selector in the PAL synchronous conversion circuit is used as an original clock pulse for the video color encoder. The PAL horizontal and vertical synchronizing signals output from the PAL synchronizing conversion circuit are supplied to the R, G, B encoders as synchronizing signals.

According to the PAL synchronization conversion circuit of the present invention, the PAL horizontal synchronization signal and the PAL synchronization signal can be obtained,
A clock pulse for TSC / PAL conversion is obtained. This NTSC /
The PAL conversion clock pulse includes a PAL clock pulse during a certain period of image data, and includes a clock pulse divided at a predetermined division ratio during part or all of the vertical blanking period.

According to the video signal generation method for PAL according to the present invention,
Since the clock pulse for NTSC / PAL conversion is given as the original clock pulse to the video color encoder having the synchronization generation circuit for NTSC, the video color encoder outputs a horizontal pulse having the same synchronization as that for PAL. ,
A vertical synchronization signal is obtained, and image data can be read using the horizontal and vertical synchronization signals. R, G, B for generating a PAL video signal from the image data thus read out
Since the encoder receives the PAL horizontal and vertical synchronizing signals output from the PAL synchronizing conversion circuit according to the present invention, a correct PAL video signal can be obtained from this encoder.

Embodiment FIG. 1 shows an embodiment of a PAL synchronization conversion circuit according to the present invention.

This PAL synchronous conversion circuit includes a counter 11, a decoder 12,
3, 14, a mixer 15, a rise detection circuit 16, a frequency divider 17, and a selector 18.

The frequency of the input clock pulse is about 2 in this embodiment.
This clock pulse is supplied to the counter 11 and counted. On the other hand, video color
The rising _edge of the PAL vertical synchronizing signal _{Vsync supplied} from the encoder 20 (FIG. 2) is detected by the rising edge detecting circuit 16, and the output of the rising edge detecting circuit 16 clears the counter 11 at the timing of detecting the rising edge. Each time the counter 11 is cleared, it starts counting input clock pulses from zero.

The count value of the counter 11 is provided to the decoders 12, 13 and 14. The decoder 12 generates the PAL horizontal synchronization signal _Hsync every time the count value of the counter 11 becomes a multiple of 1365. The decoder 13 generates the PAL vertical synchronization signal _Vsync every time the count value of the counter 11 becomes a multiple of 1365 × 312. These synchronization signals H _sync and V _sync are mixed by the mixer 15 and output as a PAL composite synchronization signal SYNC.

The input clock pulse is also applied to divider 17 and selector
18 input terminal. The frequency divider 17 divides the input clock pulse by a predetermined number n (divided by 8 in this embodiment) and outputs the divided clock pulse. The divided clock pulse (frequency 2.67 MHz) is supplied to the other input of the selector 18. Terminal.

Switching of the selector 18 is controlled by the output of the decoder 14. The decoder 14 controls the selector 18 based on the count value of the counter 11 so that the selector 18 selects the divided clock pulse during the vertical blanking period and selects the input clock pulse during the other periods.

As described above, the synchronizing circuit outputs the synchronizing signal SYNC including the PAL horizontal synchronizing signal _Hsync and the vertical synchronizing signal _Vsync , as well as the clock pulse CCK for generating the PAL synchronizing signal. Occurs. In addition, the clock pulse CCK includes a low-frequency clock pulse divided by n in a predetermined period. This clock pulse CCK is used for NTSC video color
When used as the original clock pulse for the encoder,
Since the clock frequency becomes slow while the selector 18 selects the clock pulse divided by n, the time of one field (vertical scanning period) becomes long. By appropriately setting the time zone in which the clock pulse divided by n is selected, 1 field time can be reduced to 1/50 second (= 20 ms) of the PAL system
It becomes possible.

Also, during the period in which the clock pulse divided by n is selected, the pulse width of the synchronizing signal output from the NTSC video color encoder becomes n times and cannot be used. Would. Therefore, the synchronization signal SYNC output from the synchronization conversion circuit is used in the RGB encoder described later. This synchronization signal SYNC is for PAL, and the horizontal scanning period is 64 μs.
Is set to

FIG. 2 shows the case where image data is converted using the synchronous conversion circuit described above.
A circuit for converting a video signal according to the PAL system and outputting the video signal is shown. FIG. 3 shows the operation of this circuit, in particular, how an NTSC-type synchronizing signal is converted to a PAL-type synchronizing signal.

The circuit shown in FIG. 2 includes a PAL synchronous conversion circuit 10, a memory 31 for storing image data, a video display controller (hereinafter referred to as VDC) 30, which reads image data from the memory 31, and a VDC 30 shown in FIG. CPU50, VDC30 to control
A video color encoder (hereinafter referred to as VCE) 20 for converting image data provided from the VCE into R, G, B analog color signals, and converting R, G, B signals provided from the VCE 20 into PAL video signals An RGB encoder (hereinafter referred to as RGBE) 40 is included. CPU50, VDC30 and VCE20 can be used as they are for TNSC video signals.

The symbols OSC, _Vsync , SYNC and CCK of the input / output signals of the synchronous conversion circuit 10 are the same as those shown in FIG. This circuit 10
In this embodiment, the input clock pulse is generated by a PLL (Phase Locked Loop) circuit including a voltage controlled oscillator (VCO) 3, a low-pass filter (LPF) 2, and a reference oscillator 1. Other components of the PLL circuit, that is, the phase comparator and the like are included in the synchronous conversion circuit 10. A clock pulse having the same frequency (about 21.3 MHz) as the input clock pulse is given to the CPU 50. The clock pulse CCK output from the synchronous conversion circuit 10 is given to the VCE 20 as its original clock pulse. The VCE20 uses this original clock pulse and divides it to obtain horizontal and horizontal signals.
Vertical sync signals H _sync and V _sync are created,
_sync is given to the synchronization conversion circuit 10. The output synchronization signal SYNC of the synchronization conversion circuit 10 is given to the RGBE 40.

For easy understanding, the operation of the VCE 20 when the synchronous conversion circuit 10 is not considered will be described. VCE20 is NT
This is a circuit for SC and its original clock pulse input terminal OS
It is assumed that an original clock pulse for NTSC is given to C. The original clock pulse for NTSC is
A VCE20 internal synchronization generator circuit can be used, and its frequency is, for example, 6 fsc (about 21.47 MHz).
This value is slightly higher than the frequency of the original clock pulse for PAL, which is about 21.3 MHz.

VCE20 gives the VDC30 create a vertical synchronization signal V _sync, a horizontal synchronization signal H _sync for NTSC by dividing the original clock pulse. In VDC, these synchronization signals V
_Since the position on the screen is determined by the _sync and the Hsync, the image data corresponding to the position is read from the memory 31.
Since the VCE 20 also generates a dot clock pulse for NTSC and supplies it to the VDC 30, the VDC 30 transfers the read image data to the VCE 20 in synchronization with the dot clock pulse. The VCE 20 converts the given image data into R, G, B signals and outputs them. Therefore, if a circuit for creating an NTSC video signal from the R, G, B signals output from the VCE20 is provided, the NTS
A C video signal will be obtained.

By supplying the clock pulse CCK from the synchronous conversion circuit 10 as an original clock pulse to the NTSC VCE 20, the VCE 20 operates as a video color encoder for PAL.

 Next, an operation according to the PAL method will be described.

The clock pulse CCK is given to the VCE 20 from the synchronous conversion circuit 10 as its original clock pulse. The clock pulse CCK is switched to 21.3 MHz or 2.67 MHz depending on the period.

The case where the clock pulse CCK is 21.3 MHz will be described. As described above, the VCE 20 creates a horizontal synchronization signal for NTSC by dividing the frequency of the original clock pulse for NTSC (strictly speaking, 21.47727 MHz). Original clock for PAL
When a pulse (strictly, 21.328125 MHz) is given, the VCE 20 creates and outputs a horizontal synchronization signal for PAL with the same frequency division ratio using the same frequency dividing circuit. Since the horizontal synchronization signal for NTSC and the horizontal synchronization signal for PAL have different periods as described above, the frequency of the original clock pulse may be determined according to the difference in the period.

Repeating it again, if the NTSC clock pulse of 21.47727 MHz is divided by 1365, a horizontal synchronization signal for NTSC with a period of 63.5 μs is obtained, and if the frequency of 21.328125 MHz for PAL is also divided by 1365, the PAL for 64 μs is A horizontal synchronization signal is obtained.

Next, the clock pulse CCK is about 2.67 MHz (about 21.3 MHz
Will be described. The frequency-divided clock pulse is used to generate a vertical synchronization signal for PAL. The synchronization of the vertical synchronization signal for PAL is 1/50 second, which is longer than the period of the vertical synchronization signal for NTSC 1/60 second. Therefore, instead of the 21.3 MHz clock pulse,
By applying a 2.67 MHz clock pulse divided by 8 to the VCE20 as an original clock pulse for a certain period,
The period of the vertical synchronization signal generated from the VCE 20 can be reduced to 1/50 second for PAL.

The period for selecting the divided clock pulse is preferably within the vertical blanking period. As a result, it is possible to eliminate adverse effects on the R, G, and B image data due to the delay of the clock pulse. That is, since the clock pulse is delayed, the horizontal synchronizing signal and the dot clock signal are also delayed, so that the R, G, and B data are also skipped. Since there is no image data (black level data) during the vertical blanking period, there is no adverse effect on the image data.

As described above, by supplying the clock pulse CCK generated from the synchronization conversion circuit 10 to the VCE 20, the VCE 20 outputs a horizontal synchronization signal (excluding the vertical retrace period) _Hsync and vertical since synchronization signal V _sync and a dot clock pulse is applied to the output VDC30, image data at the position specified by these synchronization signals are read out by VDC30, it would be given to VCE20.

The uppermost waveform in FIG. 3 shows a synchronization signal for NTSC output from VCE20. The second waveform shows a PAL synchronization signal output from the VCE 20. The third row shows the switching of the clock signal by the selector 18.
Both the first-stage and second-stage synchronization signals correspond to one frame 26.
Two lines (for simplicity, in the case of in-interlace).

Thus, a correct PAL video signal cannot be obtained with 262 lines per frame. Therefore, as described above, since the synchronization signal SYNC conforming to the PAL system is correctly output from the synchronization conversion circuit 10, this is supplied to the RGB encoder 40 and used for creating a PAL video signal. Since the synchronization signal SYNC and the synchronization signal output from the VCE 20 are created by using the same clock pulse of the synchronization conversion circuit 10, their timings match each other. The synchronization signal shown at the bottom of FIG. 3 is the synchronization signal SYNC for PAL. Here, one frame has 312 lines. Black level data is provided during the additional horizontal scanning period in the retrace period.

According to the synchronization conversion circuit for PAL according to the present invention, the horizontal synchronization signal and the vertical synchronization signal for PAL can be obtained,
A clock pulse for TSC / PAL is obtained. This NTSC / PAL
The conversion clock pulse is used during the period when there is image data.
A clock pulse for PAL is included, and a part or all of the vertical blanking period includes a clock pulse divided at a predetermined dividing ratio.

According to the video signal generation method for PAL according to the present invention,
Since the clock pulse for NTSC / PAL conversion is given as the original clock pulse to the video color encoder having the synchronization generation circuit for NTSC, the video color encoder outputs a horizontal pulse having the same synchronization as that for PAL. ,
A vertical synchronization signal is obtained, and image data can be read using the horizontal and vertical synchronization signals. R, G, B for creating a PAL video signal from the image data thus read out
Since the encoder receives the PAL horizontal and vertical synchronizing signals output from the PAL synchronizing conversion circuit according to the present invention, a correct PAL video signal can be obtained from this encoder.

Therefore, according to the present invention, it becomes possible to use an NTSC video color encoder having an NTSC synchronization generation circuit for PAL.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a PAL synchronization conversion circuit according to the present invention. FIG. 2 is a block diagram showing a circuit for generating a PAL video signal by controlling the NTSC video color encoder by using the above-mentioned PAL synchronization conversion circuit, and FIG. 3 is a waveform diagram showing the operation thereof. It is. 3 ... voltage controlled oscillator, 10 ... synchronous conversion circuit for PAL, 11 ... counter, 12, 13, 14 ... decoder, 16 ... rising edge detection circuit, 17 ... frequency divider, 18 ... selector, 20 ... Video color encoder, 30 ... Video display controller, 40 ... R, G, B encoder.

Claims (2)

(57) [Claims] A clock pulse generating circuit for generating a clock pulse for PAL; a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal for PAL by dividing the frequency of the PAL clock pulse; A vertical synchronizing signal generation circuit for generating a PAL vertical synchronizing signal by dividing the frequency, a frequency dividing circuit for dividing the PAL clock pulse by a predetermined number, a PAL clock pulse and a frequency dividing clock output from the frequency dividing circuit. Selector for selectively outputting pulses and
And means for controlling the selector so that a period during which the selector selects a divided clock pulse is within a vertical retrace period. The dividing ratio of the dividing circuit and the divided clock pulse in the selector are provided. A synchronous conversion circuit for PAL, wherein a period to be selected is set so as to convert an NTSC vertical scanning period into a PAL vertical scanning period. 2. An NTSC for dividing an applied original clock signal to generate a horizontal synchronizing signal and a vertical synchronizing signal and converting applied image data into R, G, B analog color signals. A video color encoder; image data reading means for reading image data at a position on a screen represented by a horizontal synchronization signal and a vertical synchronization signal given from the video color encoder from a memory and giving the image data to the video color encoder;
And R, G, B given from the above video color encoder
An R, G, B encoder for converting a color signal into a video signal for PAL is used, wherein the output clock pulse of the selector in the synchronous conversion circuit for PAL according to claim 1 is used as an original clock pulse. A PAL synchronous conversion circuit, wherein the PAL horizontal and vertical synchronization signals output from the PAL synchronization conversion circuit are supplied to the R, G, B encoders as synchronization signals. Video signal generation method.