JP3094346B2 - Image memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device.

[0002]

2. Description of the Related Art Conventionally, access of an image memory device is basically performed in pixel units. Further, as a method for realizing a multiport, that is, a plurality of inputs and outputs, a configuration in which an image memory is accessed via an input / output bus has been proposed. In this configuration, access is basically performed in pixel units. .

[0003]

As described above, even if a multi-port connection is used, the transfer speed of the input / output bus is limited, so that a single input / output (I / O) circuit can be used while accessing. However, it is difficult to interrupt the access of other input / output circuits, and especially in the case of a large-capacity image memory device, it often waits for a long time.

In the case of an image memory, it is conceivable to simplify data management in units of frames (or fields) of an image. Data management becomes difficult, and complicated address management is required.

An object of the present invention is to provide an image memory device in which an input / output bus is used effectively and address management is simplified.

[0006]

An image memory device according to the present invention is based on a memory and a data amount of input image data.
Determine the number of packets and the amount of data in each packet
Determining means, and the input image data by the determining means
Packetizing means for dividing the packet into packets in units of the determined data amount and outputting the image data in packet units; and writing the image data of each packet in the memory based on the data amount of the input image data. the packet and the address generating means for generating a start address to start each packet, the image data outputted from the packetizing means based on previously <br/> head address that will be generated by the address generating means to said memory Intermittent in units
And writing means for writing the data into the memory.
The image memory device according to the present invention also includes a memory and an input image.
Based on the amount of image data, the number of packets and each packet
Determining means for determining the data amount of the input image data;
Data in units of the data amount determined by the determination means.
The image data on a packet-by-packet basis.
Packetizing means for outputting the input image data;
Based on the data amount of each packet,
Specify the start address to start writing image data in each packet.
Address generating means for generating each address;
Based on the start address generated by the generating means.
The image data output from the
Writing means for writing intermittently in packet units;
The packet output from the packetizing means is
After the packet has been recorded in the
Control to enable interrupts for other processing while data is output
Means.

[0007]

The head address of each packet is generated by the generation means.
Can be obtained without the need for complicated address management.
Image data can be quickly written to and read from memory.
Wear.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 1A is a block diagram of the entire configuration, and FIG. 1B is an example of an internal circuit of an A / D conversion circuit as an input port.

In FIG. 1A, reference numeral 10 denotes a memory for storing image data, which has a memory capacity capable of storing a plurality of frames. Reference numeral 11 denotes a memory control circuit that controls the memory 10. Reference numeral 12 denotes an image data bus for accessing the memory 10 via the memory control circuit 11;
4 and 16 digitize an analog video signal.
The / D conversion circuits 18 and 20 are D / A conversion circuits for converting the image data read from the memory 10 onto the image data bus 12 into analog data and outputting the analog data.

In this embodiment, the A / D conversion circuit 14 is for camera input, the A / D conversion circuit 16 is for line input,
/ A conversion circuit 18 for VTR output, D / A conversion circuit 20
Are used for monitor output, and are input to and output from the image data bus 12 in packet units.

As shown in FIG. 1B, the A / D conversion circuit 14 includes an A / D converter 22 and an A / D converter 22.
It comprises M FIFO (first in first out) memories 24 for packetizing bit outputs. A / D conversion circuit 16
Has a similar configuration. The D / A conversion circuits 18 and 20
In contrast to the / D conversion circuits 14 and 16, the image data bus 1
M FIFO memories to which packets from 2 are input;
And a D / A converter for converting the output of the FIFO memory into an analog signal.

Reference numeral 26 denotes A / D conversion circuits 14, 16 and D via the image data bus 12 and the memory control circuit 11.
The bus control circuit controls input / output between the / A conversion circuits 18 and 20 and the memory 10. Reference numeral 28 denotes an address conversion circuit which outputs the start address of the memory 10, the required number of packets, and the number of data of one packet in response to the designation of the frame number and the number of frames from the bus control circuit 26, and stores an initial value. It consists of a ROM and a RAM for updating during operation.

Reference numeral 30 denotes a CPU for controlling the whole; 32, a monitor for displaying an operation state; 34, a monitor control circuit for controlling the monitor 32; 36, a CPU bus for interconnecting the CPU 30, the monitor control circuit 34, and the bus control circuit 26; It is.

First, the operation of the present embodiment will be described with reference to an example in which a camera input is stored in the memory 10. FIG. 2 shows a flowchart of the operation. The CPU 30 outputs the recording start of the camera input and the recording amount (frame number and number of frames) to the bus control circuit 26 (S1). The bus control circuit 26 refers to the address conversion circuit 28 and
From the frame number and the number of frames from the PU 30, the start address of the memory 10, the required packet number n and the data number q of one packet are obtained. Then, the obtained number q of data of one packet is transferred to the A / D conversion circuit 14 via the image data bus 12, and the start address 10 is stored in the memory control circuit 11
Transfer to

In the A / D conversion circuit 14, the number q of data of one packet is set in the control section of the FIFO memory 24 (S3), and the A / D converter 22 outputs the analog input signal of the camera.
The video signal is digitized and stored in the FIFO memory 24. When one packet of q data is stored in the FIFO memory 24, the transfer request is sent to the image data bus 12
Output to the top.

On the other hand, the bus control circuit 26 clears the variable x for managing the number of packets (S5), transfers the start address of each packet to be transferred to the memory control circuit 11 (S7), and executes A / D conversion. It waits for a transfer request from the conversion circuit 14 (S8). The image data bus 12 is released for the A / D conversion circuit 14 in response to the transfer request from the A / D conversion circuit 14, and the memory control circuit 11 transfers the data from the A / D conversion circuit 14 to the memory 10. Write in.

The memory 10 is a D-RAM (dynamic
(Random access memory), the data on the image data bus 12 is stored in the memory 1 at a high speed in the high-speed page mode or the write mode corresponding thereto.
Write to 0. After writing one packet of data,
An end message is sent to the bus control circuit 26 (S9). The bus control circuit 26 increments the variable x according to the end message (S10).

Until the necessary number n of packets are transferred, that is, until n = x (S6), S7 to S9 are repeated,
When n = x, an end message is sent to the CPU 30, and the CPU 30 ends the camera input storage control.

FIG. 3 shows the data structure of one packet.
q is the number of data of one packet specified by the bus control circuit 26 and can be changed freely. P is the width (byte) of the image data bus. The number m of data in one packet is m = q × p.

FIG. 4 shows a timing chart of the above operation for writing the camera input into the memory 10. In the figure, A
Indicates a period during which one packet of data is stored in the A / D conversion circuit 14, and B indicates a period during which one packet of data is written into the memory 10. In the period A except the period B in the period A, the image data bus 12 is not used, and the other A / D conversion circuit 16 or D
/ A conversion circuits 18 and 20.

FIG. 5 shows the VTR output (D / A) during the period C.
Conversion circuit 18), line input (A / D conversion circuit 16),
4 shows a timing chart when the monitor output (D / A conversion circuit 20) is sequentially interrupted. Thus, the four tasks of writing the camera input to the memory 10, outputting the contents of the memory 10 to the VTR, writing the line input to the memory 10, and outputting the contents of the memory 10 to the monitor can be performed in a short time. Become.

[0023]

As can be easily understood from the above description, according to the present invention, since the head address of each packet can be obtained, the image data can be quickly stored in the memory without complicated address management. Can be written to and read from. Write image data to memory intermittently in packet units
Write each packet to memory
After that, other processing is performed until the next packet is written.
Enables memory access, improving system processing efficiency
can do. Also, the amount of input image data
By determining the packet size accordingly,
Enables memory access and increases memory space
It can be used effectively.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of the embodiment.

FIG. 3 is a configuration diagram of a packet according to the present embodiment.

FIG. 4 shows the timing of the present embodiment with respect to the camera input.
It is a chart.

FIG. 5 is a timing chart of a camera input, a VTR output, a line input, and a monitor output according to the present embodiment.

[Explanation of symbols]

10: Memory 11: Memory control circuit 12: Image data bus 14, 16: A / D conversion circuit 18, 20:
D / A conversion circuit 22: A / D converter 24: FIFO
(First in first out) memory 26: bus control circuit 28:
Address conversion circuit 30: CPU 32: Monitor 34: Monitor control circuit
36: CPU bus

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Ichiro Kuwana 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-2-31935 (JP, A) JP-A-5 -130549 (JP, A) JP-A-2-191048 (JP, A) JP-A-62-198925 (JP, A) JP-B-60-53327 (JP, B2) (58) Fields investigated (Int. . ^7, DB name) G06T 1/60 G06F 13/16 510 G09G 5/00 550 G09G 5/39 H04N 5/907

Claims (5)

(57) [Claims] 1. A memory,The number of packets and each
Determining means for determining the data amount of the packet; The input image data is stored in a data determined by the determination means.
Data amount into packets, and The packet unit
Packetizing means for outputting the image data atBased on the data amount of the input image data, In the memory
Where writing of image data for each packet is started
Address generating means for generating a head address for each packet
Generated by the address generating means.ToTo the first address
Image data output from the packetizing means based on the
Into the memoryIntermittently in packet unitsBook to write
Image memory device comprising:
Place. 2. The image memory device according to claim 1, wherein said address generation means further generates a frame head address at which writing of image data of said frame in said memory is started based on a frame number of said input image data. . 3. The image memory device according to claim 2, wherein said packetizing means generates a plurality of said packets from one frame of said image data. 4. The memory according to claim 1 , wherein said address generating means is provided in said memory.
When reading the image data, the
Read the image data of each packet from the memory.
Start address for starting sending is generated for each packet
The image memory device according to claim 1. 5. A memory, The number of packets and each
Determining means for determining the data amount of the packet; The input image data is stored in a data determined by the determination means.
Data into packet units.
Packetizing means for outputting the image data at Based on the data amount of the input image data,
Where writing of image data for each packet is started
Address generating means for generating a head address for each packet
When, The start address generated by the address generation means
Image data output from the packetizing means based on the
Is written intermittently in the memory in the packet unit.
Means of writing, The packet output from the packetizing means is
After the packet has been recorded in the
Control to enable interrupts for other processing while data is output
And an image memory device.