JP3090115B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a plan view and a side view schematically showing a semiconductor chip of a conventional general semiconductor device. In FIG. 4, since the present invention aims to improve the method of arranging pins in the semiconductor chip 1, the outline of the semiconductor integrated circuit element 5 mounted on the semiconductor chip 1 is indicated by a dashed line. The display is simplified, and the display of the entity is omitted. The same applies to the plan views and side views / side sectional views in the following drawings. In FIG. 5, pads 2 are arranged along the periphery of the semiconductor chip 1, and the pads 2 have ball terminals 3 functioning as external terminals.
Is installed. In the surface plan view of FIG. 4, the pad 2 is indicated by a square, and the ball terminal 3 is indicated by a circle. At the time of mounting such a semiconductor device, the size of the ball terminal 3 needs to be defined within the size of the pad 2, which lowers the assembly yield at the time of manufacturing and also reduces the semiconductor device. Also on the substrate 6 side, it is required to form pads with a fine pitch, and thus there is a problem that the manufacturing cost increases.

On the other hand, in recent years, the number of pins provided on a semiconductor chip of a resin-encapsulated semiconductor device has been rapidly increasing with the increase in integration and functionality of the semiconductor device. In addition, the area occupied by the pins arranged on the semiconductor chip also increases, which causes a problem that goes against downsizing of the semiconductor device itself. As a countermeasure, various BGAs (ball grid arrays) in which bumps and the like are provided on both surfaces of a semiconductor substrate in accordance with each purpose.
A semiconductor device of the type or a method of manufacturing the same has been proposed. If it collapses, in JP-A-59-8361,
To prevent the container of the semiconductor device from increasing in size with an increase in the number of pins, and to reduce the wiring resistance and the wiring capacitance from the chip to the external lead, external electrodes are provided on both upper and lower surfaces of the container of the semiconductor device. There is disclosed a method of increasing the number of pins without increasing the size of a semiconductor device by providing bumps for the semiconductor device. Further, in this semiconductor device, by doing so, the wiring resistance and the wiring capacitance of the semiconductor integrated circuit element on the chip can be suppressed. FIG. 5 is a cross-sectional view of a semiconductor chip in the semiconductor device. The internal lead pattern 10 connected to the semiconductor integrated circuit element 5 by a wire corresponds to the semiconductor integrated circuit element 5.
There is connected to the upper surface bumps 8 _a and the lower surface bumps 8 _b. The ceramics (not shown) for sealing the semiconductor chip, these top bump 8 _a and the lower surface bumps 8 _b, and the through hole for pulling the upper and lower surfaces respectively provided, this is this prior art It is a feature of. The assembling method includes a first layer on which a semiconductor chip is mounted and a second layer on which internal leads are arranged.
A method of sintering the third layer for joining the layer and the metal cover plate has been adopted.

[0004] As another conventional example, Japanese Patent Application Laid-Open No. HEI 9-19953 has been proposed.
In the semiconductor device disclosed in Japanese Patent Publication No. 3 (2003), the purpose is to improve the design margin, which is limited by the number of wirings between elements on a semiconductor substrate, and to reduce the chip size and the occupied area during mounting. Therefore, as a structural form for connecting predetermined elements on the semiconductor substrate, using an electrically conductive bump and an insulating film formed to have a horizontal electrical wiring, A structure is employed in which bumps corresponding to electrode pads for element connection of a semiconductor substrate are connected by an adhesive, pressure bonding, or the like. The insulating film is referred to as a bump film in the present proposal, but as a structure of the bump film, a hole is formed in a resin film having an electrical insulating property, the hole is filled with nickel, and A conductive adhesive is applied to the lower surface, and bumps are formed on the upper and lower surfaces of the film in the form of attaching gold to the upper surface.
A wire made of nickel or copper for connecting desired electrode pads is provided. Also, Japanese Patent Application Laid-Open No. 8-153
Japanese Patent Application Laid-Open No. 819 discloses a BGA (Ball Grid Array) which is designed to improve the reliability of the semiconductor device due to the proximity between the pads of the BGA (Ball Grid Array) due to the increase in the number of pads accompanying the increase in the density of the BGA. A method of manufacturing a semiconductor package of the type is shown. The BGA type semiconductor device that is the object of the manufacturing method in this conventional example is a semiconductor device that has been developed to reduce the size of the semiconductor chip in response to recent high-density mounting of the semiconductor chip. The structure is such that a semiconductor chip is mounted on one surface of a semiconductor circuit board and sealed with resin, and a plurality of pins connected to the semiconductor chip are arranged on the other surface. The connection between the semiconductor chip and the plurality of pins is made via through holes provided in the circuit board. As described above, a method of connecting both sides of the circuit board via the through holes provided in the circuit board has been generally performed.

[0005]

In the conventional semiconductor device described above, in the case of the semiconductor device described at the beginning, the size of the ball mounted on the pad of the semiconductor device is the size of the pad. If the size is within the range, mounting is possible, but if the size does not fit within the size of the pad, mounting is not possible.
There is a drawback that the yield of assembling the semiconductor chip is reduced, and it is indispensable to form pads with finer pitches on the substrate side, and the manufacturing cost including the semiconductor device itself and the substrate increases.

Further, in the case of the semiconductor integrated circuit device disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Sho 59-8361, both the production and sintering of the three ceramic layers require a great deal of time and effort, and There is a drawback that it is not easy to form a two-layer ceramic having a wiring pattern. In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 9-199333, it is generally not easy to make a hole in a semiconductor substrate, and a metal is formed in the hole. There is a disadvantage that a large number of man-hours are required when filling the object. Further, Japanese Patent Application Laid-Open No.
BGA produced by the manufacturing method disclosed in JP-A-19
As a conventional method of connecting both sides of a circuit board, a through-hole provided in the circuit board is used as in the case of the semiconductor device disclosed in the above-mentioned publication. Has been done through. In this method, a step of making a hole in the circuit board is required in common, and there is a disadvantage that the required man-hour and manufacturing cost are increased.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device, wherein pads arranged on a peripheral portion of a semiconductor chip are divided into a first group of pads and a second group of pads, and the first group is divided into pads. A first group of input / output terminals electrically connected to each of the included pads; a wiring member electrically connected to each of the pads included in the second group; The semiconductor device is characterized in that it extends to the back surface of the semiconductor chip via the side surface of the chip, and forms a second group of input / output terminals on the back surface that are electrically bonded to each terminal of the wiring member. . The first group of pads and the second group of pads arranged in the peripheral portion of the semiconductor chip are arranged in an arbitrary number of pads between the first group and the second group. The first group of pads and the second group of pads arranged at the periphery of the semiconductor chip may be arranged in a state of being alternately replaced by each other. First
The first group and the second group may be arranged such that they are alternately replaced by one pad at a time.

Further, both the first group of input / output terminals and the second group of input / output terminals may be formed by ball terminals, and the wiring member is formed of the second group of pads and the second group of input / output terminals. May be formed by TAB connecting the input / output terminals of the above. The TAB may be formed by a wiring portion made of a copper material and a resin portion made of polyimide or the like. The first group of input / output terminals may be formed as signal input / output terminals, and the second group of input / output terminals may be formed as power / ground input / output terminals.

In a second aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor chip by forming a semiconductor circuit element, a pad, and a cover on an upper surface of a semiconductor substrate; and forming a bump on the pad. Step 1, TAB (A) functioning as a wiring part and TA functioning as an insulating part
A second step of aligning the TAB formed by B (B) and the semiconductor chip with the pad on the upper surface of the semiconductor chip, and pressing the TAB (A) against the semiconductor chip using bumps 3rd to fix
And TAB (A) and TAB (B)
Is folded along the side surface of the semiconductor chip to the back surface, and the folded TAB (A) and the back surface of the semiconductor chip are joined and fixed by an adhesive, and the TAB (B) is
A fourth step of fixing as an insulator between (A) and a wiring portion on the back surface of the semiconductor chip, and temporarily fixing a ball terminal to the pad on the upper surface of the semiconductor chip by bonding the ball terminal to the pad; A fifth step of temporarily fixing the ball terminals to the TAB (A) on the back surface of the semiconductor chip, and exposing the pole terminals to the front surface on both surfaces of the semiconductor chip and enclosing the entire semiconductor chip with the molding resin 9 And at least a sixth step as an assembly process procedure.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a front plan view (see FIG. 1 (a)), a side view (see FIG. 1 (b)), and a rear plan view (FIG. 1 (c)) showing the appearance of a semiconductor chip according to one embodiment of the present invention. )). As shown in FIG. 1A, pads 2 are arranged on the surface of a semiconductor chip 1 along the periphery thereof, and ball pads 3 and T terminals are alternately provided on these pads.
AB4 is electrically bonded. In FIG. 1A, the square is the pad 2, and the ball terminal 3 is superimposed on the pad 2 and circularly displayed. The black square display superimposed on the pad 2 is a display indicating the TAB 4 adhered to the pad 2. Since the semiconductor integrated circuit element 5 mounted on the semiconductor chip 1 does not directly participate in the description of the present invention, the outline of the semiconductor integrated circuit element 5 is simply indicated by a dashed line. Fastening.

On the surface of the semiconductor chip 1 shown in FIG.
Every other ball terminal 3 is electrically bonded, and for every pad 2 to which this ball terminal 3 is not mounted, every other TAB 4 is electrically bonded. The TAB 4 serves as a lead wire from the pad 2 bonded on the front surface of the semiconductor chip 1 to the back surface, and as shown in the schematic side view of FIG.
The terminal is formed in a U-shape along the side surface of the semiconductor chip 1, and the terminal is formed in the semiconductor chip 1 shown in FIG.
Is set in the peripheral portion on the back surface of. And this TAB
The ball terminals 3 functioning as connection terminals for external leads are electrically connected to the respective terminals 4. That is, in the present embodiment, TAB mounting technology is effectively used, and as shown in FIGS. 1A and 1C, both sides of the semiconductor chip 1 are
By arranging the ball terminals 3 connected to the corresponding pads 2, the ball terminals 3 shown in FIG. 1A function as external connection terminals on the surface of the semiconductor chip 1. On the back surface of the semiconductor chip 1, the ball terminals 3 shown in FIG. 1C can function as terminals for connection to the outside. Then, the semiconductor chip 1 configured as shown in FIG. 1 is finally subjected to mold sealing for the purpose of protection.

As described above, every other ball terminal 3 and TAB 4 are bonded to the peripheral pads on the surface of the semiconductor chip 1, and ball terminals are provided on both sides of the semiconductor chip 1 via the TAB 4. Can be placed,
In addition, the distance between the ball terminals arranged on both sides of the chip is doubled. As a result, the number of pins arranged in the peripheral portion of the semiconductor chip 1 can be increased to about twice the number, and the area occupied by the semiconductor chip can be increased in response to high-density mounting of the semiconductor device. The number of pins can be increased.

In FIG. 1, every other pad 2 on the surface of the semiconductor chip 1 has a T
Although the lead wire is drawn out from the back surface by AB4, the lead wire drawn out from the back surface by TAB4 is limited to only the signal terminal or only the power supply terminal and the ground terminal. Accordingly, the arrangement surface of the ball terminals 3 can be sorted for each use of the pad 2. In this case,
When only the power supply terminal and the ground terminal are drawn out to the back surface, the signal terminals are arranged on the front surface of the semiconductor chip 1 and the wiring length from the pad 2 to the terminal can be shortened. It is effective when you need. Further, if a dielectric is used as the insulating material of the TAB 4, a capacitance is formed between the power supply voltage supplied from the back surface and the ground potential, and the effect of suppressing generation of power supply noise can be expected. Secondary effects can also be obtained. Further, when the signal terminals are drawn out on the back surface, the wiring lengths for the power supply terminal and the ground terminal are shortened, so that the wiring inductance is reduced, and particularly when an input / output signal having a large amplitude is handled, There is an advantage that the power supply capability is stabilized.

FIG. 2 and FIG. 3 are schematic side views showing the main points of the procedure of the assembling process when manufacturing the semiconductor device of the present invention. In the following, referring to FIGS. 2 and 3,
The procedure for assembling the semiconductor device will be described. In FIG. 2, first, a semiconductor circuit element 5, pads 2 and a cover 8 are formed on the upper surface of a semiconductor substrate 6, and a semiconductor chip 1 is formed. The bumps 8 are formed by using (FIG. 2)
(See (a)). Then, TAB (wiring portion) created by copper 4 and _a, TAB created by polyimide
(Resin part) 4 _b is formed, the TAB (wiring portion) 4 _a
The TAB (resin portion) _4b and the semiconductor chip 1 are aligned with the pad 2 (see FIG. 2B). Then, the TAB (wiring portion) 4 _a is pressed and fixed to the semiconductor chip 1 using the bump 8 (see FIG. 2C). Next, the TAB (wiring portion) 4 _a and the TAB (resin portion) 4 are folded into the back surface along the side surface of the semiconductor chip 1, and the folded TAB (wiring portion) 4 _a and the back surface of the semiconductor chip 1 Are bonded and fixed by an adhesive, and TAB
The (resin portion) _4b is fixed as an insulator between the TAB (wiring portion) _4a and the wiring portion on the back surface of the semiconductor chip 1 (see FIGS. 2D and 3A). Then, the upper surface of the semiconductor chip 1 is temporarily fixed ball pin 3 is bonded to the pad 2, the rear surface of the semiconductor chip 1, the TAB (wiring portion) ball pin 3 is being temporarily fixed adhered to 4 _a (See FIGS. 3B and 3C). Then, as a final step, the entire semiconductor chip 1 is sealed with the molding resin 9 in a state where the ball terminals 3 are exposed on the surface (see FIG. 3D).

[0016]

As described above, according to the present invention, every other ball terminal and TAB are adhered to the pad at the peripheral portion of the semiconductor chip, and the ball is attached to both sides of the semiconductor chip via the TAB. By arranging the terminals, the distance between the ball terminals on both sides of the semiconductor chip is increased, thereby making it possible to increase the number of pins arranged in the peripheral portion without increasing the area occupied by the semiconductor chip. There is an effect that it is possible to cope with high-density mounting.

When ball terminals set on both surfaces of the semiconductor chip are divided into signal terminals and power supply terminals / ground terminals via the TAB, and only the power supply terminals / ground terminals are drawn out to the back surface, the signal terminals are used. Are arranged on the surface of the semiconductor chip, the wiring length from the pad to the external terminal can be shortened, and it is possible to adapt particularly to an operation function requiring high-speed input / output.

Further, by using a dielectric as an insulating material of the TAB, a capacitance is formed between the power supply voltage and the ground potential on the back surface of the semiconductor chip, and an effect of suppressing the generation of power supply noise is expected. There is a side effect of being able to do it.

Further, in the manufacturing method, the connection between the pad on the upper surface of the semiconductor chip and the ball terminal on the lower surface is performed by TAB without passing through a through hole.
The assembling process can be easily performed, and the required man-hour and manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a front plan view, a side view, and a back plan view of an embodiment of the present invention.

FIG. 2 is a schematic side view (1) showing an assembling procedure according to one embodiment of the present invention.

FIG. 3 is a schematic side view (2) showing an assembling procedure according to one embodiment of the present invention.

FIG. 4 is a plan view and a side view of a conventional example.

FIG. 5 is a side sectional view showing another conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor chip 2 pad 3 ball terminal 4 TAB 4 _a TAB (wiring portion) 4 _b TAB (resin portion) 5 semiconductor integrated circuit element 6 semiconductor substrate 7 cover 8 bump 8 _a upper surface bump 8 _b lower surface bump 9 mold 10 internal lead pattern

Claims (8)

(57) [Claims] A first group of pads arranged in a peripheral portion of the semiconductor chip and a second group of pads; a first group of pads electrically connected to each of the pads included in the first group; A group of input / output terminals is provided, and a wiring member electrically connected to each pad included in the second group is provided, and the wiring member is extended to the rear surface of the semiconductor chip via a side surface of the semiconductor chip. And set it on the back,
A semiconductor device, wherein a second group of input / output terminals is formed to be electrically bonded to each terminal of the wiring member. 2. The semiconductor device according to claim 1, wherein the first group of pads and the second group of pads arranged in a peripheral portion of the semiconductor chip have an arbitrary positional relationship between the first group and the second group. 2. The semiconductor device according to claim 1, wherein the pads are alternately arranged. 3. A positional relationship between the first group of pads and the second group of pads arranged in a peripheral portion of the semiconductor chip is one pad between the first group and the second group. 2. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged alternately. 4. The semiconductor device according to claim 1, wherein said first group of input / output terminals and said second group of input / output terminals are both formed by ball terminals. 5. The wiring member according to claim 1, wherein the wiring member is formed by TAB that connects the second group of pads and the second group of input / output terminals. Semiconductor device. 6. The semiconductor device according to claim 5, wherein said TAB is formed by a wiring portion made of a copper material and a resin portion made of polyimide or the like. 7. The input / output terminal of the first group is formed as an input / output terminal for signal input / output, and the input / output terminal of the second group is formed as an input / output terminal for power / ground. 7. The semiconductor device according to claim 1, claim 2, claim 3, claim 3, claim 4, claim 5, or claim 6. 8. A semiconductor circuit element on an upper surface of a semiconductor substrate.
A first step of forming a pad and a cover to form a semiconductor chip and forming a bump on the pad; and forming a TAB (A) functioning as a wiring portion and a TAB (B) functioning as an insulating portion. A second step of aligning the TAB to be performed and the semiconductor chip with the pad on the upper surface of the semiconductor chip; and a third step of pressing and fixing the TAB (A) to the semiconductor chip by using a bump. And TAB (A) and TAB (B) are folded on the back surface along the side surface of the semiconductor chip, and the folded TAB
(A) and the back surface of the semiconductor chip are bonded and fixed with an adhesive, and the TAB (B) is fixed as an insulator between the TAB (A) and the wiring portion on the back surface of the semiconductor chip. And a fifth step of temporarily bonding the ball terminal to the pad on the upper surface of the semiconductor chip by bonding the ball terminal to the pad and bonding the ball terminal to the TAB (A) on the rear surface of the semiconductor chip. A sixth step of exposing the ball terminals on both surfaces of the semiconductor chip and enclosing the entire semiconductor chip with a mold resin 9 as at least an assembly process procedure. Method.