JP3089149B2 - Branch metric operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch metric operation circuit of a trellis decoding circuit for decoding an information symbol subjected to trellis coding modulation.

[0002]

2. Description of the Related Art In recent years, in the field of broadcasting, a trellis coded modulation method is used as a coding method for obtaining a coding gain in a limited frequency band. For the encoding method and its effect, see, for example, G. Ungerboeck, "Trellis-
Coded Modulation with Redundant Signal Sets Part
I: Introduction "and" Trellis-Coded Modulatio "
nwith Redundant Signal Sets Part II: State of the A
rt ", IEEE Communications Magazine, 1987-Vol.25.N
stated in o.2.

[0003] A brief overview is given below. FIG. 9 shows a general form of the trellis encoder. Referring to FIG. 9, information symbol (k + m) bits are uncoded bits (k bits),
Encoded bits (n bits) obtained by expanding m bits by the convolutional encoder 101 are used as modulation symbol (k + n) bits, which are modulated and transmitted. The trellis coded modulation method is characterized by the way of arranging the modulation symbols.

FIG. 10 shows an example in which k = 2, m = 1, and n = 2, and the modulation method is 16QAM. In the example shown in FIG. 10, the upper 2 bits correspond to non-coded bits, and the lower 2 bits correspond to coded bits. Obviously from the configuration of the trellis encoder shown in FIG. 9, the coded bits, which are the lower two bits, have a larger inter-code distance. So the top 2bi
For t, the inter-code distance is determined by the modulation symbol arrangement.

In FIG. 10, for example, a symbol of 〇 is a symbol whose lower 2 bits are “00”. Δ is a symbol of “11”, □ is a symbol of “01”, and ◎ is a symbol of “10”. The basic principle of the trellis coded modulation scheme is that, by arranging the symbols in this way, for symbols that differ only in the upper 2 bits, the distance on the modulation symbol arrangement is maximized to obtain the total inter-code distance.

By the way, the receiving side decodes this by the Viterbi algorithm. The state transition diagram which is the basis of decoding includes parallel state transitions as shown in FIG. That is, in the case of this example, among the state transitions from the time (j-1) to the time j, focusing on the transition from the state {0,0} to the state {0,0}, the output of the possible encoder is There are four ways. This means that the number of cases where uncoded 2 bits can be taken is four, which corresponds to the symbol 〇 in FIG. Also, the four branches corresponding to the symbol of △ in the case where the coded bit is “11” are obtained at time j
In the state {0, 0}. Therefore, the path selection in this node selects the path closest to the received symbol sequence from the eight paths.

[0007] Also, when soft-deciding a received symbol, it is assumed that a position e of the received symbol is detected by soft-decision at a position as shown in FIG.
In this case, first, a branch metric is obtained to obtain a path metric. At this time, it is clear that the distance to the symbol of $ 8 is the shortest among the distances to the four symbols of $.

In the text, ８8 means that 8 is entered in ○ (for example, see FIG. 8), and similarly, △ F is △
Means the one in which F is entered. In other words, by writing a character immediately after a graphic, it means that the character is written in the graphic.

As described above, when a path is selected using a branch metric, as shown in FIG.
Since the path (Rj-1) left in 1) is common to the four paths passing through the path of the symbol 〇, the path (Rj
The path metric for -1) is also common. Therefore,
The difference in path metric for these four paths is equal to the difference in branch metric for each of the 〇 symbols. Therefore, the calculation of the path metric for selecting a path can be represented by the calculation for a path passing through $ 8. Therefore, this $ 8 will be referred to as a representative symbol.

Referring to FIG. 12, for symbol △, ΔF is closest to the received symbol, and △ F is the representative symbol. Therefore, it is sufficient to consider only the path passing through ΔF among the dotted paths in FIG. 13, and the path metric of the path passing through # 8 and the path metric of the path passing through ΔF are compared, and the likelihood is calculated. Is selected, that is, the path with the smaller path metric is selected. As described above, in trellis decoding, it is not necessary to calculate the branch metric for all the symbols, but only for the representative symbol determined by the position of the received symbol.

In this way, the coded bit at time j is decoded by the Viterbi algorithm,
If it is “1”, among the representative symbol set # 8, ΔF, ２2, and □ 5 at the time j, the possible modulation symbol is □ 5 in which the lower 2 bits are “01”.
The uncoded bit is "01", which is the upper two bits. That is, non-coded bits can be decoded using the coded bits that have been Viterbi decoded. In summary, the basic configuration of trellis decoding is roughly divided into an uncoded bit decoding unit 105 and a Viterbi decoding unit 103 as shown in FIG. It should be noted that the non-coded bits are decoded using Viterbi-decoded coded bits.

As described above, it is necessary to calculate a branch metric in Viterbi decoding. FIG. 15 shows a configuration example of a conventional branch metric unit (hereinafter, sometimes abbreviated as BMU) for calculating a branch metric. In trellis decoding, the square of the Euclidean distance between a received symbol and a representative symbol of each subset is used. This Euclidean distance 2
If the power is used directly as a branch metric, for example, each branch metric (〇, △, ，, □) is represented by 8 bits.

[0013]

On the other hand, in many cases, bits are truncated in order to reduce the scale of the path metric operation circuit that follows. That is, in the conventional configuration, for example, when the branch metric unit is configured by a ROM, the soft-decided received symbol is represented by 10 bits,
If the bit censoring is the upper 4 bits, 2 ¹⁰ × 4 × 4 =
Requires 8192 bit ROM. RO of this scale
It is disadvantageous in terms of cost to incorporate M as a trellis decoding LSI and integrate it into one chip.

The present invention has been made in view of the above problems, and has as its object to provide a branch metric calculation circuit capable of reducing the number of bits of a branch metric and reducing the circuit scale.

[0015]

According to a first aspect of the present invention, an information symbol consisting of a plurality of bits is convolutionally coded on a transmitting side with a predetermined number of bits. A group of symbols set in a predetermined bit arrangement with encoded bits and the remaining bits as unencoded bits, wherein the arrangement of the unencoded bits in each subset symbol of the subset is a gray code, Trellis-coded modulation of adjacent symbols among the representative symbols, in which the coded bits are arranged so that only one bit is different, is demodulated on the receiving side, and based on the received symbols obtained by soft decision, Viterbi A branch metric operation circuit of a trellis decoding circuit for decoding non-encoded bits using encoded bits that have been Viterbi-decoded by a decoding unit. Amplitude limiting means for limiting the amplitude of the received symbol obtained by the soft decision, and calculating the square of the Euclidean distance for the data subjected to the amplitude limitation by the amplitude limiting means to calculate the square in the Viterbi decoding. The gist of the invention is to have a Euclidean distance calculating means for setting a branch metric.

Specifically, on the transmitting side, an information symbol composed of a plurality of bits is convolutionally encoded with m bits, which are a part of the information symbol, so that the information symbol is enlarged to n (> m) bits, and the remaining k Bits are transmitted as non-coded bits and (k + m) bits are trellis coded and modulated in combination with the coded bits. On the receiving side, demodulated by a demodulator and a soft-decision received symbol is used as an input and a Viterbi decoding circuit is input. A trellis decoding circuit configured to decode the k-bit non-coded bits using n-bit coded bits decoded according to the following formula: a branch metric for calculating a branch metric for a representative symbol of each subset used for the Viterbi decoding In the arithmetic circuit, the data obtained by subjecting the soft-decided received symbol to the amplitude limiting Is obtained by a configuration in which a branch metric by calculating the square of the Euclidean distance by the Euclidean distance calculation means.

Further, the second invention of the present application has non-linear processing means for performing non-linear processing for limiting the output value of the Euclidean distance calculating means to the predetermined value when the output value exceeds the predetermined value. Is the gist.

Further, the third invention of the present application is characterized in that there is provided a bit truncating means for truncating a bit with respect to the output of the Euclidean distance calculating means.

Further, the fourth invention of the present application is characterized in that there is provided a bit truncation means for truncating the bit of the output of the non-linear processing means according to the second aspect.

Further, the fifth invention of the present application has nonlinear processing means for performing non-linear processing for limiting the output value to the predetermined value when the output value of the bit truncation means according to claim 3 exceeds a predetermined value. Make a summary.

[0021]

With the above configuration, the branch metric operation circuit according to the first invention of the present application demodulates the signal subjected to trellis-coded modulation on the transmission side on the reception side and converts the symbol into a received symbol obtained by soft decision. On the other hand, in order to easily calculate the Euclidean distance, the amplitude is limited by the amplitude limiting means. Further, the square of the Euclidean distance for the data subjected to the amplitude limitation is calculated by the Euclidean distance calculating means, and is used as a branch metric in Viterbi decoding.

The branch metric operation circuit according to the second aspect of the present invention is configured such that when the output value of the Euclidean distance operation means according to the first aspect exceeds a predetermined value, the nonlinear processing means performs non-linear processing to such an extent that decoding deterioration does not occur. By limiting the value to the predetermined value, the number of bits required to represent each branch metric can be reduced.

In a branch metric operation circuit according to a third aspect of the present invention, the output of the Euclidean distance operation means is subjected to bit termination by the bit termination means.

According to a fourth aspect of the present invention, there is provided a branch metric operation circuit for performing bit truncation on the output of the non-linear processing means.

The branch metric calculation circuit according to a fifth aspect of the present invention performs nonlinear processing to such an extent that decoding degradation does not occur when the output value of the bit truncation means according to claim 3 exceeds a predetermined value, and converts the output value to the predetermined value. , The number of bits required to represent each branch metric can be reduced.

[0026]

An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a branch metric operation circuit according to the present invention. As shown in FIG. 1, in the branch metric operation circuit of this embodiment, a limiter unit 11, a Euclidean distance operation unit 13, a non-linear processing unit 15, and a bit truncation unit 17 are connected in series.

First, an example of limiting the amplitude of a received symbol will be described with reference to FIG. Even if the branch metric is obtained after the amplitude limitation as shown in FIG. 2 is performed, there is no deterioration in the correction ability. This is because the order of the Euclidean distance for each representative symbol does not change even if the amplitude is limited. For example, the received symbol a shown in FIG.
Is □ 9, and 〇C, ◎
The distance is smaller in the order of 6, △ 3. Then, even in the symbol b after the amplitude limitation, no change occurs in this order.

By applying the amplitude limitation in this manner, the Euclidean distance calculation can be performed by calculating the square of the Euclidean distance only in an area surrounded by a set of four representative symbols as shown in FIG. FIG. 3 shows an example of what value the square of the Euclidean distance for the lower left representative symbol takes in accordance with the position of the received symbol in the 9-value soft decision. For example, if the received symbol is c
, The square of the Euclidean distance from the representative symbol at the lower left starting point is 5 ² +5 ² = 50.
Further, the Euclidean distance from the representative symbol at the position of d is 7 ² +0 ² = 49, and similarly, the position of e is 8 ² +8 ² = 128.

Next, a second embodiment will be described with reference to FIG. Referring to FIG. 3, the possible value of the square of the Euclidean distance is 0 to 0, as is apparent from the above.
128, which requires 8 bits. By the way, in FIG. 3, the MSB bit becomes 1 only when there is a received symbol at the position (c), and only for this case, the MSB (Most Significant).
It is uneconomical to use one bit of an ant bit).
Therefore, the value of 128 at this time is converted to the nonlinear processing means 103.
To 127. Thereby, the whole can be represented by 7 bits.

FIG. 4 shows a computer simulation experiment as a typical example of the error rate characteristics (in the figure, TCM stands for Trellis Coded Modulation). In FIG. 4, the graph [g] shows that the amplitude limit is
BER (Bit Error Ra) when non-linear processing is not performed
te) Characteristics. Graph [f] shows the BER characteristics when the amplitude limitation and the non-linear processing are performed. The number of bits BS of each branch metric is 7. Graph [g]
It can be seen from the comparison between the graphs of the graphs [f] and [f] that there is almost no difference in BER characteristics. For reference, the BER characteristic when the QPSK modulation of the graph [a] is used and the graph [b]
BER characteristics (when coding is not performed) of 16QAM.

Next, a third embodiment will be described with reference to FIGS. After the amplitude limitation is performed, the bit is truncated by the bit truncation unit, and the path metric calculation in the subsequent stage can be made more efficient. According to the graph [e] of the simulation experiment result in FIG. 4, even if the upper 3 bits are cut off, decoding deterioration hardly occurs. FIG. 5 shows the respective branch metrics corresponding to FIG. 3 in that case in decimal notation. If bit truncation is performed without performing the non-linear processing, in order to prevent decoding deterioration,
It is easy to imagine that 4 bits are required as shown in FIG.

Next, a fourth embodiment will be described with reference to FIGS. As is clear from the above, the order of the non-linear processing means 103 and the bit truncation means 104 in FIG. 1 is interchangeable. For example, by forcing the upper right “8” of the branch metrics of FIG. 6 to “7”,
It matches the branch metric of FIG. 5 and can be represented by 3 bits.

Next, a fifth embodiment according to the present invention will be described with reference to FIGS. FIG. 7 shows an example of a better signal arrangement when the number of uncoded bits is 2 bits or more.
t).

In this method, first, a symbol group set in a predetermined bit arrangement, that is, an arrangement of uncoded 2 bits (upper 2 bits) in each subset symbol of a subset is mapped by a Gray code. Specifically, for example, when attention is paid to the symbol ○ (the lower 2 bits are “00”), the adjacent symbols ０0 and ４4 differ only by 1 bit.

Next, among the representative symbols of each subset,
The adjacent lower bits are arranged so that only the lower 2 bits of the coded bits differ by 1 bit. In particular,
For example, adjacent □ 5 and ＣC, □ 5 and △ 3 are different from each other only in the lower 2 bits by 1 bit.

In this way, the magnitude relationship between the Euclidean distance and the Hamming distance for uncoded bits matches. Further, since the magnitude relationship between the Euclidean distance and the Hamming distance of the coded bits that are the targets of Viterbi decoding match, the BER characteristic is 0.1 to 0.3 dB in C / N conversion as compared with the example shown in FIG. The degree is improved.

FIG. 8 shows BER characteristics when the above-described amplitude constraining, non-linear processing, and bit truncation (Bs = 3) are performed and not performed using the signal arrangement shown in FIG. [I], graph [j]). In addition,
In this example, the number of expression bits (quantization bit number) of the received symbol is 12 bits (FIG. 4 is 10 bits). Also in this case, the effects of the three processes, namely, the amplitude limitation, the nonlinear process, and the bit truncation can be ignored.
It turns out to be effective.

The graph [h] is an asymptotic lower bound (theoretical value) of the BER characteristic of the 16 TCM of the present embodiment, calculated based on the above literature.

As described above, according to the above embodiments,
First, in order to make it easy to calculate the Euclidean distance, a limiter (reception symbol amplitude limitation) is applied. This is 16QA
This is useful for a rectangular or cross type modulation scheme such as M or 32QAM. In addition, the number of bits of each branch metric can be reduced by performing non-linear processing (limiter) on the output of the Euclidean distance calculating means to such an extent that decoding deterioration does not occur, thereby reducing the load of the path metric calculation in the subsequent stage. Can be. Further, the scale of the branch metric operation circuit itself can be reduced.

[0040]

As described above, the present invention has the effects of reducing the number of bits of the branch metric and reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a branch metric unit according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a range of amplitude limitation of a received symbol.

FIG. 3 is a diagram illustrating an example of calculating a branch metric;

FIG. 4 is a diagram showing BER simulation experimental values.

FIG. 5 is a diagram illustrating a case where nonlinear processing is performed.

FIG. 6 is a diagram showing a case without nonlinear processing.

FIG. 7 is a diagram illustrating an example of a better signal arrangement.

FIG. 8 is a diagram showing a BER characteristic by a computer simulation experiment.

FIG. 9 is a diagram illustrating an example of trellis-coded modulation symbol arrangement.

FIG. 10 is a block diagram illustrating a configuration of a trellis encoder.

FIG. 11 is a diagram showing an example of a parallel state transition.

FIG. 12 is a diagram illustrating received symbols and branch metrics.

FIG. 13 is a diagram showing representative symbols and state transitions.

FIG. 14 is a block diagram illustrating a basic configuration of trellis decoding.

FIG. 15 is a block diagram illustrating a configuration example of a conventional branch metric unit.

[Explanation of symbols]

 11 Limiter section 13 Euclidean distance calculation means 15 Non-linear processing means 17 Bit truncation means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00 H03M 13/25 H04L 27/22 H04L 27/38

Claims (5)

(57) [Claims] An information symbol composed of a plurality of bits on a transmission side is convolutionally encoded with a predetermined number of bits as a coded bit, and the remaining bits are encoded as uncoded bits. A symbol group set by the bit arrangement of, the gray code the arrangement of the uncoded bits in each subset symbol of the subset,
For adjacent symbols among the representative symbols of the subset, the receiving side demodulates trellis-coded modulation in which the coded bits are arranged such that only one bit is different,
A branch metric calculation circuit of a trellis decoding circuit for decoding non-coded bits using coded bits Viterbi-decoded by a Viterbi decoding unit based on the received symbols obtained by the soft decision. Amplitude limiting means for limiting the amplitude of the obtained received symbol; and a Euclidean distance as a branch metric in the Viterbi decoding by calculating the square of the Euclidean distance for the data on which the amplitude is limited by the amplitude limiting means. A branch metric calculation circuit comprising: calculation means. 2. The branch metric according to claim 1, further comprising nonlinear processing means for performing nonlinear processing for limiting the output value to the predetermined value when the output value of the Euclidean distance calculation means exceeds a predetermined value. Arithmetic circuit. 3. The branch metric calculation circuit according to claim 1, further comprising bit cutoff means for cutting off the bit of the output of said Euclidean distance calculation means. 4. The branch metric operation circuit according to claim 2, further comprising bit truncation means for truncating a bit of an output of said non-linear processing means. 5. The branch metric operation according to claim 3, further comprising nonlinear processing means for performing nonlinear processing for limiting the output value to the predetermined value when the output value of the bit truncation means exceeds a predetermined value. circuit.