JP3085831B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3085831B2 JP3085831B2 JP05231531A JP23153193A JP3085831B2 JP 3085831 B2 JP3085831 B2 JP 3085831B2 JP 05231531 A JP05231531 A JP 05231531A JP 23153193 A JP23153193 A JP 23153193A JP 3085831 B2 JP3085831 B2 JP 3085831B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- oxide film
- storage electrode
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000000034 method Methods 0.000 title description 10
- 238000004519 manufacturing process Methods 0.000 title description 4
- 238000003860 storage Methods 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の中でも
特にＤＲＡＭ（Ｄｙｎａｍｉｃ Ｒａｎｄｏｍ Ａｃｃ
ｅｓｓ Ｍｅｍｏｒｙ）のメモリセルなどにおけるキャ
パシタ部のストレージ電極の形状とその製造方法に関す
るものである。BACKGROUND OF THE INVENTION The present invention relates to a DRAM (Dynamic Random Acc.) Among semiconductor devices.
The present invention relates to a shape of a storage electrode of a capacitor part in a memory cell of an ess memory, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】図３に従来のスタックト（積層）型メモ
リセルの製造工程を断面図で示し、以下に説明する。2. Description of the Related Art FIG. 3 is a sectional view showing a manufacturing process of a conventional stacked memory cell, which will be described below.
【０００３】まず、図３（ａ）に示すように、シリコン
半導体基板（以下単に基板と称す）１上に、公知のＬＯ
ＣＯＳ法（選択酸化法）によりフィールド酸化膜２を形
成して素子分離を行なう。次に素子形成領域にトランジ
スタのゲートのゲート絶縁膜となる薄い酸化膜３ａを通
常の酸化法で形成し、その上にゲート電極となるポリシ
リコン３を形成し（一般にこのゲート電極３にはさらに
不純物を導入して導電性を高める）、所定の形状にホト
リソ（ホトリソグラフィ）・エッチング技術でパターニ
ングする。次いで、そのゲート電極３をマスクにして、
基板１の所定部分に不純物をイオン注入（以下インプラ
と称す）して、トランジスタのソース・ドレイン４を形
成する。ここまでは、本発明には直接関係しない工程で
ある。First, as shown in FIG. 3A, a known LO is placed on a silicon semiconductor substrate (hereinafter simply referred to as a substrate) 1.
A field oxide film 2 is formed by a COS method (selective oxidation method) to perform element isolation. Next, a thin oxide film 3a serving as a gate insulating film of a transistor gate is formed in the element formation region by a normal oxidation method, and polysilicon 3 serving as a gate electrode is formed thereon (generally, the gate electrode 3 is further provided with a polysilicon). Introducing impurities to increase conductivity) and patterning into a predetermined shape by photolithography (photolithography) etching technology. Next, using the gate electrode 3 as a mask,
Impurities are ion-implanted into predetermined portions of the substrate 1 (hereinafter referred to as implants) to form the source / drain 4 of the transistor. The steps so far are not directly related to the present invention.
【０００４】次ぎに、図３（ｂ）に示すように、前記で
形成された構造の上全面にシリコン酸化膜（以下、単に
酸化膜と称す）５をＣＶＤ法（化学的気相成長法）など
で堆積させ、所定部分にホトリソ・エッチング技術でコ
ンタクトホール（セルコンタクトと称す）５ａを形成す
る。次いで、そのセルコンタクト５ａの側壁、底面を含
めて表面に導電性膜であるポリシリコン６をＣＶＤ法で
形成し、不純物をインプラして導電性を持たせる。次い
で、そのストレージ電極６の上にキャパシタ絶縁膜とな
るシリコン窒化膜（以下、単に窒化膜と称す）７をＬＰ
（低圧）ＣＶＤ法で形成し、その窒化膜７の上部を酸化
した（図示せず）後、セルプレート電極となるポリシリ
コン８をＣＶＤ法で形成し、不純物をインプラして導電
性を持たせる。そして、キャパシタ部としての所定形状
にホトリソ・エッチング技術でパターニングする。[0004] Next, as shown in FIG. 3 (b), a silicon oxide film (hereinafter simply referred to as an oxide film) 5 is formed on the entire surface of the structure formed above by a CVD method (chemical vapor deposition). Then, a contact hole (referred to as a cell contact) 5a is formed in a predetermined portion by a photolithographic etching technique. Then, polysilicon 6 as a conductive film is formed on the surface including the side wall and the bottom surface of the cell contact 5a by the CVD method, and impurities are implanted to have conductivity. Next, a silicon nitride film (hereinafter, simply referred to as a nitride film) 7 serving as a capacitor insulating film is formed on the storage electrode 6 by LP.
After forming by a (low pressure) CVD method and oxidizing the upper part of the nitride film 7 (not shown), polysilicon 8 serving as a cell plate electrode is formed by a CVD method, and impurities are implanted to have conductivity. . Then, patterning is performed by a photolithography etching technique into a predetermined shape as a capacitor portion.
【０００５】次いで、図３（ｃ）に示すように、前記構
造の上に層間絶縁膜９（一般に酸化膜をＣＶＤ法などで
形成）、配線（一般にアルミニウムあるいはその合金を
スパッタ法などで形成）１０を形成してメモリセル部の
構造を得る。Then, as shown in FIG. 3C, an interlayer insulating film 9 (generally, an oxide film is formed by a CVD method) and a wiring (generally, aluminum or an alloy thereof is formed by a sputtering method) on the structure. 10 is formed to obtain the structure of the memory cell portion.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、前述し
た従来の方法では、半導体装置の高集積化、縮小化に伴
いストレージ電極も当然縮小化する場合、十分なセル容
量（キャパシタ容量、Ｃｓ）が得られず、ホールドタイ
ム不良やソフトエラーが生じ、デバイス特性の劣化、歩
留まりの低下をきたす。However, in the above-mentioned conventional method, when the storage electrodes are naturally reduced in size as the semiconductor device becomes more highly integrated and smaller, sufficient cell capacitance (capacitor capacitance, Cs) is obtained. However, a hold time defect and a soft error occur, resulting in deterioration of device characteristics and a decrease in yield.
【０００７】本発明は、前記セル容量が十分確保できな
いという問題点を除去するため、ストレージ電極の形状
として孔を設けるようにして、その孔の内壁にもキャパ
シタ絶縁膜を形成するようにし、キャパシタとしての実
効面積を増すことにより、十分なセル容量を得られるよ
うにすることを目的とするものである。According to the present invention, in order to eliminate the problem that the cell capacity cannot be secured sufficiently, a hole is provided as the shape of the storage electrode, and a capacitor insulating film is formed on the inner wall of the hole. It is an object of the present invention to obtain a sufficient cell capacity by increasing the effective area as described above.
【０００８】[0008]
【課題を解決するための手段】この発明は、前述した目
的を達成するため、ストレージ電極の形状として複数の
孔を設け（実施例では、ストレージ電極を断面としてＴ
字型にし、そのひさし部分に孔が形成された形状として
いる）、その孔の内壁にもキャパシタ絶縁膜を形成する
ようにしたものである。According to the present invention, in order to achieve the above-mentioned object, a plurality of holes are provided as the shape of the storage electrode (in the embodiment, the storage electrode has a cross section of T
And a hole is formed in the eaves), and a capacitor insulating film is also formed on the inner wall of the hole.
【０００９】[0009]
【作用】本発明は、前述したように、ストレージ電極に
孔を設けるようにしたので、ストレージ電極ひいてはキ
ャパシタとしての面積が大きくなり、十分なセル容量が
確保できる。従って、装置が縮小されても良好なデバイ
ス特性の半導体装置を実現できる。According to the present invention, as described above, since holes are provided in the storage electrode, the area of the storage electrode and thus the capacitor is increased, and a sufficient cell capacity can be secured. Therefore, a semiconductor device having good device characteristics can be realized even if the device is reduced in size.
【００１０】[0010]
【実施例】図１ないし図２に本発明の実施例の製造工程
を主要部分の断面図で示し、以下に説明する。なお、従
来例の図３と同じ部分には同じ符号を付してある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 show a manufacturing process of an embodiment of the present invention in a sectional view of a main part, which will be described below. The same parts as in FIG. 3 of the conventional example are denoted by the same reference numerals.
【００１１】図１（ａ）に示す、基板１上にフィールド
酸化膜２、ゲート酸化膜３ａ、ゲート電極３、ソース・
ドレイン４を形成するところまでは、従来例の図３
（ａ）と全く同じであり、また本発明には直接関係する
ところではないので、説明は割愛する。As shown in FIG. 1A, a field oxide film 2, a gate oxide film 3a, a gate electrode 3, a source
Up to the point where the drain 4 is formed, FIG.
Since this is exactly the same as (a) and is not directly related to the present invention, the description is omitted.
【００１２】この後、本実施例では図１（ａ）に示すよ
うに、前記構造の上に絶縁膜であるシリコン酸化膜（以
下、単に酸化膜と称す）５を３００〜５００ｎｍ、その
上にシリコン窒化膜（以下、単に窒化膜と称す）１１を
１０〜２０ｎｍ、さらにその上に酸化膜１２を４００〜
６００ｎｍ程度の厚さＣＶＤ法により順次形成する。つ
まり積層させる。Thereafter, in this embodiment, as shown in FIG. 1A, a silicon oxide film (hereinafter simply referred to as an oxide film) 5 serving as an insulating film is formed on the above-mentioned structure in a thickness of 300 to 500 nm, and further thereon. A silicon nitride film (hereinafter simply referred to as a nitride film) 11 is 10 to 20 nm, and an oxide film 12 is further
The layers are sequentially formed by a CVD method with a thickness of about 600 nm. That is, they are stacked.
【００１３】次いで、その上にＬＰＣＶＤ法により、シ
ラン（ＳｉＨ4 ）ガスを用いてアモルファス状態からポ
リシリコンに変わる遷移温度（例えば５７０℃）でシリ
コン膜を３０〜５０ｎｍ厚さ形成すると、図１（ａ）に
示すように島状に孤立した粒径３０〜５０ｎｍの半球状
のシリコン膜１３が多数形成される。Next, a silicon film is formed thereon by LPCVD using a silane (SiH 4 ) gas at a transition temperature (for example, 570 ° C.) at which the amorphous state is changed to polysilicon at a thickness of 30 to 50 nm. As shown in a), a large number of hemispherical silicon films 13 having a particle size of 30 to 50 nm isolated in an island shape are formed.
【００１４】次いで、図１（ｂ）に示すように、島状の
前記シリコン膜１３をマスクにしてＲＩＥ（反応性イオ
ンエッチング）法により、前記酸化膜１２をエッチング
して溝（トレンチ）１２ａを形成する。このときのエッ
チングは、前記酸化膜１２の下部が１００〜３００ｎｍ
の厚さ残るように行なう。つまり前記溝１２ａは酸化膜
１２の途中まで形成するのである。なお、この溝１２ａ
によりできた凸部を１２ｂとする。Next, as shown in FIG. 1B, the oxide film 12 is etched by RIE (Reactive Ion Etching) using the island-shaped silicon film 13 as a mask to form a trench (trench) 12a. Form. At this time, the lower portion of the oxide film 12 is formed to have a thickness of 100 to 300 nm.
Is performed so that the thickness remains. That is, the groove 12a is formed halfway through the oxide film 12. The groove 12a
The projection formed by the above is 12b.
【００１５】次いで、前記島状のシリコン膜１３をフッ
酸（ＨＦ）と硝酸（ＨＮＯ3 ）との混合液などで除去し
た後、図１（ｃ）に示すように、ホトリソ・エッチング
技術でセルコンタクト５ａを従来同様形成する。続い
て、全面に（勿論セルコンタクト５ａも埋まるように）
導電性膜であるポリシリコン膜６をＬＰＣＶＤ法により
４００〜６００ｎｍの厚さ堆積させる。そして、ＰＯＣ
ｌ3 を拡散源として不純物としてリンを注入して導電性
を高める。Next, after removing the island-shaped silicon film 13 with a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO 3 ), as shown in FIG. The contact 5a is formed as in the conventional case. Subsequently, the entire surface (of course, so that the cell contact 5a is also buried).
A polysilicon film 6, which is a conductive film, is deposited to a thickness of 400 to 600 nm by LPCVD. And POC
Phosphorus is implanted as an impurity using l 3 as a diffusion source to increase conductivity.
【００１６】次いで、図２（ｄ）に示すように、ＲＩＥ
法により前記ポリシリコン膜６を前記溝１２ａの深さよ
り薄くなるように全面エッチバックする。そして、ホト
リソ・エッチング技術により、ストレージ電極となる所
定形状にパターニングする。つまり、前記セルコンタク
ト５ａに埋まっているポリシリコン膜６と、その部分を
中心として前記溝１２ａの一部を含むポリシリコン膜６
のパターン（いわばストレージ電極として断面が次の図
２（ｅ）で明確なようにＴ字型）にする。Next, as shown in FIG.
The entire surface of the polysilicon film 6 is etched back so as to be thinner than the depth of the trench 12a. Then, it is patterned into a predetermined shape to be a storage electrode by a photolithographic etching technique. That is, the polysilicon film 6 buried in the cell contact 5a and the polysilicon film 6 including a part of the trench 12a around the portion.
(A so-called storage electrode having a T-shaped cross section as clearly shown in FIG. 2E).
【００１７】次いで、図２（ｅ）に示すように、フッ酸
溶液などによる等方性エッチングにより、前記酸化膜１
２を前記窒化膜１１をストッパーとして全部除去する
と、前記溝１２ａを形成した際の酸化膜１２の凸部１２
ｂがあった部分がポリシリコン膜６において空洞（孔）
６ａになる。つまり、断面がＴ字型に形成されたストレ
ージ電極（ポリシリコン）６のひさし部分に多数の孔６
ａができた形状となる。この孔６ａによりストレージ電
極６の表面積が増加することになる。Next, as shown in FIG. 2E, the oxide film 1 is subjected to isotropic etching using a hydrofluoric acid solution or the like.
2 is completely removed using the nitride film 11 as a stopper, the protrusions 12 of the oxide film 12 at the time of forming the grooves 12a are removed.
The portion where b was present is a cavity (hole) in the polysilicon film 6.
6a. That is, a large number of holes 6 are formed in the eaves of the storage electrode (polysilicon) 6 having a T-shaped cross section.
a is formed. Due to the holes 6a, the surface area of the storage electrode 6 increases.
【００１８】この後、図２（ｆ）に示すように、前記ス
トレージ電極の表面、無論前記孔６ａ内の側壁の面も含
めて、キャパシタ絶縁膜となる窒化膜７をＬＰＣＶＤ法
により５〜１０ｎｍの厚さ形成し、その表面を酸化し
（図示せず）、その上にセルプレートとなるポリシリコ
ン膜８を２００〜３００ｎｍの厚さ形成し（これも勿
論、前記孔６ａ内を含む）ＰＯＣｌ3 を拡散源としてリ
ンを注入して導電性を持たせ、ホトリソ・エッチング技
術でセルプレート電極８としての所定形状にパターニン
グする。この後は、従来同様、絶縁膜９、配線１０を形
成して、図２（ｆ）に示すようなメモリセル部の構造を
得る。Thereafter, as shown in FIG. 2F, a nitride film 7 serving as a capacitor insulating film including the surface of the storage electrode and, of course, the side wall surface in the hole 6a is formed to a thickness of 5 to 10 nm by LPCVD. Then, the surface thereof is oxidized (not shown), and a polysilicon film 8 serving as a cell plate is formed thereon to a thickness of 200 to 300 nm (this also includes the inside of the hole 6a, of course). Phosphorus is implanted using 3 as a diffusion source to make it conductive, and patterned into a predetermined shape as the cell plate electrode 8 by photolithographic etching technology. Thereafter, as in the conventional case, the insulating film 9 and the wiring 10 are formed to obtain the structure of the memory cell portion as shown in FIG.
【００１９】[0019]
【発明の効果】以上説明したように、本発明によれば、
ストレージ電極の構造として複数の孔を設けた形状とし
たので、キャパシタ部としての表面積を狭い範囲におい
ても増加させることができ、装置の高集積化、縮小にも
かかわらず十分なセル容量を確保でき、良好なデバイス
特性の半導体装置を得られる。As described above, according to the present invention,
Since the storage electrode has a shape with a plurality of holes, the surface area of the capacitor can be increased even in a narrow range, and sufficient cell capacity can be secured despite high integration and reduction of the device. A semiconductor device having good device characteristics can be obtained.
【図１】本発明の実施例の工程説明図（その１）FIG. 1 is a process explanatory view of an embodiment of the present invention (part 1).
【図２】本発明の実施例の工程説明図（その２）FIG. 2 is a process explanatory view of an embodiment of the present invention (part 2).
【図３】従来例の工程説明図FIG. 3 is a process explanatory view of a conventional example.
１ 基板 ５、１２ シリコン酸化膜 ６ ポリシリコン ６ａ 孔 １１ シリコン窒化膜 １３ シリコン膜 １２ａ 溝 Reference Signs List 1 substrate 5, 12 silicon oxide film 6 polysilicon 6a hole 11 silicon nitride film 13 silicon film 12a groove
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04
Claims (1)
第１の耐酸化性絶縁膜、第２の絶縁膜を順に積層する工
程、 （ｂ）前記第２の絶縁膜に複数の溝を形成し、該溝を埋
め込むように全面に導電性膜を形成する工程、 （ｃ）前記導電性膜を、キャパシタ部のストレージ電極
となる部分のみ残るように選択的に除去する工程、 （ｄ）前記第２の絶縁膜を、前記第１の耐酸化性絶縁膜
をストッパーとして除去し、前記導電性膜に複数の孔を
形成する工程、 以上の工程を順に施すことを特徴とする半導体装置の製
造方法。(A) a first insulating film on a semiconductor substrate;
A step of sequentially laminating a first oxidation-resistant insulating film and a second insulating film; (b) forming a plurality of grooves in the second insulating film and forming a conductive film on the entire surface so as to fill the grooves; (C) selectively removing the conductive film so that only a portion serving as a storage electrode of a capacitor portion remains; and (d) removing the second insulating film from the first oxidation-resistant insulating film. Removing the film as a stopper and forming a plurality of holes in the conductive film; and performing the above steps in order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05231531A JP3085831B2 (en) | 1993-09-17 | 1993-09-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05231531A JP3085831B2 (en) | 1993-09-17 | 1993-09-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0786433A JPH0786433A (en) | 1995-03-31 |
| JP3085831B2 true JP3085831B2 (en) | 2000-09-11 |
Family
ID=16924954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05231531A Expired - Fee Related JP3085831B2 (en) | 1993-09-17 | 1993-09-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3085831B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2321776A (en) * | 1996-08-16 | 1998-08-05 | United Microelectronics Corp | Method of fabricating a stacked capacitor |
| US5759890A (en) * | 1996-08-16 | 1998-06-02 | United Microelectronics Corporation | Method for fabricating a tree-type capacitor structure for a semiconductor memory device |
| NL1005624C2 (en) * | 1997-03-25 | 2000-02-08 | United Microelectronics Corp | Poly:silicon CMP processing high density DRAM memory cell structure - includes depositing 1st and 2nd insulating, 1st and 2nd poly:silicon, 3rd insulating, removing redundant 2nd poly:silicon and 3rd insulating, forming dielectric & deposit 3rd poly:silicon |
-
1993
- 1993-09-17 JP JP05231531A patent/JP3085831B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0786433A (en) | 1995-03-31 |
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