JP3085282B2 - ATM buffering method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asyn)
More particularly, the present invention relates to an ATM buffering method in which buffering required for each processing unit is realized by a shared memory.

More specifically, in the present invention, in an ATM system having a plurality of processing units, each processing unit has a shared memory for sharing buffering, and multiplexes cells from the processing units. A having a cell multiplexing unit for writing to the shared memory and a cell separating unit for sending a cell from the shared memory to a target processing unit at the time of reading.
It relates to the TM buffering method.

Further, according to the present invention, there is provided a shared memory control unit for controlling writing and reading from the plurality of process processing units to the shared memory, and from the process processing unit to the shared memory control unit. It is characterized by having a control multiplexing unit for multiplexing read commands and write commands sent to it.

[0004]

2. Description of the Related Art As an example of this type of conventional technology, a publication 1
And Publication 2.

[0005] Publication 1 Author Akihiro Miyamoto et al. (NEC) Publication title Proceedings of the 1995 IEICE Society Conference B-558 Publication date August 30, 1995 Explanation page 225, No. 2 Publication 2 Author Hideaki Nakakita et al. (Toshiba) Title of the publication Proceedings of the Institute of Electronics, Information and Communication Engineers 1996 B-598 Date of issue: March 11, 1996 30, No. 2 Regarding the method of processing ATM cells, for example, as shown in Publication 1, an external memory is additionally provided at each buffering point.

FIG. 5 is a block diagram for explaining the technique described in Publication 1. As shown in FIG.

Referring to FIG. 5, as shown in FIG. 5, memories 215 to 218 are externally provided for the respective processing units from the process 1 processing unit 211 to the process n processing unit 214.

In these memories, it is necessary to temporarily store cells mainly for performing switching processing and scheduling processing. For this purpose, external memories 215-2 are used.
18 are used.

FIG. 6 is a block diagram for explaining the technique disclosed in Publication 2. As shown in FIG.

In the conventional method adopted by Publication 2, when cells are buffered, an object is defined as a buffering target instead of the cell itself, and the object is read and written.

Referring to FIG. 6, as shown in FIG. 6, after the cell arrives, an object is first generated from the information by the object generating section 301. The cells themselves are stored in a common shared memory 321 in the device by the shared memory control unit 322.

The processing in the apparatus is performed for each defined object, and buffering is also performed for this unit.

That is, what passes from the process 1 processing unit 311 to the process n processing unit 314 is not the cell itself, but an object generated by the cell.

Similarly, in the case of the external memory, the objects are temporarily stored in the object memories 315 to 318.

After all processes are completed, a cell corresponding to the object is read out from the shared memory 321 and transmitted. This reading is performed by the object termination unit 302
Is sent to the shared memory control unit 322.

In this way, the technique described in Publication 2 has an advantage that the amount of memory for buffering can be reduced as compared with the method disclosed in Publication 1.

In the conventional example disclosed in Publication 1, since it is necessary to provide a memory in every process processing unit in units of cells, it is necessary to provide a large amount of memory for the entire apparatus.

The reason is that the accumulated amount of cells in each processing unit is not always constant, and it is necessary to calculate the maximum amount of memory so as not to cause memory overflow and to provide each processing unit with the maximum amount. Because there is.

Alternatively, the amount of memory needs to be back calculated from the value based on the discard rate specified in the device specifications and the like. Need to have quantity.

The amounts of cells actually stored in these memories are exclusive. For example, when the amount of cells stored in a memory belonging to a certain processing unit is large, the amount of cells stored in a memory belonging to another processing unit is large. The causal relationship holds.

Further, the prior art represented by Publication 2 is intended to solve the problem of Publication 1 to some extent, and has an advantage that the device can be designed with a smaller memory amount than Publication 1. is there.

The reason for this is that the object to be defined has a smaller amount of data than a cell, and the amount of memory in each processing unit can be reduced.

Further, the cells to be actually stored are shared without having to be provided in each process processing unit, and the problem of the memory amount due to the above-described characteristic of cell storage having exclusive characteristics is solved. doing. As a result, the sum of the two types of memory in the device is smaller than that of the publication 1.

[0024]

However, problems still remain in the conventional method represented by Publication 2. The first problem is that an object is defined for the purpose of reducing the amount of memory in the device. The necessity of this processing causes an increase in circuit scale and internal delay.

For the purpose of managing the resources of the shared memory, it is necessary to constantly monitor whether the cell and the object correspond to each other, in other words, to monitor the object.

The second problem is that the problem inherent in the technology disclosed in Publication 1 cannot be completely solved.

The reason is that it is necessary to newly provide an object memory, and in order to apply the apparatus with a smaller memory amount, it is necessary to reduce the memory.

The present invention has been made in view of the above-mentioned conventional circumstances, and accordingly, an object of the present invention is to provide a novel ATM which can solve the above-mentioned problems inherent in the prior art.
It is to provide a buffering method.

[0029]

In order to achieve the above object, an ATM buffering system according to the present invention uses a process for temporarily storing cells, such as a switching process and a scheduling process, that is, a process requiring buffering. In an ATM system having a plurality of processing units, a shared memory for sharing the buffering between the processing units, a cell multiplexing unit for multiplexing cells from the processing units and writing the multiplexed cells to the shared memory, A cell separation unit configured to transmit a cell from the shared memory to a target process processing unit when the process processing unit performs reading to end buffering in the shared memory.

Further, the ATM buffering system according to the present invention provides an ATM system having a plurality of processing units which need a buffering process for temporarily accumulating cells such as a switching process and a scheduling process. A shared memory control unit for controlling writing and reading to and from the shared memory when performing buffering, and multiplexes a read command and a write command sent from the process processing unit to the shared memory control unit; It has a control multiplexing section for performing

When a write request command arrives in accordance with a command from each of the processing units, the shared memory control unit determines the address of the processing unit from the number and free address of the corresponding processing unit, and The address information is sent to the shared memory.

The shared memory control unit sends address information of a cell to be read out to the shared memory from the number of the corresponding process processing unit, and the cell from the shared memory is transferred to a predetermined process processing unit. A control signal is sent to the cell separation unit so that the cell read from the shared memory is controlled to be received by the corresponding process processing unit via the cell separation unit. And

Further, the shared memory control unit performs all of the management and assignment of free addresses of the shared memory.

[0034]

Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

[Structure of Embodiment] First, the structure of an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the ATM buffering system according to the present invention.

Referring to FIG. 1, reference numerals 111 to 114 denote process processing units, 121 denotes a shared memory, 122 denotes a shared memory control unit, 123 denotes a control multiplexing unit, 124 denotes a cell multiplexing unit,
Numeral 25 indicates a cell separation unit.

[Operation of Embodiment] Next, the operation of the embodiment according to the present invention will be described with reference to FIG. 1. First, when a cell is input to the device, the process 1 Is entered. This process 1 processing unit 111
When buffering becomes necessary in the course of the processing in, the process 1 processing unit 111
After that, a cell write request command is sent to the shared memory control unit 122. At the same time, the process 1 processing unit 111
Sends a cell to be written to the shared memory 121 via the cell multiplexing unit 124.

When a write request command arrives in accordance with a command from each process processing unit, the shared memory control unit 122 determines the address from the corresponding process processing unit number and free address and determines the address.
1 and sends the address information.

When the process 1 processing section 111 terminates buffering in the course of processing and reads cells,
The process 1 processing unit 111 passes through the control multiplexing unit 124,
A cell read request command is sent to the shared memory control unit 122.

The shared memory control unit 122 sends the address information of the cell to be read out to the shared memory 121 from the number of the corresponding process processing unit, and transfers the cell from the shared memory 121 to the target process processing unit. The control signal is sent to the cell separation unit 125 so that the control signal is transmitted.

At this time, the cell transmitted from the shared memory 121 is received by the process 1 processing unit 111 through the cell separation unit 125 at the beginning. The management and allocation of free addresses in the shared memory 121 are all performed by the shared memory control unit 122.
Done in

The cell is transferred from the process 1 processing unit 111 to the process 2 processing unit 112,
In the process, the same processing as the buffering described in the process 1 processing unit 111 is performed. Thus, when the processing by the process n processing unit 114 is completed,
A cell is transmitted from the device.

Next, the operation of the embodiment according to the present invention will be described in more detail according to the operation flow shown in FIGS. 2, 3 and 4.

FIG. 2 is a flowchart showing an example of an overall processing flow (Flow1) in one embodiment of the present invention, and FIG. 3 is a flowchart showing an example of a shared memory writing processing flow (Flow2) in one embodiment of the present invention. FIG. 4 is a flowchart showing an example of a shared memory read processing flow (Flow 3) according to an embodiment of the present invention.

Referring to FIGS. 1 to 4, in step S1 of the entire process (Flow 1) shown in FIG. 2, process i (i = 1 to n) processing units 111 to 114 are selected. This process processing includes a process 1 processing unit 111, a process 2 processing unit 112,.
It is assumed that the processing proceeds sequentially with the processing unit 114.

Next, the process i selected in step S1
The processing in the processing unit is executed. First, in step S2, a cell arrives. Next, in step S3,
The writing process of the cell arriving at the shared memory 121 is performed. The details of this write processing are the shared memory write processing (Flow 2) shown in FIG. 3, and will be described later in detail.

Subsequently, in step S4, processing is executed.

Next, in step S5, the shared memory 1
The process of reading the cell from 21 is performed. This shared memory read processing is shown in the shared memory read processing (Flow 3) in FIG. 4 and will be described later in detail.

Next, in step S6, a cell is transmitted.
The cell is transferred to the next processing unit.

Subsequently, in step S7, it is determined whether or not the processing unit to which the cell has been transferred is the final processing unit.
That is, it is determined whether or not i = n, and in the case of Yes, that is, if it is the final process processing unit, the process ends.

If the result of determination in step S7 is No,
That is, if it is not the final process processing unit, step S
At 8, the cell is moved (transferred) to the process i + 1 processing unit,
The processing of steps S2 to S7 described above is executed.

The above processing is performed by using i + 1 shown in step S9.
→ Execute until n.

Next, the shared memory write processing (Flow 2) shown in FIG. 3 will be described.

In step S11, when buffering becomes necessary in the course of processing, the process processing unit generates a write request command to the shared memory, and through command multiplexing of the control multiplexing unit in step S12,
Send to shared memory control unit.

Next, in step S13, an address is generated in the shared memory control unit based on the number of the corresponding process processing unit and the free address according to the write request command, and cell multiplexing is performed in the cell multiplexing unit in step S14.

Subsequently, in step S15, the address of the shared memory generated in step S13 is stored in step S15.
The cell multiplexed data is written into the shared memory at 14,
finish.

Next, the shared memory read processing (Flow 3) shown in FIG. 4 will be described.

First, in step S21, when reading out cells by terminating buffering in the course of processing, the process processing unit generates a read request command to the shared memory.

In step S22, the read request command is command-multiplexed in the control multiplexing unit.

In step S23, step S2
The shared memory control unit generates an address signal and a separation signal based on the signal multiplexed in step 2.

In step S24, the data at the address generated in step S23 is read from the shared memory.

Next, in step S25, processing in the cell separation unit is performed, and cells are separated by the cell separation signal.

The separated cells are transferred to the next processing section in step S26.

[0065]

As described above, A using the present invention
When the TM buffering method is applied to the device, the conventional memory overflow condition can be set without causing an increase in the circuit configuration and delay in the device caused by the addition of special processing such as object generation, termination, and monitoring. The device can be designed with a smaller amount of memory as compared with the method.

The reason is that the cells to be buffered are temporarily stored in the shared memory.
This is because the problem of the memory amount due to the exclusive characteristic of the cell storage is solved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment according to the present invention.

FIG. 2 is a flowchart illustrating an example of an overall processing flow (Flow1) according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an example of a shared memory write processing flow (Flow2) according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating an example of a shared memory read processing flow (Flow3) according to an embodiment of the present invention;

FIG. 5 is a block diagram illustrating buffering of ATM cells according to the prior art disclosed in Publication 1.

FIG. 6 is a block diagram illustrating buffering of ATM cells according to the prior art disclosed in Publication 2.

[Explanation of symbols]

 111 process 1 processing unit 112 process 2 processing unit 113 process 3 processing unit 114 process n processing unit 121 shared memory 122 shared memory control unit 123 control multiplexing unit 124 cell multiplexing unit 125 cell separation unit 211 ... Process 1 processing unit 212 ... Process 2 processing unit 213 ... Process 3 processing unit 214 ... Process n processing unit 215 to 218 ... Memory 301 ... Object generation unit 302 ... Object terminal unit 311 ... Process 1 processing unit 312 ... Process 2 processing unit 313: Process 3 processing unit 314: Process n processing unit 315 to 318 ... Object memory 321 ... Shared memory 322 ... Shared memory control unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/56 H04L 12/28 G06F 12/00

Claims (4)

(57) [Claims] 1. In an ATM system having a plurality of processing units which need a buffering process for temporarily accumulating cells, such as a switching process and a scheduling process, each of the process units is configured to share buffering. A shared memory, a cell multiplexing unit for multiplexing cells from each of the process processing units and writing the cells to the shared memory, and a readout by each of the process processing units to terminate buffering in the shared memory. a cell separation unit for delivering a cell to processing section of interest from the shared memory, each processing section is Ba
When performing buffering, writing and writing to the shared memory
A shared memory control unit for controlling read and read,
Sent from each process processing unit to the shared memory control unit.
Multiple read and write commands issued
AT having a control multiplexing section for performing
M buffering method. 2. When a write request command arrives according to a command from each of the process processing units, the shared memory control unit determines the address of the process processing unit from the corresponding process processing unit number and free address. 2. The ATM buffering method according to claim 1 , further comprising transmitting the address information to the shared memory. 3. The shared memory control unit sends address information of a cell to be read to the shared memory from the number of the corresponding process processing unit, and transfers the cell from the shared memory to a predetermined process processing unit. To be,
A control signal is transmitted to the cell separation unit, and control is performed so that a cell read from the shared memory is received by a corresponding processing unit via the cell separation unit. Item 2. The ATM buffering method according to Item 1 . Wherein said shared memory control unit, ATM buffering scheme of claim 1, further characterized by performing all the free address management and allocation of the shared memory.