JP3082189B2 - Semiconductor relay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reduces the capacitance between output terminals of a semiconductor relay for switching a weak signal at high speed,
Also, the present invention relates to an improvement to a high withstand voltage.

[0002]

2. Description of the Related Art Conventionally, mechanical relay contacts have been used exclusively for switching weak signals such as measurement signals and LSI testers. However, in a mechanical relay having a movable part, the reliability becomes unstable when the switching operation is performed about 50 million times, and there is a limit in improving the operation speed. On the other hand, an LSI tester needs to form a huge relay matrix, and it has been considered to use a semiconductor relay instead of a mechanical relay. FIG. 7 is an explanatory diagram of a changeover switch circuit of an LSI tester. 70 is the IC to be inspected
(LSI). The large current sources 71a to 71n are connected to the V / I source and the measurement unit (PPV) from the lateral direction.
The I-circuits 72a to 72n are connected in the vertical direction, and each intersection 73 forms a selection switch circuit as shown partially enlarged, forming a huge relay matrix. When measuring the leak current of the IC 70, all the stray capacitances of the measurement system including the relay matrix must be charged first. Therefore, it is necessary to use a relay having a small capacity between output terminals as a relay for switching the measurement signal. Further, an analog LSI tester requires a withstand voltage of about 150 to 200 V due to the properties of an IC to be measured. The measurement signal line of the above LSI tester is
As shown in the enlarged view in FIG. 7, the semiconductor device is composed of three lines of force, sense, and guard.
The characteristics of low capacitance between output terminals and low on-resistance are simultaneously required.

FIG. 8 is a circuit diagram of a semiconductor relay used in the selection switch circuit indicated by reference numeral 73 in FIG. 1 is an LED, 2 is a voltage output type photodiode array, 3
a and 3b are double diffusion MOS FETs (hereinafter DMOS F
ET), 4 is a control circuit. Input terminals IN1 and IN
The LED 1 emits light in response to an input signal given from the LED 2, the voltage of the emitted light is converted by a voltage output type photodiode array 2, and the voltage is converted to a DMOS FET3.
a, 3b are applied to the gates. DM of this switch element
Two OS FETs 3a and 3b are inserted in series (3a and 3b) to handle both positive and negative signals. The main capacitance between the output terminals OUT1 and OUT2 can be expressed as follows. That is, the equivalent circuit of the capacitance of one DMOS FET has a capacitance C _DG between the drain and the gate and a capacitance C _GS between the gate and the source which are connected in series and exist between this and the drain and the source. Capacitance C _DS
And can be represented in a form connected in parallel. But,
The gate-source capacitance C _GS is connected in parallel with the control circuit 4 that promotes the discharge of the gate when the photodiode array 2 and the semiconductor relay change from the ON state to the OFF state. Since it is sufficiently larger than the capacitance C _DG , it can be ignored. Therefore, one D
The capacitance between the output terminals of the MOS FET is the capacitance C _DS between the drain and the source and the capacitance C _DG between the drain and the gate.
Can be represented by a parallel circuit. Therefore, two DM
Output terminals OUT1, O2 to which OS FETs are connected in series
Major capacitance between UT2 can two series C _DS and two series C _DG approximates the equivalent circuit of the form of being parallel. There is a demand for a semiconductor relay having a small capacitance and a high withstand voltage. Vertical or horizontal DMOS FET as a switch element of this semiconductor relay
Can be considered.

[0004] Here, the disadvantages of the vertical DMOS FET and the characteristics of the horizontal DMOS FET are compared and the horizontal DMOFET is compared.
The advantages of improving the SFET will be described. FIG. 9 is a sectional structural view of a vertical DMOSFET. The current flows vertically. That is, the current flows from the source electrode 91 to N ⁺
High concentration impurity layer 92, P-BASE surrounding it
Inverted P-BAS facing layer 93 and gate electrode 94
Through the E layer 95, the epitaxial layer 96, the semiconductor substrate 9
7. Flow to the drain electrode 98. Discharge breakdown occurs in the Si bulk. The thickness and concentration of the epitaxial layer 96 forming the drift channel layer are closely related to the withstand voltage and the on-resistance. To reduce the drain-source capacitance C _DS, it is necessary to introduce a high degree of microfabrication techniques for minimize the small bonding area of the window of the DMOS cells forming P-BASE layer 93.

FIG. 10 is a plan view showing a general electrode shape of a lateral DMOSFET. It has a shape like a race track in which the gate electrode 14 and the source electrode 12 surround the drain layer 7 around the center. Drain-source capacitance C _DS for a larger area of the plan view 10 in the drain layer 7 is large. The concentration of the semiconductor substrate for determining the capacitance C _DS is convenient to have vertical DMOS epitaxial layer 96 features not closely related to the breakdown voltage, on-resistance than the concentration of (9) improved. In this corner, the drain layer 7
An uneven electric field is generated in accordance with the magnitude of the radius of curvature Rd. When this radius of curvature Rd is extremely small,
At the corners, the electric field concentrates near the drain layer 7 and the breakdown voltage is inevitably reduced. Reference numeral 16 denotes a bonding pad for wiring provided on the drain layer.

[0006]

An object of the present invention is to provide a semiconductor relay for switching a large number of weak signals at high speed,
An object of the present invention is to realize a semiconductor relay having a small capacitance between output terminals and a high withstand voltage.

[0007]

According to the present invention, there is provided a semiconductor relay which emits light by receiving an input signal, a photodiode array which receives the light-emitting signal, and a horizontal type which uses an output signal of the photodiode array as a gate input signal. DM
In a semiconductor relay comprising an OS FET, a semiconductor substrate having a low concentration of impurities and an elongated shape having a predetermined width formed on one surface of the semiconductor substrate, and both ends thereof are formed into an arc shape having a diameter larger than the width. A drain layer formed therein, and a drift layer formed in a similar shape to the drain layer with a certain width (drift channel length) from the drain layer so that a predetermined withstand voltage value is obtained by disposing the drain layer in the drain layer. A horizontal DMO comprising a gate electrode and a source layer formed outside the drift layer.
It consists of an SFET. The drain electrode provided at one end of the drain layer is made smaller by reducing the junction between the drain electrode and the drain layer in order to reduce the shock applied to the junction by ultrasonic waves or the like when bonding the wiring wire. The structure is filled with an oxide film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention focuses on the following points. (1) In order to reduce the capacitance C _DS between the drain and the source, to reduce the width of the drain layer. The drain-source capacitance _CDS is determined by the junction area between the drain layer and the drift layer and the underlying P- type semiconductor substrate at the same potential as the source electrode. Thus in order to reduce the drain-source capacitance C _DS, it is necessary to reduce the area of the drain layer of the DMOS FET center. In the drain layer, it is necessary to provide a region of a wire bonding pad, which is a portion where a drain electrode is exposed for wire wiring, to secure a minimum area where a wire from which an electrode is drawn can be stretched. Thus, a pattern is obtained in which a wiring area is secured at one end of the drain layer and the remaining area is sufficiently reduced. Further, in order to reduce the drain-source junction capacitance itself, the impurity concentration of the semiconductor substrate is made one digit lower than that of the epitaxial layer of the vertical DMOS FET (about 5 × 10 ¹³ [1 / cm ³ ] ).

(2) Another point in reducing the capacitance at the output terminal of the DMOS FET is to reduce the capacitance C _DG between the drain and the gate. On the other hand, since a low-concentration semiconductor substrate is used, the capacitance C _DG between the drain and the gate is generated by the N-type inversion layer formed on the Si surface. The area where the inversion layer is formed is reduced. (3) At the same time, the drift channel length Ld is determined so that the withstand voltage can be secured. (4) The corner portion of the track-shaped drift layer is formed into a circular shape having a radius of curvature larger than the drift channel length so that the concentrated electric field is reduced and a breakdown voltage equivalent to that of the straight portion can be secured.

FIG. 1 shows a horizontal DMOSFE used in the present invention.
It is sectional drawing of T. Reference numeral 5 denotes a semiconductor substrate in which impurities of the first conductivity type have a low concentration. Reference numeral 7 denotes one of the semiconductor substrates 5.
This is a semiconductor drain layer formed slenderly with a predetermined width on one surface. Both ends are formed in an arc shape having a diameter larger than the width of the drain layer. Reference numeral 8 denotes a drain electrode, which is locally joined to one end of the drain layer 7 to form an oxide film in other gaps to alleviate the shock at the time of wire wiring to reduce damage to the junction with the drain layer 7. This is a drain electrode having a structure for preventing the drain electrode. Reference numeral 6 denotes a drift layer in which the drain layer 7 is disposed. The drift layer 6 has a constant width (drift channel length Ld) from the drain layer 7 and has a similar shape to the drain layer so as to obtain a predetermined withstand voltage. It is a drift layer. Reference numeral 9 denotes a semiconductor diffusion layer of the first conductivity type impurity formed in the semiconductor substrate 5 apart from the drift layer 6. Reference numeral 10 denotes a semiconductor layer of a second conductivity type high-concentration impurity formed in the semiconductor diffusion layer 9. Reference numeral 11 denotes a semiconductor layer of the first conductivity type high-concentration impurity provided in contact with the semiconductor layer 10 and on the side remote from the drift layer 6. Reference numeral 12 denotes a source electrode commonly connected to the two layers of the semiconductor layer 10 and the semiconductor layer 11. Reference numeral 14 denotes a gate electrode formed from the semiconductor layer 10 to the drift layer 6 via the insulating film 13.

The current flows in the horizontal direction. That is, the inverted P-BA facing the gate electrode 14 from the source electrode 12
It flows through the SE layer 9 to the semiconductor substrate 5, the drift layer 6, the drain layer 7, and the drain electrode 8. The thickness of the oxide film in the overlap region between the drift layer 6 and the gate electrode 14 is larger than that of the vertical DMOS, and the capacitance C _DG between the drain and the gate is increased.
Can be kept low. Further, by adjusting the length Ld of the drift channel and the concentration thereof, it is possible to suppress discharge breakdown occurring near the Si surface. drain·
The concentration of the semiconductor substrate 5 to determine the source capacitance C _DS is, the higher the vertical DMOS epitaxial layer 96 (FIG. 9) pressure-resistant,
Not closely related to on-resistance. Thus reducing the capacitance C _DS between the drain and the source using the semiconductor substrate 5 having low impurity concentration. Therefore, the impurity concentration of the semiconductor substrate 5 is 5 ×
The density is set to about 10 ¹³ [1 / cm ³ ], which is lower by one digit than the concentration of the epitaxial layer 96 of the vertical DMOS FET. Reference numeral 13 denotes a silicon oxide insulating film. 15 is a protective cover.

FIG. 2 shows a configuration in which the drift layer 6 shown in FIG. 1 is divided into 6 a and 6 b by a drain layer 7. The capacitance C _DS can be further reduced. FIG. 3 is a plan view of the above-mentioned lateral DMOS FET. This FIG.
In FIG. 3, the drift layer 6 is additionally drawn for the cross section where the gate electrode 14 appears, and is schematically drawn. The width from the drain layer in the drift layer, that is, the drift channel length L
d is constant in a track-like plane. Reference numeral 14 is the same as the reference numeral in FIG. 6 is a drift layer.
7 is a drain layer. 12 is a source electrode. 16
Is a wire wiring region for extracting a drain electrode, which is a wire bonding pad.

FIG. 4 is an improved drawing of the vicinity of the drain electrode 8 of FIG. An example in which a bonding pad 16 whose electrode is exposed for wiring is formed on the drain electrode 8 is shown. Reference numeral 6 denotes a drift layer, reference numeral 7 denotes a drain layer, and reference numeral 8 denotes a drain electrode locally (two in the drawing) joined to the drain layer 7. A wiring wire is attached on the bonding pad of the drain electrode 8, but the connection is usually made by ultrasonic waves, so that the junction between the drain electrode 8 and the drain layer 7 is easily broken by the impact. For this reason, the drain electrode 8 and the drain layer 7 are locally joined, and an oxide film 13 is formed under the drain electrode 8 to reduce the vibration so that the junction is not damaged. Reference numeral 13 denotes an oxide film for insulation. 1
5 is a protective film covering the surface. Horizontal DMOSFET is 2
If the breakdown voltage is about 00 V, it is possible to secure a wire bonding pad on the field oxide film other than the drain layer 7. However, a parasitic capacitance is generated by the bonding pad portion, which causes an increase in the output terminal capacitance of the DMOS FET itself. Therefore, the low-concentration substrate 5 is used, and the wire bonding pad 16 is formed directly on the drain electrode, so that the capacitance at the junction caused by this is made smaller than the above-mentioned parasitic capacitance.

FIG. 5 is a characteristic diagram showing the relationship between the drift channel length Ld and the withstand voltage. The parameter that determines the breakdown voltage in the structure of the lateral DMOSFET is the drift channel length Ld. FIG. 5 shows a simulation result and an experimental result of the relationship between the drift channel length Ld and the breakdown voltage. This is in good agreement with the measured value. It can be seen that the length Ld of the drift channel should be about 10 to 15 μm to obtain a withstand voltage of 200 V.

FIG. 6 is a characteristic diagram showing the relationship between the radius of curvature Rd of the drain layer and the breakdown voltage. A factor that lowers the breakdown voltage of the lateral DMOSFET is the influence of the radius of curvature of the drain layer 7. At the corner opposite to the corner where the wire bonding pad 16 is located, an optimum radius of curvature Rd is determined by simulation so that the withstand voltage does not decrease. The connecting portion between the corner portion and the straight portion has a gentle streamline shape so that the breakdown voltage does not decrease. The predicted value of the breakdown voltage by simulation is that the radius of curvature is Rd = 30 μm
Although it decreases when the temperature falls below the level, this can be actually confirmed.

[0016]

As described above, the lateral DMOSFET has the above structure. (1) The capacitance between the output terminals of the lateral DMOSFET is 1.
It could be reduced to 7 pF. (2) Withstand voltage between output terminals became 300V practical. (3) By simulating the device,
The junction area and the gate length were reduced while maintaining the breakdown voltage, and the dimensions of the DMOS FET having a small capacitance between the output terminals became possible. As a result, a semiconductor relay having a high withstand voltage and a low capacitance between output terminals was realized.

[Brief description of the drawings]

FIG. 1 shows a lateral DMOSFET according to an embodiment of the present invention.
FIG.

FIG. 2 is a horizontal DMMOS having a drift layer divided into two parts.
It is sectional drawing of ET.

FIG. 3 is a plan view of a cross section where a drain layer of a lateral DMOS FET appears.

FIG. 4 is a diagram showing a bonding pad on a drain electrode.

FIG. 5 is a characteristic diagram showing a relationship between a drift channel length and a withstand voltage.

FIG. 6 is a characteristic diagram showing a relationship between a radius of curvature of a drain and a withstand voltage.

FIG. 7 is an explanatory diagram of a switching selection switch circuit of an LSI tester.

FIG. 8 is a circuit configuration diagram of a semiconductor relay.

FIG. 9 is a sectional structural view of a vertical DMOSFET.

FIG. 10 is an explanatory diagram of a general electrode shape of a lateral DMOSFET.

[Explanation of symbols]

Reference Signs List 1 LED 2 photodiode array 3a, 3b DMOS FET 4 control circuit 5 semiconductor substrate 6a, 6b drift layer 7 drain layer 8 drain electrode 9 P-BASE layer 10 first semiconductor layer 11 second semiconductor layer 12 source electrode 13 insulating oxide film Reference Signs List 14 gate electrode 15 protective film 16 bonding pad 70 IC under test 71a to 71n large current source 72a to 72n V / I source & measurement unit 73 selection switch circuit 91 source electrode 92N ⁺ high concentration impurity layer 93 P-BASE layer 94 gate Electrode 95 inversion layer 96 epitaxial layer 97 semiconductor substrate 98 drain electrode

Continuation of front page (56) References JP-A-7-46109 (JP, A) JP-A-62-2422 (JP, A) JP-A-62-132422 (JP, A) JP-A-62-298152 (JP, A) JP-A-5-235361 (JP, A) JP-A-4-192338 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H03K 17/78

Claims (4)

(57) [Claims] 1. A semiconductor relay comprising: an LED which receives an input signal and emits light; a photodiode array which receives the emission signal; and a lateral DMOS FET which uses an output signal of the photodiode array as a gate input signal. A semiconductor substrate having a width of not more than 10 ¹⁴ [1 / cm ³ ] ; a drain layer having an elongated shape having a predetermined width on one surface of the semiconductor substrate and having both ends formed in an arc shape having a diameter larger than the width. A drift layer formed with the drain layer disposed therein and surrounding the drain layer with a constant width (drift channel length); and a gate electrode formed on the opposite side of the drain layer with the drift layer interposed therebetween. And a source electrode comprising a lateral DMOS FET. 2. A lateral DMOS FET comprising a drift layer having a bisected shape with a drain layer interposed therebetween.
The semiconductor relay according to claim 1, comprising: 3. A lateral DMOS FET comprising a drain electrode having an oxide film formed in a gap between a part of a junction surface between the drain layer and the drain electrode.
Semiconductor relay described in the above. 4. A semiconductor relay comprising: an LED that receives an input signal and emits light; a photodiode array that receives the emission signal; and a lateral DMOS FET that uses an output signal of the photodiode array as a gate input signal. A semiconductor substrate (5) having a conductivity type impurity concentration of 10 ¹⁴ [1 / cm ³ ] or less; and a semiconductor substrate (5) formed on one surface of the semiconductor substrate (5) to be elongated with a predetermined width. A second-conductivity-type drain layer (7) formed in a large-diameter arc shape; and a drain electrode (8) having an oxide film formed in a gap between a part of a junction surface between the drain layer (7) and the drain electrode. A second conductivity type drift layer (6) formed with the drain layer (7) disposed therein and surrounding the drain layer (7) with a constant width (drift channel length); The first semiconductor layer of a high concentration impurity of the second conductivity type formed in the semiconductor substrate (5) semiconductor diffusion layer of the first conductivity type impurity formed in (9) in the away from the lift layer (6) (1
0) and a second semiconductor layer (11) of high concentration impurity of the first conductivity type provided in contact with the first semiconductor layer (10) and remote from the drift layer (6), and common to these two layers. A source electrode (12) connected to the first semiconductor layer (1);
A semiconductor relay comprising a lateral DMOS FET, comprising: a gate electrode (14) formed via an insulating film (13) from 0) to a drift layer (6).