JP3069333B2 - Multimedia multiplex receiving method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a two-wire system or a four-wire system.
The present invention relates to a multimedia multiplex receiving method and apparatus for receiving and reproducing a signal obtained by simultaneously multiplexing and transmitting a data signal and an audio signal from a host computer or a terminal device using a single line-type analog line, and particularly to a main data. The present invention relates to a multimedia multiplex transmission method and apparatus for superimposing another signal such as an audio signal on a data signal point obtained by converting the multiplexed signal and simultaneously receiving and reproducing a multiplexed signal.

In recent years, with the diversification of transmission media, multiplex transmission of various signals such as telephone voice signals, facsimile signals, data signals, and image signals has become possible. Has been realized.

On the other hand, most of the lines other than the trunk line are analog lines, and the analog lines cannot support a plurality of media. Therefore, the data signal is a 3.4 KHz line using a modem, and the voice is a telephone, The reality is that transmission is performed using separate lines, such as a voice-grade line using an in-band ringer, a switch, or the like.

[0004] Further, since digital lines take time to spread and have high running costs, there is still a strong demand for analog lines.

[0005] For this reason, multiplex transmission of a plurality of media such as data signals, audio signals, and image signals is also required for analog lines in order to reduce running costs.

[0006]

2. Description of the Related Art FIG. 80 shows an example of a utilization form of a conventional multimedia multiplex transmission system. At large-scale offices such as a head office 10 and a branch office 12, these are connected by a digital backbone line 14, and multimedia signals such as audio signals, data signals, and image signals are multiplexed using a multimedia multiplex transmission device. It is transmitted by one digital backbone line 14.

However, between the head office 10 and the branch offices 16-1 to 16-n connected to the branch office 12, individual analog lines 18-1 to 18-18 using public lines or dedicated lines are used to reduce running costs. -N is used.

For this reason, as shown in detail in FIG. 81, for example, between the head office 10 and each of the branches 16-1 to 16-n, a 3.4 kHz line using modems 20-1 to 20-n for data signals. 22-1 to 22-n, and the voice signal is a voice-grade line 26-1 using a telephone 24-1 to 24-n.
26-n. This point is the branch 12 and each branch 1
The same applies to 6-1 to 16-n.

Further, in a facsimile apparatus, since an analog line is used for both a voice signal and a data signal, image data and a voice signal are transmitted over one analog line by switching between a modem and a telephone.

[0010]

However, such a conventional multimedia multiplex transmission system has the following problems.

First, data communication and telephone communication are often used at the same time in communication between offices of a company, and the line switching method used in facsimile machines is inefficient, so that the head office 10 shown in FIG. Branch 12 and branch 1
As shown in 6-1 to 16-n, 3.4K is used for data communication.
Hz lines 22-1 to 22-n, and telephone-grade lines 26-1 to 26-n must be used for voice communication. By using separate lines, lines are required for media, Extra line charges are required. Also, communication equipment is required for the media, and equipment costs are incurred.

An object of the present invention is to provide a multimedia multiplex receiving method and apparatus for reproducing two types of signals such as a data signal and a voice signal from a multiplexed transmission signal using a single analog line.

[0013]

FIGS. 1 and 2 are diagrams for explaining the principle of the present invention.

[0014] First, the present invention provides a multimedia multiplex receiving method for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is allocated, and reproducing the first signal and the second signal. In the above, the second signal is reproduced by subtracting the data signal point determined from the transmission signal from the data signal point before the determination delayed by a predetermined time required for the determination. here
The following combinations can be used for the first signal and the second signal.
You. (A) first signal: data signal second signal; analog baseband signal (b) first signal: data signal and analog passband signal
Partially synthesized signal second signal: The remaining signal of the analog passband signal (c) first signal: first analog passband signal and the second A
A signal obtained by synthesizing a part of the analog passband signal. The second signal: the remaining signal of the analog passband signal

As described above, the data signal point before the determination is delayed by the time necessary for the determination of the signal point, and then the difference from the determined data signal point is obtained. Can be accurately separated and reproduced.

According to the multimedia multiplex receiving method of the present invention, a judging step of judging a data signal point from a transmission signal and a delaying step of delaying a data signal point before judging by the judging step by a predetermined time necessary for judging. And an adding step of extracting the second signal by subtracting the data signal point determined in the determination step from the data signal point before determination delayed in the delay step.

In the determination step, maximum likelihood detection is performed to determine a likely data signal point according to a Viterbi decoding procedure (Viterbi algorithm).

The first and second signals to be repeated according to the present invention include:

A data signal is reproduced as a first signal, and an analog passband signal converted from an analog signal is reproduced as a second signal (first invention).

A signal obtained by combining the data signal and a part of the analog passband signal is reproduced as the first signal, and the remaining analog passband signal is reproduced as the second signal (second invention).

A signal obtained by combining a part of the first analog bandpass signal and a part of the second analog passband signal is reproduced as the first signal, and the remaining signal of the second analog passband signal is reproduced as the second signal. (Third invention).

Further, the present invention provides a multimedia multiplex receiving apparatus for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is allocated and reproducing the first signal and the second signal. Here, the second signal is reproduced by subtracting the data signal point determined from the transmission signal from the data signal point before the determination delayed by a predetermined time required for the determination. Here, the first signal and the second signal are the following combination
Can be used. (A) first signal: data signal second signal; analog baseband signal (b) first signal: data signal and analog passband signal
Partially synthesized signal second signal: The remaining signal of the analog passband signal (c) first signal: first analog passband signal and the second A
A signal obtained by synthesizing a part of the analog passband signal. The second signal: the remaining signal of the analog passband signal

The reproducing means includes a judging means 62 for judging a data signal point from a transmission signal, a delay means 70 for delaying a data signal point before judgment by the judging means 62 by a predetermined time necessary for judgment, and a delay means 72. And an adder for extracting the second signal by subtracting the data signal point determined by the determiner from the delayed data signal point before the determination.

The judging means 62 has a soft judging means for judging a likely data signal point in accordance with the Viterbi decoding procedure. The first signal and the second signal reproduced by the multimedia multiplex receiving apparatus are the same as in the case of the method.

[0025]

By removing the echo component contained in the received signal, it is possible to improve the signal quality when a two-wire analog line is used in full-duplex as a transmission path.

The following is a more detailed description. [Voice + Data] FIG. 1 shows a first invention of the present application. As shown in FIG. 1A, multimedia multiplex transmission in which a transmitting unit 30 and a receiving unit 32 are connected via an analog line 46 is performed. set to target.

The transmission section 30 stores the main transmission data in 2
Data transmitting means for converting a data signal point in a dimensional coordinate space and transmitting a modulated signal obtained by modulating the data signal point; converting an analog passband signal into an analog baseband signal; and converting the analog baseband signal into a data signal point And multiplexing means for superimposing and transmitting the signals.

The receiving section 32 includes a data reproducing means for receiving the transmission signal from the transmitting section 30 from the analog line 46 and reproducing the original transmission data, and a data reproducing section for separating the analog baseband signal from the received signal and then reproducing the original signal. And an analog reproducing means for performing an inverse conversion to an analog passband signal.

The data transmitting means of the transmitting section 30 includes a data signal point generating means 38 for inputting transmission data in a predetermined length unit to generate a corresponding data signal point, and a data signal point generated by the data signal point generating means 38. And a modulating means 42 for transmitting a modulated signal (PSK, QAM, TCM, or the like) obtained by modulating the signal with two components of amplitude and phase.

The multiplexing means of the transmitting section 30 comprises: a baseband conversion means 50 for converting an analog passband signal in a passband such as a voice signal or a facsimile signal into an analog baseband signal in a baseband; And an adding means for adding the analog baseband signal from the means to the data signal point.

The data reproducing means of the receiving section 32 includes a demodulating and equalizing means 60 for demodulating and equalizing the modulated signal from the received signal, and a judging means 62 for judging a data signal point from the demodulated signal obtained by the demodulating and equalizing means 60. Code conversion means 64 for restoring the original transmission data from the data signal points determined by the determination means 62
At least.

The analog reproduction means of the receiving section 32 calculates the difference between the signal before the judgment by the judgment means 62 and the signal after the judgment and demodulates the baseband signal by the baseband demodulation means 72.
And a passband conversion means 76 for converting the baseband signal from the baseband demodulation means 72 into a passband and reproducing the original analog passband signal.

Normally, the transmitting section 32 is provided with a scrambling means 36 for scrambling transmission data input to the data signal point generating means 38, and eliminates data correlation in order to enable automatic equalization on the receiving side. Therefore, the analog baseband signal superimposed on the main data signal point is also subjected to random conversion by the random conversion means 52 to eliminate data correlation.

In response to this, the receiving section 32 is provided with a descrambling means 66 for descrambling the converted signal from the code converting means 64 to reproduce the original transmission data. There is provided random inverse conversion means 74 for performing random inverse conversion of the baseband signal from the means 72 and converting it into the original analog passband signal.

In this case, the random conversion means 52 performs random conversion on the analog baseband signal corresponding to the data scrambled by the scramble means 36, and the inverse random conversion means 74 supports the conversion data of the code conversion means 64. Thus, the signal from the baseband demodulation means 72 is inversely transformed at random.

In order to improve the signal quality, the data signal point generating means 38 of the transmitting section 30 includes trellis coding means for converting the generated signal points of the transmission data into data signal points in accordance with the trellis coding procedure. 32 determination means 6
2 includes soft decision means for determining a likely data signal point according to a Viterbi decoding procedure (maximum likelihood estimation method).

The multiplexing means of the transmitting section 30 includes an amplitude limiting means 54 for limiting the amplitude of the analog baseband signal superimposed on the main data signal point. Amplitude limiting means 54
It is desirable to control the amplitude limit value of the analog baseband signal by feeding back the signal quality status of the receiving unit 32 of the partner station to the own station. [Data + voice; voice separated into digital and analog]
FIG. 2C is an explanatory view of the principle of the second invention of the present application.

According to the second aspect of the present invention, the transmitting section (30) includes a separating section 255 for separating the analog baseband signal from the baseband converting section 50 into an analog signal component and a digital signal component, and the separated digital signal as transmission data. A time-division multiplexing means 254 for time-division multiplexing and transmission by a data transmission means, and an adding means 40 as an analog multiplexing means for transmitting a separated analog signal by superimposing it on a data signal point are provided. .

In response to this, the transmitting section 32 includes a time division distribution means 258 for separating the original transmission data and the digital signal component of the baseband signal from the data corresponding to the reproduced data signal point, and a time division distribution means. And a signal synthesizing unit 256 for synthesizing the original baseband signal based on the digital signal component from the analog demodulation unit 72 and the analog signal component from the analog demodulation unit 72. [Voice + Voice] FIG. 2 (d) is an explanatory diagram of the principle of the third invention of the present invention, wherein two channels of voice signals are simultaneously multiplexed and transmitted.

For this reason, the transmitting section 30 of the third aspect of the present invention includes a phase quantization means 314 for converting the phase information of the baseband signal converted from the analog passband signal into a quantized phase signal, and a phase quantization means 314 for converting the amplitude of the baseband signal. Separation means for separating a quantized amplitude signal and a quantized residual analog signal are provided for each channel of two analog passband signals, and further, a quantized phase signal and a quantized amplitude signal for two channels are transmitted and transmitted. Time-division multiplexing means 254 for performing time-division multiplexing, data transmission means for converting time-division multiplexed transmission data into data signal points in a phase space, and transmitting a modulated signal obtained by modulating the data signal points; After combining one of the quantized residual analog signals generated by the separation means 255 for each channel as a real component and the other as an imaginary component, the data signal is synthesized. Characterized in that a adding means 40 as an analog multiplexing means for transmitting superimposed on.

In response to the transmission side, the receiving unit 32 reproduces the quantized phase signal and the quantized amplitude signal for two channels from the data corresponding to the reproduced data signal points, and separates them for each channel. Distributing means 258 and analog demodulating means 72 for extracting a quantized residual analog signal based on the reproduced data signal point and separating the signal into a real component and an imaginary component are provided. Phase dequantization means for dequantizing the quantized phase signal to demodulate the phase signal, amplitude dequantization means for dequantizing the quantized amplitude signal from the time division distribution means 258 and demodulating the amplitude value, Signal combining means 25 for combining the original baseband signal from the phase signal and amplitude value obtained by the inverse quantization and the analog demodulated signal from the analog demodulating means.
6 and a passband conversion means 76 for converting the signal into an original analog passband signal.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Table of Contents> 1. Basic embodiment of first invention 2. Detailed embodiment of the first invention transmission unit 3. Operation of first invention transmitting section 4. Detailed embodiment of first invention receiving unit 5. Operation of first invention receiving unit 6. Another embodiment of the first invention 7. Basic embodiment of second invention 8. Details of the second invention transmission unit Operation of second invention transmitting section 10. Details of second invention receiving section 11. Operation of second invention receiver 12. Basic embodiment of third invention for transmitting two channels of audio 13. 13. Details of the third invention transmission unit Operation of third invention transmitting section 15. Details of third invention receiving section 16. Modified embodiment of third invention Basic Embodiment of First Invention FIG. 3 is a configuration diagram showing a basic embodiment of the first invention of multimedia multiplex communication of the present invention, taking a modem as an example.

In FIG. 3, the modem includes a transmitting unit 30 and a receiving unit 32. The transmission unit 30 includes a scrambler 36, a data signal point generation unit 38 having a trellis coding function, a data modulation unit 42, and a hybrid circuit 42 for transmitting main transmission data 34.
In order to simultaneously transmit an analog passband signal 48 such as voice or facsimile, a baseband conversion unit 50,
A random conversion unit 52, an amplitude limiting unit 54, and an adding unit 40 are provided.

An analog passband signal such as voice or facsimile signal is converted into an analog baseband signal by a baseband conversion unit 50, and subjected to random conversion by a random conversion unit 52 for non-correlation.
To limit the amplitude, and the adder 40 performs the main transmission data 3
4 is superimposed on the data signal point obtained from step 4, and is simultaneously transmitted as a noise component of the data signal point of the main transmission data.

On the other hand, the receiving unit 32 of the modem is
0, a soft decision unit 62 for determining a data signal point according to the Viterbi algorithm, a code conversion unit 64 for converting the data signal point into a bit sequence, and a descrambler unit 66.
In addition to such a main transmission data receiving system, a delay circuit 70, an addition unit 72 having a baseband demodulation function, and a delay circuit 70 for reproducing analog passband signals such as voice or facsimile superimposed as noise components of data signal points.
A random inverse transform unit 74 and a passband transform unit 76 are provided.

The modem side includes a transmitting unit 30 and a receiving unit 32
, The hybrid circuit 44
, The transmission line 30 and the reception unit 3
2 to realize full-duplex transmission. An echo estimator 56 is provided between the hybrid circuit 44 and the receiver 32.
And an adder 58 having an echo component removing function of removing the echo component estimated by the echo estimator 56 from the received signal from the hybrid circuit 44.

In the present invention, since the analog baseband signal such as voice is superimposed on the data signal point of the main transmission data as a noise component and transmitted simultaneously, the level of the analog baseband signal is maintained at the main signal level. It is necessary to keep transmission data transmission within a range that does not affect transmission.

FIG. 29, the modulation speed is 2400 baud, the number of bits allocated per thin-hole is 2
Bit / symbol and data transmission rate of 4800bp
9 shows error rate characteristics of a data signal in the case of the s mode.

In the error rate characteristic of the data signal, the S / N ratio of the data signal at a 1/10000 error rate, that is, an error rate of 1 × 10 ⁻⁵ is about 15 dB. On the other hand, in the case of an analog audio signal, the standard value is about 28 dB.
8 dB, and the analog line uses S /
There is room for N.

In the present invention, the S / N margin in the analog line is used for transmitting analog signals such as voice and facsimile, and the analog signal is superimposed on the data signal to be simultaneously transmitted through a single analog line. Transmit. For this reason,
The level of the analog signal to be superimposed on the data signal is, as shown in the level range 35-1, in the analog line of the standard value,
The level may be lower than the level of the main data signal by 15 dB or more and higher than the standard value by 28 dB or more. When the line quality is good, as shown in the level range 35-2, the level of the main data signal is higher than the level of the main data signal by 15 dB.
A lower level and a level higher than 38 dB may be applied to the analog signal.

The amplitude controller 54 provided in the transmitter 30 of FIG.
Will limit the amplitude so as to fall within a level applicable to analog signals such as audio shown in FIG. 4, for example.

More preferably, the signal quality SQD of the receiving unit of the partner station is received by using the secondary channel transmitting the monitoring signal, and the amplitude limiting unit 54 is adapted to optimize the signal quality SQD of the partner station. It is desirable to set an amplitude limit value. 2. Detailed Embodiment of the First Invention Transmitter FIG. 5 is an embodiment configuration diagram showing details of the transmitter 30 in the modem of the first embodiment shown in FIG.

In FIG. 5, the transmitting unit 30 includes a processor unit 75 in terms of hardware, an analog LSI unit 55 for converting an analog passband signal 48 such as voice or facsimile into a digital signal, and a processor unit 7.
5 is composed of an analog LSI section 45 for converting the transmission modulation data from 5 into an analog modulation signal, and a hybrid circuit 44.

More specifically, the processor unit 75 is composed of a microprocessor (MPU) and a digital signal processor (DSP). The main transmission data system includes a scrambler unit 36 and a data unit having a trellis coding function. Signal point generator 38, data modulator 4
2 functions are realized. On the other hand, the functions of the baseband converter 50, the random converter 52, the amplitude limiter 54, and the adder 40 are realized as a system for superimposing an analog signal such as voice or facsimile on the data signal point of the main transmission data.

Further, in order to remove the estimated echo component from the signal received from the hybrid circuit 44, the echo estimating unit 5
6 and the function of the addition unit 58 and the function of the optimum amplitude limit value determination unit 108 for setting the optimum amplitude limit value for the amplitude limit unit 54 based on the signal quality signal SQD of the partner station.

An analog L for converting an analog passband signal 48 such as voice or facsimile into a digital signal
The SI unit 55 includes a low-pass filter 90 and an A / D converter 92. The low-pass filter 90 cuts high frequency components of an analog passband signal from a telephone, a facsimile or the like, and extracts a voice band component such as a voice signal. A /
The D converter 92 converts the audio band component from the low-pass filter 90 into a digital signal and inputs the digital signal to the processor unit 75.

An analog LSI section 45 for converting modulated data from the processor unit 75 into an analog signal.
Includes a D / A converter 86 and a low-pass filter 88. The A / D converter 86 is a processor unit 75
Is converted into an analog modulation signal. The low-pass filter 88 removes unnecessary band components of the analog modulation signal.

Next, details of each unit realized by the processor unit 75 will be described.

First, the scrambler unit 36 randomizes the transmission data 34 from the host computer, the terminal device, or the like to obtain uncorrelated data. The function of the scrambler 36 is described in, for example, V. CCITT. The transmission data 34 is randomized by the generator polynomial recommended in 29. In the randomization of the transmission data 34 by the scrambler 36, generally, the transmission data has a correlation, and when the data having the correlation is transmitted, the tap coefficient of the automatic equalizer provided on the receiving side does not converge, and a stable automatic transmission is performed. This is to prevent the equalization from becoming difficult.

Next, the data signal point generator 38 will be described.
In this embodiment, the data signal point generation unit 38 has a trellis coding function, and the CC. Encoding into data signal points by the method recommended in 33. CC
ITT V. Regarding the content recommended in 33, 199
It is known from the publication "Data Communication by Modem and Telephone Network" published by CQ Publishing Company on Nov. 20, 2008.

FIG. 6 shows V.I. of CCITT. 320 by 33
FIG. 3 is a configuration diagram of an embodiment of a data point signal generation unit having a trellis coding function adapted to 0 baud, 3 + 1 bits / symbol, and 9600 bps mode.

In FIG. 6, a data signal point generator 38 converts a phase difference constituted by a code converter 110-1 for performing serial / parallel conversion and Gray code / natural code conversion, a conversion table 114 and taps 116 and 118. It comprises a difference circuit, a convolutional encoder 120 and a signal point generating ROM 112-1.

The serial output of the transmission data randomized by the scrambler 36 is converted into 3-bit parallel data for each symbol by the code converter 110-1, and the parallel data is further converted into a natural code as a gray code. Two bits of the three-bit output from the code conversion unit 110-1 are input to the conversion table 114, a phase difference is obtained for each bit by feedback inputs of taps 116 and 118, and the two bits after the difference are convolutionally encoded. Input to the converter 120 and converted into 3-bit information.

Finally, the signal point generating ROM 112-1
Then, a corresponding data signal point (symbol) is generated by using 1 bit from the code conversion unit 110-1 and 3 bits from the convolutional encoder 120 as a total of 4 bits as an address.

Here, the CCITT V.V. 32 by 33
In the mode of 00 baud, 3 + 1 bits / symbol, and 9600 bps, 16-level signal points as shown in FIG. 7 are used, and the 16 signal points in FIG. The data of the corresponding signal point is read out by addressing with 4-bit data generated by trellis coding.

FIG. 8 shows the details of the data signal point generator 38 having a trellis coding function in the case of 2400 baud, 6 + 1 bits / symbol, and 14400 bps mode. Also in this case, the data signal point generating unit 38 includes a code conversion unit 110-2 having a function of serial / parallel conversion and a function of gray code / natural code conversion, and a conversion table 114.
And a difference circuit for obtaining a phase difference composed of the signals 116 and 118, a convolutional encoder 120, and a signal point generating ROM 112-2.

In the 14400 bps mode, since 7-bit data is generated, the number of data signal points is 128.
The signal point generation ROM 112-2 receives the address designation of 7 bits and reads out a corresponding one of the 128 signal point data.

Referring again to FIG. 5, a data modulation section 42 provided subsequent to the addition section 40 for superimposing an analog baseband signal on a data signal point includes a roll-off filter section 80, a modulation section 82, and a carrier generation section. 84. The roll-off filter unit 80 shapes the waveform by limiting the band of the signal obtained by superimposing the baseband analog signal on the data signal point from the adding unit 40.

The carrier generator 84 generates a carrier carrier signal of 1850 Hz. The modulator 82 includes a multiplier 124 and a real part extractor 128, as shown in FIG. That is, the 1850 Hz carrier carrier signal from the carrier generator 84 is multiplied by the signal from the roll-off filter 80 by the multiplier 124 and demodulated, and only the real component is extracted by the real part extractor 128 from the demodulated signal of the multiplier 124. And outputs it to the next-stage analog LSI unit 45.

As another embodiment of the modulation section 82 used in this embodiment, as shown in FIG. 10, a data signal point is modulated by a modulation section 80 using a carrier signal from a carrier generation section 84, and then modulated. Alternatively, a configuration in which the band is limited by the roll-off filter 82 may be used.

Next, the baseband converter 50 shown in FIG. 5 will be described. The baseband converter 50 comprises a demodulator 94, a carrier generator 96 and a low-pass filter 98.
The details of the demodulation unit 94 are shown in FIG. 11, and include multipliers 136 and 138 for each real component and imaginary component. The carrier generation unit 140 generates a clockwise rotation signal at -1850 Hz, and multipliers 136 and 13 for the real component and the imaginary component of the analog passband signal to which the real component R and the imaginary component I of the carrier signal are input.
By multiplying by 8, the baseband signal is converted into a real component and an imaginary component.

In such conversion to a baseband signal, since both the sum component and the difference component accompanying demodulation are output, unnecessary sum components are removed by the low-pass filter 98, and only the difference component is removed. Take it out as a baseband signal. FIG. 12 shows the band characteristics of an analog passband signal input to the baseband conversion unit 94. The low-pass filter 90 provided in the analog LSI unit 55 in the preceding stage has a low-pass filter characteristic 176. Taking an audio signal 174 as an example, a signal in an audio band (pass band) of 0.3 to 3.4 kHz is input as shown in the figure.

Such an analog passband signal is converted by the baseband conversion section 50 into the -1.55k signal shown in FIG.
Hz is converted into a baseband audio signal 178 centered on 0 kHz of +1.55 kHz, and the low-pass filter 98 performs band limitation according to the low-pass filter characteristic 180 to extract only a difference component obtained by demodulation. .

As another embodiment of the baseband converter 50 used in the embodiment of FIG. 5, a configuration using a Hilbert filter shown in FIG. 14 may be used.

The baseband converter 50 shown in FIG. 14 comprises a Hilbert filter 130, a multiplier 132 and a carrier generator 134. The Hilbert filter 130 receives the scalar signal from the analog LSI unit 55 and converts it into a vector signal. The multiplier 132 is a Hilbert filter 1
The passband signal is converted to a baseband signal by multiplying the vector signal from the carrier signal 30 by the carrier vector composed of a clockwise rotation signal at -1850 Hz from the carrier generator 134.

When the Hilbert filter 130 is used, unnecessary components such as a sum signal do not occur.
The low-pass filter 98 provided in the embodiment is unnecessary.

Next, the random conversion unit 52 in FIG. 5 will be described. The random conversion unit 52 includes a bit extraction unit 100 and a phase conversion unit 102. Details of the bit extraction unit 100 and the phase conversion unit 102 are described in CCITT 3 by 33
200 baud, 3 + 1 bits / symbol, 9600 bps
The mode is shown in the configuration diagram of the embodiment in FIG.

In FIG. 15, the bit extraction unit 100 includes a serial / parallel conversion unit 100-1. The serial / parallel converter 100-1 operates with a 3200 baud modulation / synchronization clock 142-1 and outputs 3-bit parallel data “X ₂ X ₁ X ₀ ” for serial data from the scrambler 36 obtained for each clock. Is converted to

Here, when the data bit string from the scrambler 36 is arranged from right to left,... C ₂ C ₁ C ₀ B ₂ B ₁ B ₀ A ₂ A ₁ A ₀ becomes 3 bits / symbol. It is possible to distinguish each symbol, and as shown in FIG. 16, a parallel output “X ₂ X ₁ X ₀ ” divided for each symbol is generated with respect to the bit extraction output from the scrambler unit 36.

The phase converter 102 stores an 8-level phase change angle using the parallel outputs X ₂ , X ₁ , and X ₀ from the bit extractor 100 shown in FIG. 17 as addresses, and stores any one of the corresponding phases. Outputs the angle of change.

In the case of the 9600 bps mode shown in FIG. 15, the number of phases 8 of the random phase signal generated by the phase converter 102 and the number of bits for each symbol input from the scrambler 36 match 3 bits. Therefore, no particularly complicated processing is required.

FIG. 18 shows V.I. of CCITT. 24 by 29
FIG. 3 is a diagram illustrating an embodiment of a random conversion unit 52 used in a mode of 00 baud, 2 bits / symbol, and 4800 bps;
The bit extraction unit 100 is provided with a serial / parallel conversion unit 100-2 which operates with a modulation synchronization clock 142 of 2400 baud and converts the serial output from the scrambler unit 36 into the number of bits per symbol.

In the 4800 bps mode, when the data bit string output from the scrambler section 36 is arranged from right to left,... D ₁ D ₀ C ₁ C ₀ B ₁ B ₀ A ₁ A ₀ / Symbol, which is smaller than eight phases, which is the number of random phase signals generated by the phase converter 102.

Therefore, the serial / parallel converter 100
There -2 converts 2 bits per symbol of the data bit string as scrambler unit outputs the parallel output of the 3 bits as shown in FIG. 19, "X ₂ X ₁ X _0". The conversion into the 3-bit parallel output is performed so as to be constituted by the last bit of the previous symbol and the two bits of the next input data bit string.

The conversion content of phase conversion section 102 is the same as that of FIG. 17, and receives the address designation by 3-bit parallel output “X ₂ X1 X ₀ ” of parallel conversion section 100-2 and outputs the corresponding phase change angle. I do.

In this embodiment, random phase modulation using eight phases is taken as an example. However, if it is desired to further enhance the randomization, the number of phases is increased, for example, using 16-phase random modulation. Is also good. Further, in this embodiment, randomization is performed only in the phase direction. However, when amplitude modulation is performed on data signal points at the same time, a random change in amplitude may be added. In any case, analog signals such as correlated voices and facsimile signals may be randomized and uncorrelated.

Referring again to FIG. 5, the bit extraction unit 10
The multiplication unit 104 multiplies the analog baseband signal from the baseband conversion unit 50 by the zero and the random phase signal extracted based on the transmission data randomized by the scrambler 36 by the phase conversion unit 102 to obtain the baseband signal. Is rotated by a random phase signal to be randomized.

Next, the amplitude limiter 54 for limiting the amplitude of the randomized baseband signal and the optimum amplitude limit value determiner 108 will be described.

First, the optimum amplitude limit value judging section 108
As shown in (1), a ROM 148 is provided, a signal quality signal (SQD) 106 and modulation mode information 146 from a partner station are input as addresses, and an optimal amplitude limit value 150 stored in advance is output.

Here, as the modulation method mode information 146, for example, 29, 2400 baud, 2 bits / symbol, 4800 bps mode, or V.29. 33 of 320
Information indicating the contents of 0 baud, 3 + 1 bits / symbol, and 9600 bps mode.

FIG. 21 is a block diagram of an embodiment of the amplitude limiter 54. First, the baseband signal 152 is input to the automatic gain controller 154, and the peak value of the baseband signal 152 is amplitude-controlled using the amplitude limit 150 as a reference signal. Limit to limit value 150. The output of the automatic gain control unit 154 is separated into a real component R and an imaginary component I,
At 56 and 164, the amplitude limit value 150 is added. The outputs of the adders 156 and 164 are limited by the limiters 158 and 162, respectively, and then supplied to the adders 160 and 168.

On the other hand, the polarity of the amplitude limit value 150 is inverted by multiplying “−1” by the multiplier 172, and the
0,168. Therefore, the adders 160, 1
68 adds the amplitude limit value 150 whose polarity has been inverted to each of the real component R and the imaginary component I, and finally outputs the result to the adder 40 for superimposition on the data signal point through the limiters 162 and 170.

The automatic gain control unit 154 provided at the input stage of the amplitude limiting unit 54 does not cause any problem. However, the provision of the automatic gain control unit 154 enables optimal control of the overall S / N ratio. Thus, the signal quality can be improved, and in the case of an audio signal, good sound quality can be obtained. 3. Operation of the first invention transmitting unit The operation of the transmitting unit 30 shown in FIG. 33
3200 baud, 2 + 1 bits / symbol, 960
A description will be given taking the 0 bps mode as an example.

The transmission data 34 output from the host computer or the terminal device is input to a scrambler unit 36 of the transmission unit 30 and is randomized to converge tap coefficients in an automatic equalizer provided on the reception side. Make it possible.

The scrambled data from the scrambler section 36 is input to a data signal point generating section 38 having a trellis coding function, and is converted into 3-bit parallel data as shown in FIG. The error rate is optimized by code conversion, the phase difference of two bits of the parallel output is obtained, then the data is converted to 3 bits by folding coding, and finally converted to 4-bit information.

The newly added 1 bit is a signal having redundancy, and the trellis encoding enables error correction by the maximum likelihood estimation method in accordance with the Viterbi algorithm on the receiving side. Finally, the data signal point generator 38 obtains any of the 16 signal points shown in FIG. 7 from the 4-bit data obtained by trellis coding.

On the other hand, if an audio signal is taken as an example of the analog passband signal 48, the audio signal is a signal having a band of 0.3 to 3.4 kHz as shown in FIG. Unnecessary band components are removed at 90 and converted into digital signals by an A / D converter 92, and then input to the processor unit 75.

The digital audio signal from the analog LSI unit 55 is converted by the baseband conversion unit 50 into an analog passband signal shown in FIG. Here, a carrier frequency of 1850 Hz, which is the center frequency of the audio band, is generated from the carrier generation unit 96 of the baseband conversion unit 50,
An audio baseband signal is obtained by the demodulation unit 94. in this case,
Since both the sum component and the difference component are output with demodulation, unnecessary sum components are removed by the low-pass filter 94.

The audio baseband signal converted by baseband conversion section 50 has a correlation showing distribution 184 shown in FIG. 22A on the phase plane, and is represented by one vector 182 in distribution 184 at a certain point in time. It is.

On the other hand, the random conversion section 52 receives the scrambled data from the scrambler section 36, converts it into 3-bit parallel data as shown in FIGS. In synchronization with the baud modulation synchronization clock, a random phase signal is generated as shown in FIG.
One of the eight phase change angles shown in (B) is generated.

This random phase signal is multiplied by the audio baseband signal from the baseband conversion unit 50 in the multiplication unit 104, and rotated on the phase plane by each phase change angle, as shown in FIG. It is converted to a randomized audio baseband signal.

Subsequently, the audio baseband signal randomized by the amplitude limiter 54 is limited to a level range that does not hinder the transmission of the main transmission data, and is superimposed on the data signal point by the adder 40.

The amplitude limit value of the amplitude limit unit 54 is controlled by the optimum amplitude limit value judgment unit 108. The optimum amplitude limit value determination unit 108 receives the aperture of the signal point on the receiving side, that is, the signal quality (SQD) 106, and obtains the amplitude of the analog baseband signal randomized to the optimum amplitude limit value. Restrict.

The adder 30 superimposes the randomized audio baseband signal whose amplitude is controlled to the optimum value from the amplitude limiter 54 on the signal point of the arbitrary data from the data signal point generator 38, 42.

The superimposed output of the audio baseband signal on the data signal point from the adder 40 is shaped into a waveform by the roll-off filter 80 of the modulator 30, and then modulated by the carrier 82 from the carrier generator 84. The signal is modulated, and only the real component is extracted and output to the analog LSI unit 45. In the analog LSI unit 45,
After being converted into an analog modulation signal by the D / A converter, the high-frequency component accompanying the sampling frequency is removed by the low-pass filter 88 and output to the hybrid circuit 44.

The hybrid circuit 44 has an analog line 46
Are two lines, and the modem side is four lines of the transmission unit 30 and the reception unit 32, so that the signals are combined and distributed in order to perform two-wire full-duplex transmission. An analog modulation signal from the LSI unit is sent to a two-wire analog line 46.

Here, in order to perform full-duplex communication on the two-wire analog circuit 46, it is necessary to remove the echo component of the transmission signal included in the reception signal from the hybrid circuit 44.

The echo component is calculated from the signal obtained by superimposing the audio baseband signal on the data signal point from the adder 40 by the echo estimator 56 provided in the processor unit 75, and the echo component calculated by the adder 58 is received. The reception signal is subtracted from the signal, and the reception signal from which the echo component of the transmission signal included in the reception signal is removed is supplied to the reception unit 32 of the modem.

FIGS. 22D and 22E show superimposition of a randomized speech baseband signal on a data signal point in the adder 40. For simplicity, the CCITT V.V. An example is the case of 4 signal points in 2400 baud, 2 bits / symbol, 4800 bps mode according to T.29.

That is, from the data signal point generating section 38, the four signal points 188-1 to 188-4 shown in FIG.
, For example, the signal point 118-1 is output. At this time, at the same time, the randomized and amplitude-limited audio baseband signal shown in FIG. 22C is added to the adder 40 by the amplitude limiting unit 54, and the signal point 188-1 is output as shown in FIG. Is superimposed as a signal of a small circle 190-1 centered at the center. Of course, the other signal points 188-2 to 188
In the case of -4, the signals are similarly superimposed as signals of small circles 190-2 to 190-4.

Actually, in this operation description, 320
Since 0 baud, 3 + 1 bits / symbol, and 9600 bps mode are taken as an example, any of the 16 signal points shown in FIG. 7 is randomized to a small circle centered on the signal point at that time in FIG. And the amplitude-limited audio baseband signal is superimposed. 4. FIG. 23 is a configuration diagram of an embodiment showing details of the receiving unit 32 in the modem shown in FIG. In FIG. 23, the receiving unit 32 includes a processor unit 200 and an analog LSI unit 85 when viewed from the hardware configuration. The processor unit 200 is a microprocessor (MP
U) and a digital signal processor (DSP), and includes a demodulation / equalization unit 60, a soft decision unit 62, and a signal conversion unit 6.
4. The functions as a descrambler 66, a delay unit 70, an adder 72 as an analog baseband signal demodulator, a random inverse converter 74, a passband converter 76, and a signal quality detector 28 are realized.

The analog LSI section 85 comprises a D / A converter 224 and a low-pass filter 226.
The D / A converter 224 converts a digital signal such as voice or facsimile reproduced by the processor unit 200 into an analog signal. The low-pass filter 226 cuts high-frequency components of the analog reproduction signal, and outputs an analog passband signal 78 such as a voice or a facsimile from which a voice band component is extracted.

Next, the processor unit 20 of the transmission unit 32
The details of each unit provided in the unit 0 will be described.

First, the demodulator / equalizer 60 comprises a demodulator 202, a carrier generator 204, a roll-off filter 206, an automatic baseband equalizer 208, and an automatic carrier phase controller 210. In receiving section 30 shown in FIG. 5, received signal 192 from which the echo component has been removed is demodulated using a carrier signal in modulating section 202 of demodulating and equalizing section 60, and is converted from a passband signal to a baseband signal. .

Subsequently, the roll-off filter unit 206
An unnecessary sum component is removed from the sum component and the difference component generated by demodulation, the waveform is shaped, and the resultant is output to the baseband type automatic equalizer 208. Baseband type automatic equalizer 20
Numeral 8 denotes waveform equalization to compensate for transmission degradation, and subsequently, an automatic carrier phase control unit 210 removes frequency offset, phase jitter, and the like generated on the line, and demodulates a signal indicating an arbitrary data signal point. .

As another embodiment of the demodulation / equalization unit 60, as shown in FIG. 24, a received signal, which is a scalar signal, is vectorized by a Hilbert transform unit 228, and subsequently a waveform is generated by a passband type automatic equalizer 230. Performs equalization, and further uses the carrier signal from the carrier generation unit 234 to remove the offset for the carrier by using the carrier signal from the carrier generation unit 234 in the demodulation carrier automatic phase control unit 232 having both the automatic carrier phase control function and the demodulation function. May be used to obtain data signal points.

The demodulator 6 shown in FIGS. 23 and 24 differs from the demodulator 6 in that the former is in the order of demodulation and equalization, while the latter is in the order of equalization and demodulation.

Referring again to FIG. 23, demodulation / equalization section 60
The soft decision unit 62 provided following the above uses the redundant bits added by the trellis coding on the transmission side from the output data of the demodulation / equalization unit 60 to correct an error occurring on the line, and to set a correct data signal line. judge. That is, when trellis coding is used on the transmission side, the soft decision unit 62 determines the correct data signal point by executing the maximum likelihood estimation method based on the Viterbi algorithm.

The correct data signal point determined by soft decision section 62 is applied to code conversion section 64. In the case of 9600 bps mode, 3-bit data is restored.
In the case of the ps mode, 2-bit data is restored. Further, the restored data is descrambled by a descrambler 66, and the original main data is reproduced and output as received data 68.

The details of the soft decision section 62, code conversion section 64, and descrambler section 66 are described in CCITT 33, 3200 baud, 3 + 1 bits / symbol, 9600
FIG. 25 shows an example of the bps mode. In FIG. 25, a soft decision unit 62 corrects an error generated on a line using redundant bits added on the transmission side in accordance with a maximum likelihood estimation method using a well-known Viterbi algorithm corresponding to trellis coding on the transmission side. Then, a correct signal point is determined. The data signal points determined by the soft decision unit 62 are converted by the code conversion unit 244-1 and the parallel / serial conversion unit 246.
−1 is provided to the code conversion unit 64. The code conversion unit 244-1 performs a phase difference and a natural code / Gray code conversion on the determined data signal point to convert it into 3-bit parallel data. The parallel / serial converter 246-1 has a demodulation clock 242 of 3200 baud.
In synchronism with the above, 3-bit parallel data obtained from one data signal point is converted into serial data, descrambled by a descrambler 66, and the received data 68 is reproduced.

FIG. 26 shows details of the soft decision section 62, code conversion section 64 and descrambler section 66 of FIG.
V. 33 shows a mode of 2400 baud, 6 + 1 bits / symbol, and 14400 bps. The mode is basically the same as that of FIG.
The code converter 244-2 outputs 6-bit parallel data from one data signal point, and converts it into parallel data by a parallel / serial conversion unit 246-2 in synchronization with a demodulation clock 242-2 of 2400 baud. Finally, the received data 68 is descrambled by the descrambler 66.
Have gained.

Referring again to FIG. 23, demodulation / equalization section 66
The extraction of the analog baseband signal superimposed on the data signal point obtained from is performed by a delay unit 70 provided for the soft decision unit 62 and an addition unit 72 having a function as analog baseband extraction means.

As shown in FIG. 27, the delay section 70 has, for example, six tap delay lines 228-1 to 228-6, which function as delay elements per symbol, provided in series. The data signal point before the determination is delayed by the time required for the determination of the data signal point by the maximum likelihood estimation method of the unit 62.

The addition section 72 subtracts the correct data signal point determined by the soft decision section 62 from the data signal point before determination delayed by the delay section 70, and obtains a randomized analog base superimposed on the data signal point. Extract the band signal.

Random inverse converter 74 for random inverse conversion of the analog baseband signal extracted by adder 72
Is composed of a bit extraction unit 212, a phase inversion unit 214, and a multiplication unit 216. Details of the bit extraction unit 212 and the phase reverse conversion unit 214 are as shown in FIG. 28 in the case of the 9600 bps mode.

In FIG. 28, the data bit string which is the code conversion output from the code conversion unit 64 is arranged from right to left: C ₂ C ₁ C ₀ B ₂ B ₁ B ₀ A ₂ A ₁ A ₀ , Since it is 3 bits / symbol, it is possible to distinguish each symbol. Therefore, the bit extraction unit 212
The serial / parallel converter 212-1 provided in the
In synchronization with the 0 baud demodulation synchronization clock 242, the data bit string of the encoded conversion output is converted into parallel data “X ₂ X ₁ X ₀ ” every three bits. That is, a bit extraction output is generated for the input data bit string as shown in FIG.

The output “X ₂ X ₁ X ₀ ” of the serial / parallel conversion section 212-1 is input as an address of the phase reverse conversion section 214, and the phase reverse conversion section 214 calculates the phase change angle with respect to the input bit string shown in FIG. Because it is stored,
A random inversely converted phase signal can be obtained as a phase change angle corresponding to the reproduced data bit string.

FIG. 31 shows that the bit extraction unit 212 and the phase inverse conversion unit 214 of the random inverse conversion unit 74 are
00 baud, 6 + 1 bits / symbol, 14400 bps
The mode is described in detail below.

Here, in the case of the 9600 bps mode in FIG. 29, since the number of phases of the random inverse transform phase signal and the number of input bits match 3 bits, no particularly complicated processing is required. Is 14400 bps in FIG.
In the case of the mode, the number of input bits corresponding to one symbol is 2 bits, which is smaller than the number of phases of the random inverse conversion phase signal of 8. Therefore, the serial / parallel conversion section 212-2 provided in the bit extraction section 212 has a code The serial 2 bits of the conversion output are converted into parallel 3 bits.

That is, in the 14400 bps mode, the data bit string as the code conversion output from the code conversion section 64 is D ₁ D ₀ C ₁ C ₀ B ₁ B ₀ A ₁ A ₀ when arranged from the right, and one symbol is 2 They are distinguished by bits. Therefore, the serial / parallel conversion section 212-2 is configured to perform parallel conversion into three bits, which are the sum of the last bit of the previous symbol and the two bits of the next input data bit string, as shown in FIG.

The phase inversion section 214 has the same contents as in FIG.
The extracted bit string "X_Two X₁ X ₀Is an address
ROM which stores eight phase change angles.
Random inverse conversion phase corresponding to data from conversion section 64
Outputs any one of the hatch phase change angles as a signal
You.

Referring again to FIG. 23, the phase inversion section 2
The random inverse transformed phase signal output from the
At 16, the analog baseband signal in a randomized state from the adding unit 72 is multiplied, and the analog baseband signal is rotated by a phase change angle for restoration, and is converted into an original correlated analog baseband signal. .

The passband converter 76 provided following the random inverse converter 74 is composed of a modulator 220 and a carrier generator 222.

The modulator 220 includes a multiplier 236 and a real part extractor 238 as shown in detail in FIG. For this reason, the analog baseband signal from the random inverse converter 74 is added to the multiplier 236 and modulated with the 1850 Hz carrier signal from the carrier generator 222,
The real part extraction unit 238 extracts only the real component of the modulated signal.
And converts it into an analog bandpass signal.

FIG. 34 shows the band characteristic of the analog baseband signal input to the band-pass converter 76.
-1.55 kHz to +1.55 kHz centering on 0 kHz
It has a band of 3.1 kHz up to z and is band-limited by a low-pass filter characteristic 264 on the transmission side. The analog baseband signal shown in FIG. 34 is converted into a passband signal having a band of 0.3 to 3.4 kHz shown in FIG.

With respect to this analog passband signal,
After a low-pass filter characteristic 268 is set by a low-pass filter 226 provided in the analog LSI unit 85 at the last stage to remove unnecessary high-frequency components, the signal is output as a reproduced analog pass-band signal 78 to a telephone or a facsimile. 5. Operation of Receiver of First Invention The operation of the receiver 32 of the first embodiment shown in FIG.
A mode of 00 baud, 3 + 1 bits / symbol, and 9600 bps will be described as an example.

The signal received from the analog line 46 is shown in FIG.
After the echo component of the transmission signal is removed by the adder 58 of the receiver 30 as shown in FIG.
The demodulation unit 40 of the demodulation and equalization unit 60 first demodulates the signal into a baseband signal. The roll-off filter 206 performs band limitation and waveform shaping.
After the waveform equalization is performed by the carrier automatic phase correction unit 21
At 0, the phase component of the carrier and the jitter are corrected. For example, as shown in the phase space of FIG. 36A, a small circle 254 is placed at one of the plurality of data signal points 252-1 to 252-4.
A signal obtained by superimposing an analog baseband signal indicated by -1 to 254-4 is obtained.

In FIGS. 36A and 36B, for simplicity of description, the data signal points are represented by CCITT
V. Taking the example of 2400 baud, 2 bits / symbol at 29, 4 values at 4800 bps,
In the case of the 9600 bps mode for explaining the transmission operation, there are 16 signal points as shown in FIG.

The data signal points obtained by demodulation / equalization section 60 are applied to soft decision section 62, where the correct signal point is determined by the maximum likelihood estimation method using the Viterbi algorithm.
At 4, the data is encoded into 3-bit data corresponding to the data signal point, and finally descrambled by the descrambler 66, and the original main data is output as received data 68.

In the decision processing in the soft decision section 62, the analog baseband signal superimposed on the data signal point is seen only as a simple noise component which does not affect the decision accuracy, and has no effect on the restoration of the main data. Absent. On the other hand, the data signal point from demodulation / equalization section 60 is delayed by delay section 70 for the determination time in soft decision section 62, and then provided to addition section 72, where the data signal point before the determination and the correct data By subtracting the signal points,
An analog baseband signal in a randomized state as shown in FIG. 6C can be obtained, and the analog baseband signal is supplied to the multiplier 216 of the random inverse converter 74.

At the same time, the bit extraction section 212 of the random inverse conversion section 76 generates a parallel output every three bits of the data decoded by the code conversion section 64,
14, one of the eight phase change angles for restoration shown in FIG. 36D is obtained and output to the multiplication unit 215.

Here, the phase change angle shown in FIG. 31 stored in the phase reverse conversion section 214 of the reception section is obtained by inverting the polarity of the phase change angle of the phase conversion section 102 shown in FIG. 17 on the transmission side. . Accordingly, as shown in FIG. 36 (D), it is possible to obtain a phase change angle for restoration for rotating by the same rotation angle in the direction opposite to the randomized rotation direction on the transmission side.

Therefore, the analog baseband signal in the randomized state in the multiplication section 216 has the same rotation angle in the direction opposite to the rotation direction randomized by the phase change angle for restoration from the phase inversion section 214. And converted back to the correlated analog baseband signal 260 shown in FIG.

The analog baseband signal obtained from the random inverse converter 74 is applied to the modulator 2 of the passband converter 76.
At 20, the signal is modulated using the carrier signal from the carrier generator 222, and is returned to the pass band signal of the voice band of 0.3 to 3.4 kHz shown in FIG. Finally analog L
The digital signal returned to the passband signal by the D / A converter of the SI unit 85 is converted into an analog signal, and a high-frequency component is cut by a low-pass filter 226, so that an analog passband signal 78 such as voice or facsimile can be obtained. .

On the other hand, the analog baseband signal in the randomized state superimposed on the data signal point output from the adding section 72 appears as noise when viewed from the main data transmission. The band signal is detected by the signal quality detection unit 218 and transmitted to the partner station using a secondary channel or the like. When the other station receives the signal quality (SQD) from the signal quality detecting section 218 on the receiving side, the analog base superimposed on the main data signal point on the transmitting side as shown in the receiving section 30 in FIG. It is possible to control the optimum amplitude value of the band signal. 6. Another Embodiment of First Invention FIG. 37 is a block diagram showing an embodiment showing a second embodiment of the present invention. The second embodiment is different from the transmitting unit 3 of the first embodiment shown in FIG.
The configuration of the transmitting unit 30 is simplified except for the scrambler unit 36, the trellis coding function of the data signal point generating unit 38, the random transform unit 52, and the amplitude limiting unit 54 provided in 0.

With the simplification of the transmitting section 30, the descrambler section 66 and the random inverse transform section 74 provided in the first embodiment of FIG. 3 are also removed from the receiving section 32. Instead of the soft decision unit 62 corresponding to trellis coding, a data signal point is determined based on whether or not a distance on a phase plane between an input data signal point and a fixedly determined data signal point falls within a predetermined threshold. , A determination unit 62-1 for performing a so-called hard decision. The other configurations are the first
This is the same as the embodiment.

In the second embodiment shown in FIG. 37, the data signal point generating section 38-1 of the transmitting section 30 is, for example, shown in FIG.
As shown in FIG. 38A, one of the quaternary data signal points is generated based on the transmission data 34, and the phase plane obtained from the baseband converter 50 by the adder 40 is shown in FIG.
For example, a voice baseband signal having a distribution shown in FIG. 38 is superimposed, and a signal is generated by superimposing a voice baseband signal indicated by a dashed small circle on a simulated data signal point shown in FIG. The signal is modulated and transmitted to the analog line 46.

The demodulation unit 32 is a demodulation / equalization unit 60 shown in FIG.
A signal in which voice is superimposed on the data signal point shown in (C) is demodulated, and the data signal point is hard-decided by the determination unit 32 to determine the data signal point. The data is converted into data and output as received data 68.

Further, the data signal point after the determination is subtracted from the data signal point before the determination by the adding section 72, whereby
The audio baseband signal shown in (B) is taken out, and the passband conversion unit 76 extracts the analog passband signal 7 in the audio band.
8 and output.

FIG. 39 is a diagram showing the configuration of a third embodiment of the first invention. This third embodiment is characterized in that a scrambler section 36 is added to the transmitting side of FIG. In response to this, a descrambler 66 is provided in the receiver 32.

FIG. 40 shows a fourth embodiment of the first invention. This fourth embodiment is characterized in that an amplitude limiter 54 is provided in the transmitter 30 of FIG.

FIG. 41 shows a fifth embodiment of the first invention. This fifth embodiment is characterized in that a scrambler section 36 is further provided in the transmission section 30 of the fourth embodiment of FIG. A descrambler unit 66 is provided in the receiving unit 32 corresponding to this.

FIG. 42 shows a sixth embodiment of the first invention, in which the data signal point generating section 38 provided in the transmitting section 30 of the fifth embodiment of FIG. 41 has a trellis coding function. It is characterized by the following. In response to this, the receiving unit 32
Is a soft decision unit 62 that determines data signal points by the Viterbi algorithm.

Further, in the second to sixth embodiments of the first invention shown in FIGS. 37 to 42, the case where the analog line 46 is connected to the partner station by a 4-wire analog line 46 is taken as an example. Therefore, the transmitting unit 30 does not include the hybrid circuit 44.

Of course, when performing full-duplex transmission using the two-wire analog line 46, the hybrid circuit 44 may be provided as shown in the first embodiment of FIG. However,
In the sixth embodiment shown in FIG.
4 is the same as in the first embodiment,
Only the line analog line 46 is targeted.

In another embodiment including the amplitude limiter 54, the optimum amplitude limit value judging section 108 is provided as shown in the receiving section 30 in FIG.
The optimum amplitude limit value may be set based on QD.

Further, in addition to the above-described first to sixth embodiments, the following modifications are possible in the first invention.

First, the scrambling data of the main data signal is used for randomization and de-randomization of the analog baseband signal in the above embodiment, but the scrambling data is not used and provided on the transmitting side. The randomizer and the inverse randomizer provided on the receiving side may be synchronized to perform randomization and inverse randomization of the analog signal. In addition, although the setting of the data signal point has been described by using the eight-phase modulation, the present invention is not limited to this, and another method standardized by CCITT, for example, TCM, QAM, PSK, or the like can be used.

Further, in the case where both the transmitting unit and the receiving unit are provided to constitute a modem device, the transmitting processor unit and the receiving processor unit may be common. 7. FIG. 43 is a diagram showing an example in which an analog passband signal such as voice or facsimile is converted into an analog baseband signal, and then the analog baseband signal is separated into an analog signal and a digital signal. FIG. 6 is a configuration diagram of an embodiment showing a basic configuration of a second invention of the present invention.

In FIG. 43, transmitting section 30 includes baseband converting section 50, residual analog signal creating section 250, amplitude non-linear quantizing section 252, time division multiplexing circuit section 254, data signal point generating section 38, adding section 40, It is composed of a data modulation section 42. The baseband converter 50 converts an analog passband signal 48 such as voice or facsimile into a baseband signal.

The amplitude non-linear quantizer 252 non-linearly quantizes the amplitude of the analog baseband signal and outputs the digital base signal to the time division multiplexing circuit 254. The residual analog signal generation unit 250 generates a non-linear quantized residual analog signal, adds the generated signal to the addition unit 40, and superimposes the analog signal on the data signal point from the data signal point generation unit 38.

The time-division multiplexing circuit section 254 combines the arbitrary transmission data 34 and the digital signal obtained by nonlinearly quantizing the amplitude value from the amplitude value nonlinear quantization section 252 into transmission data, and sequentially outputs the data in parallel in a predetermined bit unit. The data signal point generation circuit 38 converts the data into corresponding data signal points.

The adder 40 superimposes the non-linear quantized residual analog signal from the residual analog signal generator 250 on the data signal point from the data signal point generator 38. Data modulator 4
2 modulates the data signal point on which the remaining analog signal is superimposed and sends the modulated signal to the analog line 46.

Here, the amplitude value nonlinear quantization section 252 and the residual analog signal creation section 250 provided in the transmission section 30 provide
The digital / analog signal separation means shown in FIG.

On the other hand, the receiving section 32 includes a demodulating / equalizing section 42, a determining section 60, a code converting section 64, a time division distribution circuit section 258, an amplitude non-linear inverse quantization section 260, a digital / analog signal synthesizing circuit 256, and a pass band. It is composed of a conversion unit 76.

The demodulation / equalization section 42 demodulates the modulated signal received from the analog line 46 and performs automatic equalization for compensating for transmission deterioration. The determination unit 60 determines a correct data signal point from the demodulated data signal points. The code conversion unit 64 converts the determined data signal point into a bit sequence and demodulates the original transmission data and the digital signal of the baseband signal.

The time division distribution circuit section 258 distributes the original received data 68 and the digital signal of the analog baseband signal from the demodulated data. Amplitude value nonlinear inverse quantization unit 26
0 restores the amplitude value of the original baseband signal by inverse quantization of the separated digital signal.

Further, the adder 72 functions as analog demodulation means, and reproduces the remaining analog signal superimposed on the data signal point by subtracting the data signal point after the determination from the data signal point before the determination. The digital / analog signal synthesizing circuit 256 synthesizes the original baseband signal based on the reproduced amplitude value and the remaining analog signal. Finally,
The signal is converted into an analog passband 78 by the passband converter 76 and output.

Here, a modulation frequency (baud rate) necessary for simultaneously multiplexing transmission of voice and data in the embodiment of FIG. 43 will be described.

First, for example, G3 to be transmitted according to the present invention
Transmission band required for facsimile signals of CCITT 29 and V.I. 33 (V.17).
That is, V. In the case of 29, the carrier frequency = 1700
Hz, modulation speed 2400 baud, roll-off rate 15%, band is 2760 Hz from 320 Hz to 3080 Hz.

In addition, V.I. 33 (V.17)
The carrier frequency is 1800 Hz, the modulation speed is 2400 baud, the roll-off rate is 15%, and the bandwidth is 420 Hz to 318.
2760 Hz up to 0 Hz.

Accordingly, V.I. 29 or V.I. 33 (V.1
7) In order to enable reliable transmission regardless of which facsimile signal arrives, the bandwidth should be 320 Hz to 3180.
Up to 2860 Hz, and the modulation speed is 2860 Hz.
You need more than a bo. In addition, since the main data signal has a minimum data transmission rate of 2400 bps, synchronization can be achieved at an integer fraction of 2400 Hz, and a frequency higher than 2860 baud in consideration of a facsimile signal. desirable.

Therefore, one-tenth of the frequency of 2400 Hz corresponding to the data transmission rate of 2400 bps is converted to 240 Hz.
If 12 data signal points are allocated per frame, 240 Hz × 12 = 2880 baud, and 2880 Hz is the optimum baud rate frequency.

Next, in the present invention, it is necessary to transmit data using a secondary channel for monitoring and controlling the network. In order to facilitate the commercialization of the device, the secondary channel is used for main modulation. 40 baud, which is an integer fraction of the speed of 2880 baud, for example, 1/72, is selected.

Next, the bandwidth required for the analog transmission of the present invention will be described.

First, the required band is 57.44 Hz for the secondary (roll-off rate 43.44 Hz).
6%) 56 Hz for band separation (14 Hz × 4) 2986.56 Hz for main data (roll-off rate 3.7%), the total band is 3100 Hz. Here, there is no problem because the audio band is 3100 Hz from 0.3 to 3.4 kHz.

Next, the amplitude value of the audio signal transmitted as a digital signal can be generally regarded as constant during 10 ms. Therefore, the maximum sound amplitude value is 10
What is necessary is that transmission can be performed at a speed of 0 Hz or more. In addition, since the maximum amplitude value is nonlinearly quantized, 3 bits / 100 Hz
A degree of information is sufficient.

Next, bit assignment in transmission of transmission data by data signal points will be described.

The data transmission speed of the main transmission data is 9
600bps, 4800bps or 2400bp
We plan three types of s. Of course, a higher data transmission rate may be used.

First, when the data transmission rate is 9600 bps, for example, as shown in FIG. 44, a total of 48 bits are allocated per frame, that is, per frame period (1/240 Hz). Of the 48 bits, 40 bits are allocated to main transmission data of 9600 bps, and the remaining 8 bits are allocated to the amplitude value of a voice or facsimile signal.

Further, assuming that one data signal point, that is, the number of allocated bits per symbol is 4 bits / symbol, data of one frame of 48 bits can be transmitted by time division of 12 symbols.

Next, at a data transmission rate of 4800 bps, if the frame frequency is 240 Hz, 36 bits are allocated per frame. Of the 36 bits, 20 bits are allocated to the main data bit of 4800 bps, and the remaining 16 bits are allocated to the maximum amplitude value of the voice or facsimile signal. Further, if the number of symbols for one frame is the same 12 symbols, the transmission is performed with 3 bits per symbol, that is, 3 bits / symbol.

Further, in the case of 2400 bps, if the frame frequency is also 240 Hz, 24 frames per frame
Bits are allocated, of which 10 are assigned to the main data.
14 bits are allocated to the bits and the maximum amplitude information.
If the number of symbols in one frame is the same, that is, 12 symbols, transmission is 2 bits / symbol.

Further, in the embodiment of the present invention, since the data signal points are converted after trellis coding, one redundant bit is added. At 9600 bps, 5 bits / symbol is obtained. The arrangement of the data signal points has 32 values as shown in FIG.

Also, 4800 bp is obtained by trellis coding.
For s, 4 bits / symbol and 16 data signal points
For 2400 bps, the data signal point has 8 values at 3 bits / symbol. 8. Details of the Second Invention Transmitter FIG. 46 is an embodiment configuration diagram showing a specific embodiment of the transmitter 32 shown in FIG. In the following description of the embodiment, a case where the data transmission speed is 9600 bps and the modulation speed is 2880 baud is taken as an example. The modulation method is not particularly limited, and may be any of the PSK method, QAM method, TCM method, or the like standardized by CCITT, and may be another unique modulation method.

Referring to FIG. 46, a processing system for an analog passband signal provided in transmitting section 30 will be described first. The analog passband signal 48 as an audio signal or a facsimile signal is input to an analog LSI unit 55, where unnecessary components are removed by a low-pass filter 90 and sampled by an A / D converter 92. A / D converter 92
Sampling frequency is 240H
Since 12 symbols are generated per frame in z, 240 Hz × 12 symbols = 2880 Hz, which is equal to the baud rate frequency.

The analog passband signal converted to a digital signal by analog LSI section 55 is converted to an analog baseband signal by baseband conversion section 50. The details of the baseband converter 50 are the same as those shown in the specific embodiment of the receiver in FIG.

The analog baseband signal converted by baseband conversion section 50 is applied to analog / digital signal generation section 250, where it is converted into a digital signal having a maximum amplitude value and a non-linear quantized residual analog signal.

Analog / Digital Signal Creation Circuit 25
Numeral 0 comprises a data storage RAM 272, a power calculation section 274, a maximum value detection circuit section 276, a non-linear quantization section 276, and an amplitude control circuit section 278.

FIG. 47 shows the details of the power calculation section 274 provided in the analog / digital signal generation circuit section 250.
The sampled baseband amplitude information for each symbol, that is, the input of the low-pass filter 98, is output to a delay circuit in which twelve tap delay lines 280-1 to 280-12 are serially connected, and the next stage multiplier 282 and AGC circuit 284 is used to calculate the power as the square of the amplitude value.

Here, the AGC circuit 284 is provided to normalize the amplitude value to a radius of 1.0. The power calculation result obtained by the multiplier 282 is removed as a real component R, and power data P1 to P12 for 12 symbols are stored in the data storage RAM 272 shown in FIG.

FIG. 48 shows details of the maximum value detection circuit 276 provided in the analog / digital signal generation circuit 250 of FIG.

The maximum value detection circuit section 276 includes power comparators 286-1 to 286-12 for 12 symbols.
The calculation power P1 of the symbol to the calculation power P12 of the twelfth symbol are sequentially compared two by two, and the higher power is output. For this reason, the final stage power comparator 28
From 6-12, a detection output of the maximum value of the power in 12 symbols is obtained.

FIG. 49 shows details of the non-linear quantization section 276 provided in the analog / digital signal generation circuit section 250 of FIG. 46, and comprises a floating point conversion section 288 and an upper bit extraction section 290. Floating point converter 288
Converts the fixed point data from the maximum value detection circuit 276 into floating point data.

In this embodiment, upper bit extraction section 290 extracts the upper 8 bits of the maximum detection value data because 8 bits of 48 bits constituting one frame are assigned to the maximum amplitude value. I do. Since this 8-bit data is floating point data, it is composed of an exponent part and a mantissa part. That is, the upper bit extraction unit 290 rounds up the maximum value detection data.

FIG. 50 shows details of the amplitude control circuit section 278 provided in the analog / digital signal generation circuit section 250 of FIG. 46. The tap delay line 29 for 12 symbols is provided.
A circuit in which 2-1 to 292-12 are connected in series, a divider 29
4 and a multiplier 296.

To the series circuit of tap delay lines 292-1 to 292-12, the amplitude information converted into the baseband signal from the low-pass filter 98 at the preceding stage is sequentially input.
In a state where the amplitude information for 12 symbols is arranged in the tap delay lines 292-1 to 292-12, the divider 294 uses the 8-bit nonlinear quantized data from the nonlinear quantizing unit shown in FIG. And outputs the reciprocal (1 / X).

The final stage tap delay line 29 is output from the multiplier 296.
The amplitude information of the first to twelfth symbols sequentially output from 2-12 is multiplied by a reciprocal (1 / X) to perform amplitude normalization of the analog amplitude information. The information obtained by multiplication of the reciprocal (1 / X) of the non-linear quantized data X is called a non-linear quantized residual analog signal. It falls within a small level that can only be seen as noise.

Referring again to FIG. 46, the 8-bit maximum amplitude value information generated by analog / digital signal generation circuit section 250 is output to data signal point generation section 38. The transmission data 34 converted from serial data into parallel data by the serial / parallel converter 254 is supplied to the data signal point generator 38 in a unit of 40 bits per frame period.

FIG. 51 shows details of the serial / parallel converter 262 provided in the serial / parallel converter of FIG. The transmission data 3 is stored in the serial / parallel converter 262.
4 is input as 9600 bps serial data,
A 9600 Hz clock is supplied as the read clock 264, and 2
A 40 Hz clock is provided.

The serial / parallel converter 262 uses the read clock 264 to read 40-bit serial transmission data 3 for each frame period determined by the frame synchronization clock 266.
4 is read and 40-bit parallel data 268 is output.

Referring again to FIG. 46, the data signal point generation section 38 includes a conversion section 264 having a scrambler and a Gray code / natural code conversion function, a data signal point generation circuit 266 having a trellis coding function, And a frame synchronization circuit 268.

The converter 264 includes a parallel / serial converter 466, a scrambler 468, a serial / parallel converter 470, and a gray code / natural code converter 472, as shown in detail in FIG.

The parallel / serial converter 466 has the structure shown in FIG.
40 from the serial / parallel converter 262 shown in FIG.
Parallel data 26 which is the main transmission data of bits
8 and the analog / digital signal generation circuit 2 of FIG.
A total of 48 bits including 8-bit parallel data indicating the maximum amplitude value, which is a digital signal from 50, are input in parallel.

A 240 Hz clock is given as the frame synchronization clock 266, and the read clock 264
A clock of 11.52 kHz is given.
Accordingly, the parallel / serial converter 466 converts 48-bit parallel data input in parallel at each frame period determined by the frame synchronization clock 266 into serial data, and outputs the serial data to the scrambler 468. The scrambler 468 is a known one according to the recommendation of CCITT.

A serial / parallel converter 470 converts the scrambled serial data again into 40-bit parallel data.

FIG. 53 shows the details of the data signal point generator 38 having the trellis coding function. The 4-bit selector 274, the conversion table 114, the taps 116, 11
8, a convolutional encoder 120 and a signal point generating ROM 112-3.

[0209] For the 4-bit selection unit 274, the 4 bits which have been converted to the scrambled and natural codes in the preceding stage are used.
8-bit data is input in parallel, and a clock of 240 Hz × 12 symbols = 2880 Hz is given as an operation clock. For each operation clock, the first to 48th bits are sequentially selected and output in 4-bit units. .

Of the four bits output from the four-bit selector 274, two bits are phase-differentiated by a phase difference circuit, and then coded by a convolutional coder 120. Bits are added and output as three bits. Therefore, the signal point generating ROM 112
For -3, 5 bits are input in parallel.

The signal point generation ROM 112-3 has the configuration shown in FIG.
The 32-valued data signal point indicated by 5 is stored by 5-bit address designation, and outputs a specific data signal point 122 corresponding to the input 5 bits. Further, the signal point generation ROM 112-3 stores the generated data signal point 112.
Is output as quadrant information 276 of the phase plane in which. This quadrant information is (1 + j0) in the first quadrant and (0 + j0) in the second quadrant.
j1), (−1 + j0) in the third quadrant, and (0−j1) in the fourth quadrant.

FIG. 54 shows the data signal point generator 38 of FIG.
2 shows details of the frame synchronization circuit 268 provided in FIG. This frame synchronizing circuit 268 has a 4-bit counter 280 and an RO
M284. The 4-bit counter 280 is 28
The 80 Hz modulation clock 282 is counted and reset every 240 Hz frame synchronization clock 266.

That is, as shown in the time chart of FIG. 55, 12 modulation clocks are counted by the 4-bit counter 280 every frame period determined by the frame synchronization clock, and the frame indicating the first to twelfth symbols is obtained. The phase numbers 1 to 12 are output.

The ROM 284 stores frame synchronization data indicating the phase angle corresponding to the phase number from the 4-bit counter 280 as shown in FIG. This frame synchronization data has a value that repeatedly changes in units of 12 phases. The frame synchronization data created by such a frame synchronization circuit 268 is multiplied by the data point signal from the data signal point generation circuit 266 to enable the receiving side to demodulate the frame synchronization signal.

The frame synchronization signal generated by the frame synchronization circuit 268 is supplied to the serial / parallel converter 262 and the code converter 26 provided in the receiver 30 shown in FIG.
4. The signal is supplied to each circuit section of the analog / digital signal creation circuit section 250 and performs processing according to frame synchronization.

Next, the phase random circuit section 52 provided in the receiving section 30 in FIG. 46 will be described. The phase random circuit section 52 is composed of a bit extraction circuit section 100 and a phase conversion circuit section 102.
And a multiplication unit 104.

FIG. 57 shows the bit extraction circuit 100 of FIG.
Of the 48-bit parallel data 27 converted into a natural code after being scrambled and output from the conversion section 264 of the data signal point generation section 38.
Enter 2. The bit extraction unit 100 operates with a frame synchronization clock 266 of 240 Hz, and extracts 48 symbols of parallel data of 12 symbols, that is, 36 bits in 3-bit units, and outputs the data.

As shown in FIG. 58, the extracted data from the bit extracting section 100 is a bit extracted output "X ₂ X ₁ X ₀ ".
From the first symbol to the twelfth symbol
The signals are sequentially supplied to the next-stage phase conversion circuit unit 102 up to the symbol and output a phase change angle. The phase conversion circuit unit 102 stores 8-valued vector data indicating the phase change angle shown in FIG. 17 in units of 45 °, and the bit extraction circuit unit 1
The vector data of the phase change angle corresponding to the values of the 3-bit inputs X ₂ , X ₁ , and X ₀ from 00 are read out and multiplied by the multiplication unit 104.
Output to

The multiplier 104 receives the non-linear quantized residual analog signal from the amplitude control circuit 278 of the analog / digital signal generation circuit 250, and multiplies this by the phase change angle to obtain the signal shown in FIG. Is given, and the distribution having the correlation as shown in FIG. 22 (A) is randomized as shown in FIG. 22 (C) to have no correlation.

FIG. 59 shows the data signal point generating circuit 2 of FIG.
The details of the adder 40, multiplier 270, and multiplier 272 provided subsequent to 66 will be described.

In FIG. 59, the data signal points output from data signal point generation circuit 266 having the trellis coding function are subjected to superimposition of analog information in adder 40.
Before being superimposed on the data signal point by the adder 40, the multiplier 270
Performs a predetermined phase rotation based on the determination output of the quadrant determination circuit 278.

That is, when analog information is simply superimposed on data signal points by the adder 40, when a carrier phase shift occurs on the line, the real component and the imaginary component are reproduced on the receiving side in reverse. It happens. To prevent this, in the present invention, the quadrant of the data signal point is determined by the quadrant determination circuit 278, and the vector to be superimposed as analog information is rotated by a predetermined angle phase according to the quadrant of the data signal point, and then superimposed. .

The quadrant judgment and judgment output by the quadrant judging circuit 278 are as shown in FIG. 60. The phase rotation in the first quadrant is 0 °, 90 ° in the second quadrant, and 180 ° in the third quadrant.
° and 270 ° in the fourth quadrant, so that the vector as analog information is phase-rotated to the vector position in the first quadrant by the multiplication of the decision output in the multiplier 270.

For this reason, the data signal point is the first on the phase plane.
Even in any of the quadrants to the fourth quadrant, the vector of the analog information to be superimposed on the data signal point exists in the quadrant of the phase plane of the same small circle as when the data signal point is located in the first quadrant. Even if a carrier phase shift occurs on the line, it is possible to reliably prevent the real component and the imaginary component from being reproduced in reverse. Data signal point generator 38
The details of the modulation section 42 provided after the above are the same as in the embodiment of FIG. Further, the analog LSI 45 is the same as the embodiment of FIG. 9. In FIG. 46, first, transmission data output from the host computer or the terminal device is input to the serial / parallel conversion unit 262, and the transmission data 3 of 9600 bps is output.
4 is parallel-converted at a frame synchronization frequency of 240 Hz to be 40-bit parallel data. The 40-bit parallel data from the serial / parallel converter 254 is provided to the converter 264 of the data signal point generator 38.

On the other hand, a voice signal from a telephone or an analog passband signal 48 having a passband of 0.3 to 3.4 kHz from a facsimile apparatus is an analog LSI.
After removing unnecessary components by the low-pass filter 90 of the unit 55, the baud rate frequency 28
Sampling is performed at an integral multiple of 80 Hz and converted from an analog signal to a digital signal to obtain a digital amplitude value.

Since the output of the A / D converter 92 is an analog passband signal, it is converted into an analog baseband signal by the baseband converter 50. That is, the signal is demodulated by the demodulation unit 94 using the carrier signal from the carrier generation unit 96 and is converted into a signal in a pass band. At this time, a signal having a band of 310 Hz to 3190 Hz is taken into the pass band, so that 3500 Hz / 2 = 1750 Hz is used as a carrier frequency used for demodulation. In demodulation to the pass band by the demodulation unit 94, since both the sum component and the difference component are output,
Unnecessary sum components are removed by the low-pass filter 98.

Next, the power of the analog baseband signal is calculated in the power calculation section 274 of the analog / digital signal generation circuit section 250, and the power obtained from the analog baseband signal for 12 symbols transmitted in one frame is stored in the data. It is stored in the RAM 272.

The maximum value is detected by the maximum value detection circuit 276 from the power of 12 symbols stored in the data storage RAM 272, and the nonlinear quantization indicating the 8-bit amplitude maximum value by the nonlinear quantization by the nonlinear quantization unit 276. Conversion section 26 provided in the data signal point generation section 264
4 For this reason, the conversion unit 264 receives 40-bit parallel transmission data and 8-bit maximum amplitude value data every frame period.

The 8-bit non-linear quantized data having the maximum amplitude value obtained by the non-linear quantizing section 276 is supplied to the amplitude control circuit section 278, and the reciprocal thereof is stored in the data storage RAM 27.
The non-linear quantization residual analog baseband signal for normalization by multiplying the power value for 12 symbols to be transmitted in one frame stored in 2 in each frame, that is, the amplitude information, is superimposed on the data signal point for 12 symbols. These are sequentially obtained and output to the phase random circuit unit 52.

The 40-bit parallel transmission data and the 8-bit non-linearly quantized maximum amplitude value data input to the conversion unit 264 of the data signal point generation unit 38 are randomized by a scrambler and the summation operation is facilitated. Is converted from gray code to natural code as
The parallel 48-bit data converted into the natural code is input to a data signal point generation circuit 266 having a trellis coding function to generate a data signal point.

In the data signal point generation circuit 266,
In this embodiment, since 12 symbols are sent in one frame, the data becomes 4 bits / symbol, and becomes 5 bits obtained by adding 1 bit of redundancy by trellis coding, and finally input to the ROM for signal point generation. FIG. 45
Is converted into a corresponding data signal point of any of the 32-valued data signal points and output.

On the other hand, in the phase random circuit section 52, the conversion section 264 provided in the data signal point generation section 38
, And the bit extraction circuit unit 100 inputs the 48-bit parallel output data as shown in FIG.
Twelve symbols are sequentially extracted to obtain 3-bit extracted data “X ₂ X ₁ X ₀ ” shown in FIG.
The ROM provided in 2 is accessed to obtain an 8-level phase change angle as shown in FIG.

The phase change angle from the phase conversion circuit unit 102 is multiplied by the non-linear quantization residual analog baseband signal from the analog / digital signal generation circuit unit 250 in the multiplication unit 104, and an automatic equalizer provided on the reception side Are made to be uncorrelated by randomization in order to allow convergence of the tap coefficients.

Subsequently, in the multiplier 270 provided in the data signal point generator 38, as shown in FIG. 62, the vector of the non-linear quantized residual analog signal according to the quadrant determination result of the data signal point is always used as the reference quadrant. After the phase is rotated so as to be in the first quadrant, the adder 40 superimposes the data on the data signal point.

Further, the data signal point on which the non-linear quantized residual analog signal is superimposed is multiplied by the multiplication section 272 with the frame synchronization data from the frame synchronization circuit 268 and output to the data modulation section 42.

The data modulation section 42 is a roll-off filter 8
After band-shaping the signal by 0, the modulator 82 modulates the signal using the carrier frequency as shown in FIG. 9 and transmits the information as one of the real component and the imaginary component. Is extracted and transmitted.

The modulated signal is finally converted to the analog LSI section 45
Is converted from a digital modulation signal to an analog modulation signal. Since the analog modulation signal contains harmonics accompanying the sampling frequency, the necessary out-of-band components are removed by the low-pass filter 88 and output to the analog line 46.

Note that the analog line 46 is a two-wire system, and the transmitting section shown in FIG. 46 is used as a modem, and FIG.
Is connected to a two-wire analog line 46 via a hybrid circuit 44 as shown in FIG. When the hybrid circuit 44 is provided, the receiver 30 is provided with an echo estimator 56 and an adder 58 for removing the echo as shown in FIG.
The received signal from which the echo component estimated from the transmitted signal is removed is supplied to the receiving unit 32. 10. Details of the second invention receiving unit FIG. 61 is an embodiment block diagram showing the details of the receiving unit 32 of the second invention shown in FIG. 43. In FIG. 61, a demodulation / equalization unit 60 includes a modulation unit 202, a carrier generation unit 204, a roll-off filter 206, a baseband type automatic equalizer 2
08, an automatic carrier phase control unit 210, a frame synchronization circuit 290, and a multiplication unit 292. The details of the demodulation / equalization unit 60 are as shown in the reception unit of the first invention in FIG.

The next soft decision unit 62 is capable of correcting an error occurring on a line by using one redundant bit added by trellis coding on the transmission side, and is generally well known. A correct data signal point is determined according to the maximum likelihood estimation method using the Viterbi algorithm.

The next code conversion section 64 inputs the determined data signal point as an address of a code conversion ROM.
The corresponding 4-bit data is output. The next code conversion unit 294 restores 48-bit data from the data signal points for 12 symbols constituting one frame, performs descrambling, further converts a natural code to a gray code, and outputs a 48-bit parallel output. The upper 40 bits from the middle are output to a parallel / serial converter 296, converted into parallel data, and output as received data 68. The code converter 294 outputs the lower 8 bits as the maximum amplitude value data to the amplitude inverse conversion circuit unit 256.

On the other hand, the adder 72 demodulates the non-linear quantized residual analog signal superimposed on the data signal point by subtracting the signal point data after the determination from the signal point data before the determination. In this case, since the soft decision in the soft decision circuit 62 takes time, the data signal point before the decision is supplied to the adder 72 via the delay 70 in order to compensate for this delay.

In the next multiplication section 298, the soft decision section 6
Based on the result of the quadrant determination of the phase plane where the data signal point after determination in 2 exists, the non-linear quantized residual analog signal is restored by applying a phase rotation in a direction opposite to that of the transmitting side.

That is, as shown in detail in FIG. 62, with respect to the data signal point after the determination from the soft decision circuit 62-1 provided in the soft decision section 62, the quadrant decision section 308 determines the phase plane where the data signal point exists. And outputs the judgment output to the multiplier 2
In addition to 98, multiply by the demodulated non-linear quantized residual analog signal to return the vector to the original quadrant.

The quadrant judging section 308 generates a judgment output for the quadrant judgment shown in FIG. That is, the data signal point is the first
In the case of the quadrant, the phase of the vector is not rotated. In the case of the second quadrant, the phase is rotated by 90 ° opposite to that of the transmitting side. In the case of the third quadrant, the phase is rotated by 180 ° opposite to that of the transmitting side. For example, it rotates 270 ° opposite to the transmitting side.

Referring again to FIG. 61, random inverse transform
The unit 74 includes a bit extraction unit 212 and a phase inverse conversion unit 214.
Based on the 48-bit reproduction data from the code conversion unit 64,
Therefore, the same bits as those on the transmitting side shown in FIGS.
After the extraction, a phase change angle opposite to that of the transmitting side is generated. I.e.
The 3-bit input bit string “X” shown in FIG._Two X₁ 
X ₀Vector data giving the phase change angle corresponding to
36D, and generates the phase reverse change angle shown in FIG.
The non-linear quantization residue demodulated by the multiplier 216 in FIG.
De-randomizing by multiplying by analog signal
To the original non-linear quantized residual analog signal
You.

The amplitude inverse conversion circuit section 256 includes a multiplication section 300 and a ROM 302. The ROM 302 performs nonlinear quantization, and stores 8-bit amplitude maximum value data, that is, the inversely quantized maximum amplitude value corresponding to the nonlinear quantized data as an address. Randomized inverse converter 7 converts the converted maximum amplitude value to random
4 is multiplied by the maximum amplitude information demodulated by inverse quantization to the non-linear quantized residual analog signal obtained through step 4, ie, the signal normalized by using the maximum amplitude value on the transmission side. The corresponding amplitude value and analog baseband signal are reproduced every time.

Next Interpolation Filter Unit 3
04 is provided with a roll-off filter 306, which performs band limiting and waveform shaping. The passband converter 76 includes a carrier generator 222 and a modulator 220, and converts an analog baseband signal into an analog passband signal. The details of the passband converter 76 are the same as those of the receiver 32 of the first invention shown in FIG. Further, an analog LSI unit 85 including a D / A converter 224 and a low-pass filter 226 is provided. The details of the analog LSI unit 85 are also shown in FIG.
This is the same as the receiving unit 32 of the first invention. 11. Next, the receiving operation of the receiving unit 32 in FIG. 61 will be described. The received signal 192 from the analog line is input to the modulation unit 202 of the demodulation and equalization unit 60, and is converted from a passband signal to a baseband signal using the carrier signal from the carrier generation unit 204. At this time, since both the sum component and the difference component occur, the necessary sum component is removed by the next roll-off filter 206 which also serves as waveform shaping.

Subsequently, waveform equalization is performed by the baseband type automatic equalizer 208, and the carrier automatic phase controller 21
At 0, the frequency offset and phase jitter generated on the line are removed, and the multiplication section 292 multiplies the frame synchronization signal from the frame synchronization circuit 290 to achieve frame synchronization, and then obtains a data signal point.

Subsequently, the soft decision unit 62 uses the redundant one bit added in accordance with the trellis coding with the transmitting side to determine a correct data signal point according to the maximum likelihood estimation method according to the Viterbi algorithm. Subsequently, the code conversion unit 64 converts the data signal points into 4-bit data, and the conversion unit 294 separates 40 bits as transmission data at the timing of a frame cycle in which 48 bits of 12-symbol bit data received in one frame are aligned. And the parallel / serial converter 29
In step 6, the data is converted into serial data and output as received data 68.

The 8-bit non-linear quantized data separated by the conversion unit 294, that is, the maximum amplitude data, is supplied to the ROM 302 of the amplitude inverse conversion circuit unit 256 and inversely quantized.

On the other hand, when the decision output is obtained from soft decision section 62, the data signal point after the decision by adder 72 is subtracted from the data signal point before the decision delayed by delay section 70 to obtain the data signal point. And demodulates the non-linear quantized residual analog signal superimposed on. Further, the multiplying unit 298 reversely rotates the vector rotated on the transmitting side based on the quadrant determination of the data signal point determined by the soft determining unit 62 so as to return to the original quadrant. Subsequently, the random inverse transform unit 74 performs a random inverse transform to convert the signal into a baseband signal.
6

Since the power of the demodulated non-linear quantized residual analog signal is normalized in the symbol unit on the transmitting side, the multiplication unit 300 of the amplitude inverse conversion circuit unit 256 uses a ROM.
By multiplying by the inversely quantized maximum amplitude value from 302, the amplitude value as power is inversely normalized, and an analog baseband signal is reproduced in symbol units.

The reproduced analog baseband signal is subjected to band limitation and waveform shaping by the roll-off filter 306 of the interpolation filter unit 304, and then converted to an analog passband signal of a passband band by the passband conversion unit 76. Is done. Further, the analog LSI unit 8
The analog passband signal is converted from a digital quadrant to an analog signal by the D / A converter 224 of No. 5, and the original analog passband signal 78 can be obtained by removing unnecessary band components by the low-pass filter 226. 12. Basic Embodiment of Third Invention for Transmitting Two Channels of Audio FIG. 64 is a configuration diagram of an embodiment showing a basic configuration of the third invention. In the third invention, audio 2 is transmitted using a single analog line. It is characterized in that channels are simultaneously multiplex-transmitted. Of course, simultaneous transmission of two channels of a facsimile signal or simultaneous transmission of two channels of a voice signal and a facsimile signal may be used. In FIG. 64, the transmission unit 30 and the reception unit 32 are connected via an analog line 46.

As in the case of the second invention shown in FIG. 43, transmitting section 30 converts time-division multiplexing circuit section 254, data signal point generating section 3
8, an adder 40 and a data modulator 42 are provided. This point is the same for the reception unit 32, and the demodulation and equalization unit 6
0, a determination unit 62, a code conversion unit 64, and a time division distribution circuit unit 258.

The present invention relates to such a signal system that converts transmission data into data signal points, modulates the data, and demodulates the data at the transmission / reception side, as in the first and second inventions. Is used only for transmitting a two-channel voice signal or a facsimile signal instead of multiplexing. Therefore, in the third invention, transmission data is not basically transmitted from the host computer or the terminal device.

Further, the transmitting section 30 is provided with analog / digital signal generating circuit sections 310 and 312 for two channels. Analog / digital signal creation circuit units 310 and 3
Reference numeral 12 denotes baseband converters 50-1 and 50-2, residual analog signal generators 250-1 and 250-2, amplitude non-linear inverse quantizers 252-1 and 250-2, and a phase linear quantizer 314-. 1, 314-2.

According to the third aspect of the present invention, the point that phase linear quantizers 314-1 and 314-2 are newly added is different from FIG.
Unlike the second aspect of the third aspect, the other aspects are the same. Also,
In order to superimpose the non-linear quantized residual analog signals generated for the two channels on the data signal points in the adder 40,
Remaining analog signal creation section 250 for one channel CH1
1 outputs the real component R of the non-linear quantized residual analog signal, and outputs the imaginary component I of the non-linear quantized residual analog signal from the remaining analog signal creation section 250-2 of the other channel CH2. After the addition, the data is added to the data signal point by the adding unit 40.

Further, by using the polarity of the non-linear quantization residual analog signal for one bit of data, the phase linear quantization
One bit of each of 14-1 and 314-2 is transmitted while being included in the signal superposition of the data signal point.

The receiving section 32 also has digital / analog reproducing circuit sections 320 and 322 corresponding to the two channels.
Is provided. Digital / analog reproduction circuit 32
0 and 322 are amplitude value nonlinear inverse quantization units 260-1 and 260-2.
60-2, phase linear inverse quantization section 324-1, 324-
2. Digital / analog signal synthesis circuit 256-1,
56-2, and passband conversion units 76-1 and 76-2 are provided.

Further, an adding section 72 is provided for demodulating a signal superimposed on the data signal point by subtracting the data signal point after the determination from the data signal point before the determination in the determination section 62. The demodulated signal from the adder 72 is separated by the distributor 318 into a real component of the channel CH1 and an imaginary component of the channel CH2, and is supplied to the digital / analog signal synthesizing circuits 256-1, 256-2, respectively.

According to the present invention, the baud rate frequency is set to 2880 Hz, and one frame is set to one frame in order to enable simultaneous transmission of two audio channels.
If two symbols are sent, the frame frequency is 240H
The maximum amplitude information, the maximum phase information, and the high-speed phase information are transmitted as digital information for each audio channel, and the high-speed amplitude information is transmitted as data signal point superimposition information. The bit allocation required for transmission in this case is as follows.

[0262]

[Table 1]

That is, it is necessary to transmit 72 bits in one frame as digital information in the simultaneous transmission of two channels of voice. Therefore, if one frame is composed of 12 symbols, time division multiplex transmission in which 6 bits are assigned to one symbol is obtained.
The data signal point on the phase plane has 64 values, and is obtained by adding 7 bits / redundant 1 bit by trellis coding.
Since it is a symbol, it has 128 values. 13. Details of Transmitter of Third Invention FIG. 65 is an embodiment block diagram showing details of the transmitter 30 of FIG. 64. In FIG. 65, an analog / digital signal generation circuit section 310 specifically showing channel CH1 side.
, The analog LSI 55, the data storage RAM 2
The power calculator 72, the power calculator 274, the maximum value detector 276, and the nonlinear quantizer 276 are basically the same as those of the second embodiment shown in FIG.

The data signal point generator 38 and the modulator 4
2, analog LSI section 45, and phase random circuit section 5
As for 2, the number of data bits transmitted in one frame is 7
Except for two bits, the configuration is the same as that of the receiving unit 32 in FIG.

FIG. 66 shows a frame configuration in two channels of audio shown in FIG. 65, and has a frame frequency of 240 Hz.
The first 36 bits of the frame period determined by
H1 and the latter 36 bits are assigned to the audio channel CH2.
Assigned to. Further, since one frame ends with time division of 12 symbols, data signal points are generated by extracting 72-bit data by 6 bits at a time. Actually, data signal points are generated at 6 + 1 bits / symbol by trellis coding.

In the transmitting section 30 shown in FIG. 65, newly provided ones are a phase difference circuit section 330 and a maximum value detection / quantization circuit section 332. Further, in the amplitude information creating section 278, the channel CH1 is a real component. Channel CH2
The difference is that the side outputs an imaginary component.

FIG. 67 shows details of the phase difference circuit section 330 of FIG. Here, since the human viewing characteristics are sensitive to low frequencies and insensitive to high frequencies, the phase displacement angle of the audio signal sampled at the baud rate frequency of 2880 Hz is determined based on the phase using the human auditory characteristics to the maximum. Perform quantization.

For this reason, the multiplication section 334 provided in the phase difference circuit section shown in FIG. 67 multiplies the analog baseband signal (in digital value notation) of each symbol by the carrier frequency of 1440 Hz to shift the frequency to the right, Minimize the amount of frequency transfer and maximize the amount of high frequency transfer. Subsequently, the AGC unit 336 creates a unit circle, and the multiplication unit 338 creates a phase difference value 345 for each symbol.

FIG. 68 shows details of the maximum value detection side of the maximum value detection / quantization circuit section 332 provided subsequent to the phase difference circuit section 330 of FIG. 65. The phase difference value 345 as vector data is shown in FIG. 342 for converting into an angle which is a scalar quantity, tap delay line 344-1 for 12 symbols
-344-12 series circuit section, tap delay line 344-1
And a maximum value detection unit 346 for inputting the phase difference angles θ1 to θ12 for 12 symbols obtained in 〜344-12 and detecting the maximum value θmax among them.

The maximum value detection unit cost 346 is the maximum value θma detected from the phase difference angles θ1 to θ12 for 12 symbols.
x is represented by 4 bits.

FIG. 69 shows details of the quantization section provided following the maximum value detection section of FIG. 68, and includes an upper bit extraction section 348 and a ROM 350. The upper bit extraction unit 348 calculates the maximum phase angle value θmax represented by 4 bits.
Are extracted and input to the ROM 350. R
The OM 350 stores the phase normalization information using the 4-bit input shown in FIG. 70 as an address, and normalizes the phase information for 12 symbols per frame.

This phase normalization information 352 is further provided to the last-stage circuit section on the quantization circuit side of the maximum value detection / quantization circuit section 332 shown in FIG. The final stage of the phase quantization circuit shown in FIG. 71 includes a multiplier 354 and a 3-bit information extraction unit 35.
6. The 3-bit information extraction unit 356 stores 3-bit data corresponding to the input phase information. The multiplication unit 354 multiplies the phase normalization information 352 by the phase maximum value θmax in the multiplication unit 354 to obtain phase information as a scalar quantity, and uses this as an address in the 3-bit information extraction unit 356 having the conversion contents shown in FIG. The information is converted into the corresponding 3-bit information, and high-speed quantization is performed for three bits.

The 3-bit data from the 3-bit information extraction unit 356 is sent as a digital signal for the upper 2 bits in a time-division manner at the data signal point, and for the least significant bit LSB as an analog signal, the polarity of the non-linear quantization residual analog signal. Control and send.

For this reason, since two bits of phase information are obtained for one symbol, the phase information of 12 symbols to be transmitted in one frame is 24 bits for one audio channel, and 4 bits indicating the maximum phase value θmax are added to this. With this addition, the phase information has a total of 28 bits. Further, by adding the maximum amplitude value of 8 bits obtained by the non-linear quantization, one voice channel has a total of 36 bits per frame, and therefore two voice channels have a total of 7 bits per frame.
It becomes 2 bits.

FIG. 73 shows details of the amplitude information creating section 278 shown in FIG. In FIG. 73, the amplitude information creating unit 2
78 is a multiplier 358, 362, 366, AGC unit 360
And a divider 364. The multiplication section 358 normalizes the analog baseband signal (in digital value notation) obtained for each symbol by multiplying the analog baseband signal by a level giving a radius of 1.0 in the AGC section 360.
Since the side is taken as an example, the real component is multiplied by the multiplier 362.
To enter.

On the other hand, the 8-bit non-linear quantized maximum amplitude value X obtained by the non-linear quantizing section 276 is calculated by the divider 36.
The reciprocal (1 / X) is obtained at 4 and the multiplier 362 multiplies the real component from the multiplier 358 to obtain a non-linear quantized residual analog signal to be superimposed on the data code point.

Further, the multiplier 366 multiplies by +1.0 when LSB = 1, based on the LSB bit output from the 3-bit information extraction unit 356 shown in FIG.
When LSB = 0, the polarity is inverted by multiplying by −1.0, 1 bit of phase information is represented by the polarity of the non-linear quantized residual analog signal of the real component, and is transmitted by being superimposed on the data signal point.

That is, the amplitude information generating circuit 278 shown in FIG.
In the above, the multiplier 366 normalizes the amplitude component vector information from the phase information by complex conjugate to obtain amplitude information including one bit of phase information.

Incidentally, the amplitude information generating circuit 2 provided in the digital signal generating circuit 328 on the channel CH2 side in FIG.
At 78, similar processing is performed on the imaginary component I from the multiplier 385 in FIG. FIG. 74 shows the details of the converter 264 provided in the data signal point generator 34 of FIG. 65. The parallel / serial converter 366, scrambler 368, serial / serial
Parallel converter 370 and gray code / natural code converters 372-1 to 372-12 for 12 symbols
It consists of.

The parallel / serial converter 366 receives parallel input of 8 bits of maximum amplitude information, 4 bits of maximum phase information, and 24 bits of phase information for 12 symbols for each of the audio channels CH1 and CH2. Using a read clock 264 of 266 and 17.28 kHz, the data is converted into parallel data in one frame cycle, scrambled by a scrambler 368, and simultaneously converted by the serial / parallel converter 370 into the original 72 data.
Return to bit parallel data.

Gray Code / Natural Code Converter 3
72-1 to 372-12 are serial / parallel converters 3
A 72-bit parallel output from 70 is input in 6-bit units, converted to a natural code and output. 14． Operation of Third Invention Transmitting Unit The transmission operation of two audio channels in FIG. 65 will be described.
First, an audio signal having a band of 0.3 kHz to 3.4 kHz is input to the analog / digital signal generation circuit units 326 and 328 as analog passband signals 48-1 and 48-2 of the channels CH1 and CH2. As shown on the channel CH1, the analog passband signal 48-1 is filtered by a low-pass filter 90 of the analog LSI unit 55 to remove unnecessary components, and then sampled by an A / D converter at a sampling frequency of a baud rate frequency of 2880 Hz to obtain a digital value. Converted to notation.

Subsequently, the data is converted into an analog baseband signal by the baseband conversion circuit section 50, and is stored in the data storage RAM2.
72. When the analog baseband signals for 12 symbols constituting one frame are stored in the data storage RAM 272, the power calculation unit 274, the maximum value detection unit 276, and the non-linear quantization unit detect the maximum power detected value among the 12 symbols. Quantized data is created and transmitted as an 8-bit digital signal.

At the same time, the 3-bit linearly quantized phase information based on the detection of the maximum value of the phase amount of the analog baseband signal for 12 symbols in the phase difference circuit 330 and the maximum value detection / quantization circuit 332 The 4-bit phase maximum value is obtained, and 6 bits including the phase maximum value of 4 bits and the phase information of 2 bits are output to the data signal point generating section for each symbol.

The 1-bit LSB of the phase information is supplied to the amplitude information creating section 278 together with the 8-bit data of the maximum amplitude value from the nonlinear quantizing section 276. Amplitude information creation unit 278
Is stored in the data storage RAM 272.
A power value for two symbols is read out and multiplied by a reciprocal of a maximum value obtained by nonlinear quantization to obtain a nonlinear quantized residual analog signal. Further, one bit LS of phase information is obtained.
The polarity is controlled by multiplying B by “1” and by “0” by minus, and supplies the real component to the combining unit 316.

At the same time, the analog / digital signal generation circuit section 328 of the channel CH2 also outputs a non-linear quantized residual analog signal obtained by inverting the polarity of 1-bit phase information as an imaginary component. The data is supplied to the circuit unit 52, is given a random rotation by giving an eight-level phase angle, and is sent to the data signal point generation unit 38.

[0286] Trellis coding in data signal point generating section 38, generation of data signal points, vector rotation according to quadrant determination of an analog signal superimposed on the generated data signal points, multiplication of frame synchronization signal, and modulation section 42 The modulation and the conversion to the analog signal in the analog LSI section 45 are the same as in the embodiment of the second invention in FIG. 15. Details of Third Invention Receiver FIG. 75 is a block diagram showing an embodiment showing details of the receiver 32 of the third invention shown in FIG. 64. In FIG. 75, demodulation / equalization section 60, soft decision section 62, code conversion section 64, conversion section 29
4, a delay unit 72 for demodulating a non-linear quantized residual analog signal
, An adder 72, a multiplier 298 for returning the vector rotation of the demodulated analog signal to the original quadrant, and a random inverse converter 7
4 is the same as the receiving unit 32 of the second invention shown in FIG. 61 except that the received data signal point is 6 bits / symbol and 72-bit data is reproduced in one frame.

In addition, analog baseband signal restoring circuits 374 and 376, passband converters 76-1 and 76-2, and analog LSI 85 correspond to two audio channels.
-1 and 85-2 are provided.

Analog baseband signal restoration circuit section 37
No. 4,376, the 8-bit amplitude maximum value data is nonlinearly inversely quantized as shown on the channel CH1 side, and simultaneously multiplied by the demodulated nonlinearly quantized residual analog signal to obtain a power value as amplitude information for each symbol. Is provided.

According to the third aspect of the present invention, the transmitting side transmits 24 bits (2 bits / symbol) of phase information as a digital signal, and transmits 1 bit of phase information as the polarity of an analog signal. Since 4 bits are sent as the maximum phase value, a selection / phase sum circuit section 380 and a multiplier 386 are provided for the phase information.

FIG. 74 shows the details of the selection / phase sum circuit section 380. The selection circuit 388 sequentially selects 2-bit phase information obtained each time each symbol is received in synchronization with the symbol reception and inputs the information to the ROM 32. At the same time, the polarity of the demodulated analog information 385 is determined by the code determination unit 390, and one bit LSB of the phase information is input to the ROM 392. The sign of the LSB by this sign determination unit 390 is + and L
SB = 1, the sign is-, and LSB = 0.

As shown in FIG. 78, ROM 392 receives 3-bit information and outputs corresponding phase information. On the other hand, 4 bits of the linearly quantized maximum phase information are input to the ROM 396, and are restored to the original maximum phase information as shown in FIG. The multiplier 394 is provided in the ROM 39 for each symbol.
2 is multiplied by the maximum phase information and inversely quantized.

Further, the inversely quantized phase information is supplied to the converter 3
At 98, the phase angle, which is a scalar quantity, is converted into vector information, and a phase sum is obtained using the next multiplier 400, amplitude normalizing section 402 and tap delay line 404.
In step 6, the phase sum information is shifted back to the baseband information at the carrier frequency of -1440 Hz, and the phase sum output 40
Yields 8.

FIG. 79 shows the amplitude inverse conversion circuit 378 shown in FIG.
The absolute value circuit 410 and the ROM 4 for non-linear inverse quantization of the 8-bit maximum amplitude value data 414
12 and a multiplier 416 are provided. That is, the polarity representing one bit of the phase information of the analog baseband signal as the restored analog information 385 is removed by the absolute value circuit 410, and at the same time, the maximum amplitude is obtained from the 8-bit maximum amplitude data quantized by the ROM 412. The value information is demodulated, and both are multiplied by a multiplier 416 to restore a power value as amplitude information. And the amplitude inverse conversion circuit 37
8 is multiplied by the phase sum output 408 obtained by the selection / phase sum circuit section 380 by the multiplier 386 to restore the original analog baseband signal.

Next, the operation of the receiving section 32 shown in FIG. 75 will be described.
The reproduction of the bit digital signal and the demodulation of the non-linear quantized residual analog signal formed by the real component and the imaginary component are the same as in the case of the second invention shown in FIG.

For the subsequent restoration of the original analog baseband signal based on the phase information and the amplitude information, the operation opposite to that of the transmitting side may be performed.

[0296]

As described above, according to the present invention, the following effects can be obtained.

First, an analog passband signal is converted to a baseband signal, and then superimposed on a data signal point of transmission data at a level considered to be noise, and transmitted. This allows simultaneous transmission of main transmission data and voice or facsimile signals. Can be achieved by using a single analog line, the line usage can be halved, and the equipment cost can be reduced because only one communication device is required.

Also, an analog passband signal such as voice or facsimile is separated into an analog component and a digital component. The digital component is converted into data signal points in time division with the main transmission data and sent. By transmitting the signal superimposed on the signal point, a higher quality analog passband signal can be transmitted, and the signal quality in voice or facsimile transmission can be greatly improved.

Further, by dividing the two audio channels into a digital signal and an analog signal and superimposing and transmitting them at the same time, it is possible to use a single analog line to use two audio lines or two facsimile lines. Efficiency can be doubled.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the first invention of the present application.

FIG. 2 is a diagram illustrating the principle of the second and third inventions of the present application.

FIG. 3 is a block diagram of an embodiment showing a first embodiment as a basic configuration of the first invention as a modem;

FIG. 4 is a characteristic diagram showing an error rate of an analog line.

FIG. 5 is a block diagram of an embodiment showing details of a transmission unit in FIG. 3;

FIG. 6 is a detailed explanatory diagram of the data signal generator of FIG. 5 used in the 9600 bps mode.

FIG. 7 is an explanatory diagram of signal points in a 9600 bps mode.

FIG. 8 is a detailed explanatory diagram of the data signal generator of FIG. 5 used in the 14400 bps mode.

FIG. 9 is a detailed explanatory diagram of a demodulator provided in the demodulator of FIG. 5;

FIG. 10 is a configuration diagram of another embodiment of the demodulation unit of FIG. 5;

FIG. 11 is a detailed explanatory diagram of a baseband conversion unit in FIG. 5;

FIG. 12 is a band explanatory diagram of a passband signal before baseband conversion.

FIG. 13 is a band explanatory diagram of a baseband signal after baseband conversion.

FIG. 14 is a configuration diagram of another embodiment of the baseband conversion unit in FIG. 5;

FIG. 15 is a detailed explanatory diagram of the random conversion unit of FIG. 5 used for the 9600 bps mode.

16 is a conversion characteristic diagram of the parallel conversion unit in FIG.

17 is a conversion characteristic diagram of a phase conversion angle by the phase conversion unit in FIG.

FIG. 18 is a detailed explanatory diagram of the random conversion unit in FIG. 5 used for the 4800 bps mode.

FIG. 19 is a conversion characteristic diagram of the parallel conversion unit in FIG. 18;

FIG. 20 is a detailed explanatory diagram of an optimum amplitude limit value determining unit in FIG. 5;

FIG. 21 is a detailed explanatory diagram of an amplitude limiting unit in FIG. 5;

FIG. 22 is an explanatory diagram showing, in a phase plane, a baseband signal, a phase change angle used for random conversion, a randomized baseband signal, a data signal point, and a superimposed signal in the transmission unit in FIG. 5;

FIG. 23 is a configuration diagram of an embodiment showing details of a receiving unit in FIG. 3;

FIG. 24 is a block diagram showing an embodiment showing another embodiment of the demodulation / equalization unit in FIG. 23;

FIG. 25 is a detailed explanatory diagram of the soft decision unit of FIG. 23 used in the 9600 bps mode.

FIG. 26 is a detailed explanatory diagram of the soft decision unit of FIG. 23 used in the 14400 bps mode.

FIG. 27 is a detailed explanatory diagram of a delay unit in FIG. 23;

FIG. 28 is a detailed explanatory diagram of the random inverse converter of FIG. 23 used in the 9600 bps mode;

FIG. 29 is a conversion characteristic diagram of the parallel conversion unit in FIG. 28;

FIG. 30 is a conversion characteristic diagram of the phase inverse converter of FIG. 28;

FIG. 31 is a detailed explanatory diagram of the random inverse transform unit in FIG. 23 used in the 14400 bps mode;

FIG. 32 is a conversion characteristic diagram of the parallel conversion unit in FIG. 31;

FIG. 33 is a detailed explanatory diagram of a modulation unit provided in the passband conversion unit in FIG. 23;

FIG. 34 is a band characteristic diagram of a baseband signal before passband conversion.

FIG. 35 is an explanatory diagram of a band of a passband signal after passband conversion.

36 shows a pre-determination data signal point, a post-determination data signal point, a baseband signal extracted from the data signal point, an inverse phase change angle used for random inverse transformation, and an inverse-transformed baseband signal in the receiving unit of FIG. Explanatory diagram showing the phase plane

FIG. 37 is a configuration diagram of an embodiment showing a second embodiment of the first invention.

FIG. 38 is an explanatory diagram showing the data signal points, the audio baseband signal, and the superimposed signal of FIG. 37 in a phase plane.

FIG. 39 is a configuration diagram showing a third embodiment of the first invention.

FIG. 40 is a configuration diagram showing a fourth embodiment of the first invention.

FIG. 41 is a configuration diagram showing a fifth embodiment of the first invention.

FIG. 42 is a configuration diagram showing a sixth embodiment of the first invention.

FIG. 43 is an embodiment configuration diagram showing a basic embodiment of the second invention.

FIG. 44 is an explanatory diagram of the frame configuration in FIG. 43.

FIG. 45 is an explanatory diagram of 32-value data signal points used in the embodiment of FIG. 43;

FIG. 46 is a block diagram of an embodiment showing details of the receiving unit of FIG. 43;

FIG. 47 is a detailed explanatory diagram of the power calculator of FIG. 46;

FIG. 48 is a detailed explanatory diagram of the maximum value detection circuit unit in FIG. 46;

FIG. 49 is a detailed explanatory diagram of the nonlinear quantization unit in FIG. 46;

FIG. 50 is a detailed explanatory diagram of the amplitude control circuit unit in FIG. 46;

FIG. 51 is a detailed explanatory diagram of the serial / parallel conversion unit in FIG. 46;

FIG. 52 is a detailed explanatory diagram of the time division conversion circuit provided in the data signal point generation circuit in FIG. 46;

FIG. 53 is a detailed explanatory diagram of a data signal point generation unit in FIG. 46;

FIG. 54 is a detailed explanatory diagram of the frame synchronization circuit unit in FIG. 46;

FIG. 55 is a signal waveform diagram of the frame synchronization circuit section of FIG. 46.

FIG. 56 is an explanatory diagram of storage contents of a ROM provided in FIG. 54;

FIG. 57 is a detailed explanatory diagram of the bit extraction circuit unit in FIG. 46;

FIG. 58 is an explanatory diagram showing conversion characteristics of the phase conversion circuit unit in FIG. 46;

FIG. 59 is a detailed explanatory diagram of an output stage of the data signal point generation circuit of FIG. 46;

60 is an explanatory diagram of the judgment output of the quadrant judging section in FIG. 59.

FIG. 61 is a configuration diagram of an embodiment showing details of the receiving unit in FIG. 43;

FIG. 62 is a detailed explanatory diagram of the soft decision unit in FIG. 61;

63 is an explanatory diagram of a judgment output of the quadrant judging section in FIG. 62.

FIG. 64 is a configuration diagram of an embodiment showing a basic embodiment of the third invention.

FIG. 65 is a block diagram of an embodiment showing details of a transmission unit in FIG. 64;

FIG. 66 is an explanatory diagram of a frame configuration in the third invention of FIG. 64;

FIG. 67 is a detailed explanatory diagram of the phase difference circuit unit in FIG. 65;

FIG. 68 is a detailed explanatory diagram of the maximum value detection side of the maximum value detection / quantization circuit unit in FIG. 65;

FIG. 69 is a detailed explanatory diagram on the quantization side of the maximum value detection / quantization circuit unit in FIG. 65;

70 is an explanatory diagram of a conversion function of the ROM of FIG. 69;

FIG. 71 is a detailed explanatory diagram on the quantization side of the maximum value detection / quantization circuit unit following FIG. 69;

FIG. 72 is an explanatory diagram of a conversion function of the bit information extraction unit in FIG. 71;

FIG. 73 is a detailed explanatory diagram of the amplitude information creating unit in FIG. 65;

74 is a detailed explanatory diagram of a time-division conversion circuit provided in the data signal point generator of FIG. 65;

FIG. 75 is a block diagram of an embodiment showing details of the receiving unit of FIG. 64;

76 is a detailed explanatory diagram of the selection / phase sum circuit section of FIG. 75;

FIG. 77 is an explanatory view showing a conversion function of the 4-bit input ROM of FIG. 76;

FIG. 78 is an explanatory view showing a conversion function of the 3-bit input ROM of FIG. 76;

FIG. 79 is an explanatory diagram showing details of the amplitude inverse conversion circuit unit in FIG. 75;

FIG. 80 is an explanatory diagram of a transmission form using a conventional digital backbone line.

FIG. 81 is an explanatory diagram of a transmission form using a conventional analog line.

[Explanation of symbols]

Reference Signs List 30: transmitting unit 32: receiving unit 34: transmission data 36: scrambler unit (SCR) 38: data signal point generating unit 40: adding unit 42: data modulating unit 44: hybrid circuit 45, 55, 85: analog LSI unit 46 : Analog line (2-wire or 4-wire) 48: Analog passband signal 50: Baseband converter 52: Random converter 54: Amplitude limiter 56: Echo estimator 58: Echo remover (adder) 60: Demodulation / Equalization unit 62: Soft decision unit 62-1: Decision unit (hard decision) 64: Code conversion unit 66: Descrambler unit (DSCR) 68: Received data 70: Delay unit 72: Addition unit (for baseband signal demodulation) 74: random inverse converter 75, 200: processor unit 76: passband converter 78: analog passband signal 80, 206: b 82, 220: demodulator 84, 96, 134, 204, 222, 234: carrier generator 86, 224: D / A converter 88, 90, 98, 226: low-pass filter (LP)
F) 92: A / D converter 94, 202: demodulation unit (DEM) 100: bit extraction unit 100-1, 100-2: parallel conversion unit 102: phase conversion unit 104, 124, 132, 136, 138, 172, 172 2
36: Multiplication unit 106: Signal quality signal (SQD) 108: Optimal amplitude limit value determination unit 110-1, 110-2: Conversion unit 112-1, 112-2: ROM for signal point generation 114: Conversion table 116, 118 : Tap 128, 238: Real part extraction unit 130: Hilbert filter 148: ROM 154: Automatic gain control unit (AGC) 156, 164, 160, 168: Adder 158, 162, 166, 170: Limiter 202: Demodulation unit 208 : Baseband type automatic equalizer (EQL) 210: automatic carrier phase control unit (CAPC) 212: bit extraction units 212-1, 212-2: parallel conversion unit 214: phase inverse conversion unit 228: Hilbert conversion unit 230: Automatic passband equalizer 232: Automatic demodulation carrier frequency control unit 244-1, 244- 2: code converters 246-1, 246-2: parallel / serial converters 250, 250-1, 250-2: residual analog signal generators 252, 252-1, 252-2: amplitude non-linear quantizers 254: Time division multiplex circuit section 258: Time division distribution circuit section 256, 256-1, 256-2: Digital / analog signal synthesis circuit (amplitude inverse conversion circuit section) 260, 262-1, 262-2: Amplitude nonlinear inverse quantization section 262: Serial / Parallel conversion unit 264: Time division multiplex conversion unit 266: Data signal point generation circuit unit 268: Frame synchronization circuit unit 272: Data storage RAM 274: Power calculation unit 275: Maximum value detection circuit unit 276: Non-linear quantization unit 278: Amplitude control circuit units 310, 312: analog / digital signal creation circuit units 314, 314-1, 314-2: phase linear quantization unit 3 0, 322: digital / analog signal reproduction circuit 330: phase difference circuit 332: maximum value detection / quantization circuit 374, 376: analog baseband signal restoration circuit 378: amplitude inverse conversion circuit 380: selection / phase Integration circuit section

──────────────────────────────────────────────────続 き Continuation of the front page (56) References Special Table 60-501087 (JP, A) European Patent Application Publication 506400 (EP, A2) Hideki Ishio, 3 others, “Polyphase multilevel carrier wave Digital communication On the other hand, “Communication method study group”, IEICE, January 29, 1975 (1975-01), p. 57-64 Tricia Hill and Kamilo Feher, "A Performance Study of NLA 64-State QAM", IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-31, NO. 6, JUNE 1983, p. 821-826 (58) Field surveyed (Int.Cl. ⁷ , DB name) H04M 11/00-11/10 H04L 27/00-27/30 H04B 3/23 H04L 5/02

Claims (10)

(57) [Claims] 1. A multimedia multiplex receiving method for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is assigned and reproducing the first signal and the second signal. Reproducing a data signal as the first signal, and subtracting a data signal point determined from the transmission signal from a data signal before determination delayed by a predetermined time required for determination to reproduce the second signal ; The second signal is an analog base
An analog passband signal converted from a band signal
Multimedia multiplex reception method characterized in that there. 2. A multimedia multiplex receiving method for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is assigned and reproducing the first signal and the second signal. And a data signal and an analog passband signal as the first signal.
A signal obtained by synthesizing a part of the signal of the signal is reproduced, and the data signal point determined from the transmission signal is necessary for the determination.
From the data signal point before judgment delayed by
To reproduce the second signal, the second signal being the analog signal
Multimedia multiplex receiving method which is a remaining signal of Gupasubando signal. 3. A multimedia multiplex receiving method for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is allocated and reproducing the first signal and the second signal. And a first analog passband signal and a second analog passband signal as the first signal.
A signal that combines a part of the analog passband signal
The data signal point determined from the transmitted signal is subtracted from the data signal before the determination delayed by a predetermined time required for the determination, and the remaining signal of the second analog passband signal is reproduced.
Multimedia multiplex receiving method which is characterized in that raw. 4. The multimedia multiplex receiving method according to claim 1 , wherein a data signal point is determined from said transmission signal, and said data signal point is not determined by said determination step. Delaying by a predetermined time required for the determination, and subtracting the data signal point determined in the determination step from the data signal point before determination delayed in the delay step
A multimedia multiplex receiving method, comprising: an adding step of extracting a signal. 5. The multimedia multiplex receiving method according to claim 4 , wherein said determining step determines a likely data signal point according to a Viterbi decoding procedure. 6. A multimedia multiplex receiving apparatus for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is assigned and reproducing the first signal and the second signal. And a first reproducing means for reproducing a data signal as the first signal.
And subtracting the data signal point determined from the transmission signal from the data signal point before the determination delayed by a predetermined time required for the determination to regenerate the analog passband signal as the second signal.
A multimedia multiplex receiving apparatus provided with a second reproducing means for generating a multimedia signal. 7. A multimedia multiplex receiving apparatus for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is assigned and reproducing the first signal and the second signal. And a data signal and an analog passband signal as the first signal.
First reproducing means for reproducing a signal obtained by synthesizing a partial signal of a signal
When the determination data signal points from the transmission signal, as the second signal is subtracted from the pre-determination of the data signal points only delayed a predetermined time required for the determination of the analog passband signal remaining
Multimedia multiplex receiving apparatus, comprising a second reproducing means for reproducing a signal . 8. A multimedia multiplex receiving apparatus for receiving a transmission signal in which a second signal is superimposed on a data signal point in a two-dimensional coordinate space to which a first signal is allocated and reproducing the first signal and the second signal. And a first analog passband signal and a second analog signal as the first signal.
Regenerate the signal obtained by synthesizing a part of the analog passband signal.
A first reproducing means for generating the signal and a data signal point determined from the transmission signal subtracted from a data signal point before the determination delayed by a predetermined time required for the determination to obtain a second analog passband signal as the second signal.
2. A multimedia multiplex receiving apparatus, comprising a second reproducing means for reproducing the remaining signal . 9. The multimedia multiplex receiving apparatus according to claim 6 , wherein said second reproducing means determines a data signal point from said transmission signal.
2); a delay means (70) for delaying the data signal point before the determination by the determination means (62) by a predetermined time necessary for the determination; and a data signal point before the determination delayed by the delay means (72). A multimedia multiplex receiving apparatus comprising: an adding means (72) for extracting the second signal by subtracting the data signal point determined by the determining means (62). 10. A multimedia multiplex receiving apparatus according to claim 9 , wherein said judging means includes soft judging means for judging a likely data signal point according to a Viterbi decoding procedure. Multimedia multiplex receiver.