JP3063660B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor memory using a capacitor using a ferroelectric or a high dielectric and a method of manufacturing the same.

[0002]

BACKGROUND OF THE INVENTION Semiconductor and the ferroelectric, for example, lead zirconate titanate _{(Pb (Zr x Ti 1-} x) O 3, below, PZT
A so-called ferroelectric memory using a combination of capacitances (hereinafter abbreviated as “1”) and “0” using the residual polarization of the ferroelectric material.
Is stored. Since this information is retained even when the power is turned off, it is known to operate as a nonvolatile memory. FIG. 2 shows a circuit diagram of the unit cell as the basic configuration. In this case, the unit cell has a configuration in which one cell transistor (usually an n-channel MOSFET) Tr and a ferroelectric capacitor Cf are combined. Bit lines (hereinafter abbreviated as BL), word lines (hereinafter abbreviated as WL),
By controlling the voltage applied to a plate line (hereinafter abbreviated as PL), the Tr is turned on and off, and the polarity of the voltage applied to Cf is changed to determine the sign of the remanent polarization of Cf.

[0003] Alternatively, the capacitor is not a capacitor using a ferroelectric, but has a high dielectric constant, for example, SrTiO ₃ , (Ba).
_In the case of a capacity using _1-x Sr _x ) TiO ₃ , non-volatile operation is not possible, but operation as DRAM is possible.
In this case, since the dielectric constant of the material is large, a large capacitance can be obtained with the same capacitance area as that of a normal DRAM using a capacitance using a silicon oxide film, or a large capacitance can be obtained without reducing the dielectric film thickness. Is obtained. In other words, a DRAM having the above advantages can be obtained by using different dielectric materials with exactly the same structure.

A unit cell of a ferroelectric memory is composed of a cell transistor Tr and a ferroelectric capacitor Cf. A device using the circuit of FIG. 2 is, for example, the 1996 International Triple Solid State Circuits (IEEE).
d-State Circuits Technical Paper (Conference Digest of T)
technical Papers), page 368. FIG. 3A is a plan view of the device in this case, and FIG. 3B is a cross-sectional view taken along the line AA ′ in FIG. In the figure, 1 is a word line (the gate of a cell transistor is made of polysilicon), 2 is a plate line or a ferroelectric capacitor lower electrode (a laminated structure of Pt / Ti), and 3 is a bit line (A
1, a laminated structure of TiN, Ti, etc., hereinafter abbreviated as Al wiring), 4 is a ferroelectric upper electrode (Pt), 5 is a local wiring (Al wiring as well as a bit line), 6 is a silicon n + layer,
7 is a contact pad (WSi ₂ ), 8 is Pb (Zr
_0.53 Ti _0.47 ) O ₃ , 9 is an interlayer insulating film (SiO ₂ ), 1
0 is a silicon p-type layer. In this configuration, WL in FIG. 2 is made of polysilicon, PL is made of Pt, and BL is made of Al wiring. Further, in the configuration shown in FIG. 3, a contact from the ferroelectric capacitor upper electrode 4 to the silicon n + layer 6 is made via a contact pad 7.
This is to reduce the depth of the contact hole and eliminate the contact failure. As described above, this structure can be applied to a DRAM using a high dielectric substance instead of a ferroelectric substance.

[0005] A sectional view of a manufacturing process for realizing this structure (FIG. 3)
(A-A 'direction) are shown in FIGS. The ferroelectric lower electrode 2 and the ferroelectric 8 are formed on the entire surface of the underlying interlayer film 11 (FIG. 4A). Here, the underlying interlayer film 11 is sufficiently planarized by a method such as chemical mechanical polishing. This is because the film quality of the upper ferroelectric does not improve unless the surface is planarized. Next, the capacitor portion is processed (FIG. 4B), and the upper electrode 4 is formed and processed on the ferroelectric (FIG. 4C). On this, the capacitor interlayer 1
2 is formed (FIG. 4D). Therefore, the interlayer insulating film 9 in FIG. 3B has a laminated structure of the base interlayer film 11 and the capacitor interlayer film 12. A contact hole is formed on the upper electrode and the contact pad by a method such as reactive ion sputtering (FIG. 4E), and an Al local wiring 5 is formed (FIG. 4).
(F)), the contact pad 7 and the ferroelectric upper electrode 4 are electrically connected.

[0006]

Problems of the present manufacturing method will be described below.

In FIG. 4E, a contact hole is formed on the contact pad and on the upper electrode. In particular, the depth of the hole on the contact pad increases. This is because the oxide film to be etched on the contact pad has a laminated structure of the base interlayer film 11 and the capacitor interlayer film 12. For example, when the thickness of the underlying interlayer film 11 is 500 nm as shown in FIG. 4 and the upper interlayer film 12 is also 500 nm, the contact depth on the upper electrode is only 500 nm corresponding to the upper interlayer film thickness. However, the contact depth on the contact pad is 1 μm, which is the sum of the two. For example,
When the contact diameter is 1 μm φ, the aspect ratio is 0.5 on the upper electrode and 1.0 on the contact pad. As a result, when the local wiring is formed of Al as shown in FIG.

For example, it is difficult to conduct a contact by a commonly used method such as sputtering. Therefore, in forming a wiring, a method such as CVD having a better embedding property is required. In particular, when a memory using a ferroelectric or high dielectric capacitor is manufactured, CV
In a reactive gas atmosphere due to D, deterioration of the ferroelectric or high dielectric capacity becomes a problem. For example, in a ferroelectric capacitor, the remanent polarization value decreases and a phenomenon of an increase in leak current occurs. In the case of a high dielectric capacitor, the dielectric constant is deteriorated. Also, in the manufacturing process, when etching is performed simultaneously on the upper electrode and the contact pad during the contact etching, the difference in depth between the two significantly impairs the controllability and causes the yield to decrease. . Therefore, it is an important issue to make the contact depth shallow and equal between the two, and to obtain contact conduction without deteriorating the ferroelectric or high dielectric capacity.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the depth of a contact hole in a semiconductor device using a ferroelectric or ferroelectric capacitor, thereby facilitating contact conduction and at the same time deteriorating its capacitance characteristics. It is an object of the present invention to provide a structure of a semiconductor device free from defects and a method of manufacturing the same.

[0010]

In order to solve the above problems, in a semiconductor device according to the present invention, an integrated circuit formed on a substrate and a first interlayer having a contact pad provided on the integrated circuit are provided. An insulating film; a capacitor portion including a capacitor lower electrode, a dielectric layer, and a capacitor upper electrode provided on the first interlayer insulating film and at a different position on the plane from the contact pad; A semiconductor device comprising: a local wiring provided through a second interlayer insulating film to electrically connect to an integrated circuit;
Wherein the interface between the first interlayer insulating film and the second interlayer insulating film is located below the interface between the first interlayer insulating film and the capacitor lower electrode. Alternatively, in a similar semiconductor device, the thickness of the second interlayer insulating film is substantially equal at least on the capacitor portion and on the contact pad portion. The dielectric layers used in such a semiconductor device _{Pb (Zr 1-x Ti x} ) O 3, Sr
Bi ₂ Ta ₂ O ₉ , SrTiO ₃ , (Ba _1-x Sr _x )
TiO _{3 and the} like. The first and second interlayer insulating films include at least a silicon oxide film, a phosphorus-doped silicon oxide film, a boron-doped silicon oxide film, a phosphorus and boron-doped oxide film, and the like.

In the semiconductor device having such a structure, a first step of forming at least a capacitor lower electrode and a dielectric film on at least a first interlayer insulating film having a contact pad; And a second step of processing the first interlayer insulating film at the same time as processing the dielectric film until the contact pad is exposed.

In the present invention, the etching time is sufficiently lengthened during the capacitance processing, the underlying interlayer film under the capacitor is also etched, and the etching is performed until the underlying interlayer film on the contact pad is removed. Thereafter, formation of an interlayer film on the capacitor, contact etching, and formation of an Al wiring can facilitate conduction on the contact pad.

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a semiconductor device according to the present invention.
(F) is a process sectional view of the manufacturing method shown in FIGS.
(F). In the figure, after a lower electrode 2 and a ferroelectric 8 are formed on the entire surface of a base interlayer film 11 (FIG. 1A),
This is processed (FIG. 1B). At this time, instead of stopping at the point where the plate line 2 is cut,
Further, the underlying interlayer film 11 thereunder is also etched in the same step. However, at this time, the kind of etching gas (in the case of reactive ion etching) or the etching power may be changed on the way. As a result, there is no underlying oxide film on the contact pad. Further, an upper electrode 4 is formed on the ferroelectric and processed (FIG. 1C), and an upper interlayer film 12 is formed thereon (FIG. 1D). Next, a contact hole is formed on the upper electrode and the contact pad by a method such as reactive ion sputtering (FIG. 1E). At this time, the depth of the contact hole is equal on the upper electrode and the contact pad. Next, an Al local wiring 5 is formed (FIG. 1).
(F)). As a result, as shown in FIG. 1F, the interface between the underlying interlayer film 11 and the lower electrode 2 becomes higher than the interface between the underlying interlayer film 11 and the capacitor upper interlayer film 12 around the contact pad. Upper contact hole and contact pad 7
The depth of the upper contact hole can be made equal and shallow.

In the above example, the lower electrode is a plate line, and since the pattern is different from that of the upper electrode, the upper electrode is formed after processing the dielectric layer. However, the upper electrode is the same as the lower electrode and the dielectric. Needless to say, in the case of a structure that can be manufactured by the above pattern, the lower electrode, the dielectric, and the upper electrode can be processed collectively after lamination.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Example 1) In FIG. 1A, wirings such as transistors and word lines are formed, and a base interlayer film 11 is formed.
A ferroelectric lower electrode 2 and a ferroelectric 8 (PZT), which will later become plate lines, are successively formed on the substrate on which is formed. The underlying interlayer film is, for example, BPSG (boron-doped phosphorus glass), which is, for example, CMP (chemical mechanical polishing).
The thickness is about 500 nm on the contact pad.

Next, the PZT and the lower electrode are processed into a predetermined shape by dry etching (FIG. 1B). This is realized by, for example, using ion milling using Ar and using a photoresist as a mask. At this time, since the ion milling is an etching having no reactivity, if the etching time is further increased from the point where the lower electrode is cut, the underlying interlayer film 11 is similarly etched. In addition, R. I. In the case of processing using E (reactive ion etching), if the etching is advanced until a contact pad made of WSi ₂ comes out, W is detected by a commonly used means such as emission spectroscopy. Can be detected. Further, during this etching, it is possible to easily control the etching by switching the gas type, switching the power, or switching the etching apparatus during the etching.

Next, after the upper electrode is formed and processed, an upper interlayer film 12 is formed on the entire surface (FIG. 1C).
(D)). As the interlayer film on the capacitor, a film that can be formed without adversely affecting the ferroelectric capacitance characteristics, for example, O ₃ (ozone)
Then, a silicon oxide film is formed to a thickness of about 500 nm by a CVD method using TEOS (tetraethoxysilane). As a result, only the upper interlayer film having a thickness of 500 nm exists on the upper electrode and the contact pad. Therefore, next, at the time of contact etching for forming a contact hole on the upper electrode and the contact pad (FIG. 1 (e)), the depth of both becomes equal to 500 nm, and furthermore, the depth of the contact pad is higher than that of FIG. And shallow. Therefore, since etching is performed at the same depth in the same chip, the control of the etching becomes easier. Since the contact hole becomes shallow, the next time an Al wiring is formed in FIG.
Even if a method such as CVD which has a particularly good embedding property is not used, the contact can be sufficiently conducted by a simpler method such as sputtering. Therefore, the ferroelectric characteristics do not deteriorate. Usually, in order to bury the contact, it is necessary to form a sufficient amount of metal film, which requires a long film formation time. However, if the contact is shallow, the amount is small. Therefore, productivity is also improved.

[0020]

As described in the above embodiments, according to the semiconductor device of the present invention and the method of manufacturing the same, the contact hole can be made shallow and equal on the contact pad and on the capacitor upper electrode. Control becomes easy.
In addition, since the contact hole is shallow, C
Since the contact failure can be reduced without using a method such as VD, the deterioration of the capacitance characteristics does not occur. As a result, the process of forming the wiring in the contact hole is simplified, and the productivity is improved. Therefore, a semiconductor memory suitable for integration and having improved reliability and productivity can be obtained.

[Brief description of the drawings]

FIG. 1 is a process sectional view of one embodiment of a method for manufacturing a semiconductor memory of the present invention.

FIG. 2 is a circuit diagram of an example of a unit cell of a semiconductor memory using a ferroelectric.

3A is a plan view of a structure of an example of a unit cell of a semiconductor memory using a ferroelectric, and FIG. 3B is a cross-sectional view taken along the line AA ′ in FIG.

FIG. 4 is a process sectional view of one embodiment of a conventional method for manufacturing a semiconductor memory.

[Explanation of symbols]

1 Word line (polysilicon) 2 Plate line or ferroelectric capacitor lower electrode (Pt / T
i) 3 Bit line (Al wiring) 4 Ferroelectric upper electrode (Pt) 5 Local wiring (Al wiring) 6 Silicon n + layer 7 Contact pad (WSi ₂ ) 8 Ferroelectric (Pb (Zr _0.53 Ti _0.47 ) O ₃ 9) Interlayer film (silicon oxide film) 10 Silicon p-type layer 11 Base interlayer film (silicon oxide film) 12 Capacitance upper interlayer film (silicon oxide film)

Claims (5)

(57) [Claims] 1. An integrated circuit formed on a substrate, a first interlayer insulating film having a contact pad provided on the integrated circuit, and a contact pad on the first interlayer insulating film. A capacitor portion including a capacitor lower electrode, a dielectric layer, and a capacitor upper electrode provided at different positions on a plane; and a second interlayer insulating film for electrically connecting the capacitor portion and the integrated circuit. A semiconductor device comprising local wiring provided by the first interlayer insulating film and the second interlayer insulating film.
A semiconductor device, wherein an interface with the interlayer insulating film is located below an interface between the first interlayer insulating film and the capacitor lower electrode. 2. An integrated circuit formed on a substrate, a first interlayer insulating film having a contact pad provided on the integrated circuit, and the contact pad on the first interlayer insulating film. A capacitor portion including a capacitor lower electrode, a dielectric layer, and a capacitor upper electrode provided at different positions on a plane; and a second interlayer insulating film for electrically connecting the capacitor portion and the integrated circuit. Wherein the thickness of the second interlayer insulating film is substantially equal at least on the capacitor portion and on the contact pad portion. 3. The method according to claim 1, wherein the dielectric layer is at least Pb (Zr _{1 -x
Ti x) O 3, SrBi 2} Ta 2 O 9, SrTiO 3,
The semiconductor device according to claim 1, wherein the semiconductor device includes _{one of} (Ba _1-x Sr _x ) TiO ₃ . 4. The semiconductor device according to claim 1, wherein said first and second interlayer insulating films are made of at least one of a silicon oxide film, a phosphorus-doped silicon oxide film, a boron-doped silicon oxide film, phosphorus, and a boron-doped oxide film. Item 3. The semiconductor device according to item 1 or 2. 5. A first step of forming at least a capacitor lower electrode and a dielectric film on a first interlayer insulating film having a contact pad, and simultaneously processing the capacitor lower electrode and the dielectric film. A second step of processing the first interlayer insulating film until the contact pads are exposed.