JP3057156B2 - Wiring board and its manufacturing method - Google Patents
Wiring board and its manufacturing methodInfo
- Publication number
- JP3057156B2 JP3057156B2 JP28611798A JP28611798A JP3057156B2 JP 3057156 B2 JP3057156 B2 JP 3057156B2 JP 28611798 A JP28611798 A JP 28611798A JP 28611798 A JP28611798 A JP 28611798A JP 3057156 B2 JP3057156 B2 JP 3057156B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resist layer
- solder
- solder resist
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 103
- 239000004020 conductor Substances 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims description 192
- 239000011347 resin Substances 0.000 claims description 19
- 229920005989 resin Polymers 0.000 claims description 19
- 239000002344 surface layer Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 6
- 238000000016 photochemical curing Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 17
- 239000000758 substrate Substances 0.000 description 12
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 229910020674 Co—B Inorganic materials 0.000 description 1
- 229910018104 Ni-P Inorganic materials 0.000 description 1
- 229910018536 Ni—P Inorganic materials 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000000805 composite resin Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920013636 polyphenyl ether polymer Polymers 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
Landscapes
- Wire Bonding (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、主表面上に電子部
品を半田付けにより搭載するフリップチップ実装型の配
線基板とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounting type wiring board on which electronic components are mounted on a main surface by soldering, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】表面上に集積回路(ＩＣ)素子やその他の
電子部品をフリップチップ接続方式により実装する配線
基板は、上記チップと導通するための半田バンプを表面
に形成している。係る配線基板４０は、図４(Ａ)に示す
ように、感光性樹脂からなる複数の絶縁層４１，４３と
の間に導体層４２を有し、絶縁層４３と表面のソルダー
レジスト層４５との間に導体層４６を有する。導体層４
２と導体層４６の間はビア４４により導通される。ま
た、導体層４６の上にはソルダーレジスト層４５に形成
したビアホール４７内に底部を充填し、且つソルダーレ
ジスト層４５の表面よりも突出する半田バンプ５０が形
成されている。この半田バンプ５０が、上記集積回路
(ＩＣ)素子やその他の電子部品と接続するための端子と
して用いられる。2. Description of the Related Art A wiring board on which integrated circuit (IC) elements and other electronic components are mounted by flip-chip connection on a surface thereof has solder bumps formed on the surface to conduct the chip. As shown in FIG. 4A, such a wiring board 40 has a conductor layer 42 between a plurality of insulating layers 41 and 43 made of a photosensitive resin, and the insulating layer 43 and a solder resist layer 45 on the surface. A conductive layer 46 is provided between them. Conductor layer 4
2 and the conductive layer 46 are electrically connected by the via 44. A solder bump 50 is formed on the conductor layer 46 so as to fill the bottom of the via hole 47 formed in the solder resist layer 45 and protrude from the surface of the solder resist layer 45. This solder bump 50 is used for the integrated circuit.
(IC) Used as a terminal for connecting to elements and other electronic components.
【０００３】半田バンプ５０は次のようにして形成され
る。図４(Ｂ)に示すように、先ず、感光性樹脂からなる
ソルダーレジスト層４５に対し露光と現像を施す。する
と、露光強度は上記レジスト層４５の底部に行くほど低
下するため、やや円錐形状のビアホール４７が形成され
る。次に、このビアホール４７の底部に露出した導体層
４６の表面上に、Ｎｉメッキ層及びＡｕメッキ層からな
るメッキ層４８を薄く被覆する。更に、半田ペーストを
ビアホール４７内に充填し且つソルダーレジスト層４５
の表面よりも突出するように印刷する。突出した半田ペ
ーストをその融点まで加熱し溶融させると、表面張力に
より上端が図示のように略半球形状の接続部５４となっ
た半田バンプ５０を得ることができる。[0003] The solder bump 50 is formed as follows. As shown in FIG. 4B, first, the solder resist layer 45 made of a photosensitive resin is exposed and developed. Then, since the exposure intensity decreases toward the bottom of the resist layer 45, a slightly conical via hole 47 is formed. Next, a plating layer 48 composed of a Ni plating layer and an Au plating layer is thinly coated on the surface of the conductor layer 46 exposed at the bottom of the via hole 47. Furthermore, the solder paste is filled in the via hole 47 and the solder resist layer 45 is filled.
Print so that it protrudes from the surface. When the protruding solder paste is heated to its melting point and melted, a solder bump 50 having an upper end serving as a substantially hemispherical connection portion 54 as shown in the figure due to surface tension can be obtained.
【０００４】[0004]
【発明が解決すべき課題】ところで、上記半田バンプ５
０は、その底部５２がソルダーレジスト層４５に形成さ
れたビアホール４７に接触しているものの、その固着強
度はメッキ層４８と底部５２との密着強度のみに依存し
ている。従って、半田バンプ５０の固着強度が弱いた
め、何らかの外力が働くと、底部５２を含めて半田バン
プ５０がメッキ層４８から剥離したり、著しくはビアホ
ール４７から半田バンプ５０が抜け出すこともある。こ
の結果、配線基板４０内の導体層４２，４６と表面上に
実装した図示しない集積回路(ＩＣ)素子やその他の電子
部品との導通が不安定になったり、或いは導通が取れな
くなるという問題を生じることもあった。The solder bumps 5
In the case of 0, although the bottom 52 is in contact with the via hole 47 formed in the solder resist layer 45, the fixing strength depends only on the adhesion strength between the plating layer 48 and the bottom 52. Therefore, the solder bumps 50 including the bottom portion 52 may be peeled off from the plating layer 48 or the solder bumps 50 may come out of the via holes 47 significantly when some external force acts on the solder bumps 50 because the bonding strength of the solder bumps 50 is weak. As a result, the conduction between the conductor layers 42 and 46 in the wiring board 40 and an unillustrated integrated circuit (IC) element or other electronic components mounted on the surface becomes unstable, or the conduction becomes impossible. Sometimes it happened.
【０００５】本発明は、以上に説明した従来の技術にお
ける問題点を解決し、半田バンプの固着強度及び耐久性
を高め、且つ集積回路(ＩＣ)素子等と内部の導体層との
安定した導通を可能とする配線基板とその製造方法を提
供することを課題とする。The present invention solves the problems of the prior art described above, improves the bonding strength and durability of solder bumps, and provides stable conduction between an integrated circuit (IC) element and the like and an internal conductor layer. It is an object of the present invention to provide a wiring board and a method for manufacturing the same, which enable the above.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記課題を解
決するため、半田バンプの底部をソルダーレジスト層内
に物理的に係合させることに着想して成されたものであ
る。即ち、本発明の配線基板は、絶縁層の上に形成した
導体層と、上記絶縁層及び導体層の上に形成され、表層
寄りの光硬化層に囲まれた細径部分と導体層寄りの太径
部分とを備えたビアホールを有するソルダーレジスト層
と、 上記導体層の上に形成され且つ上記ソルダーレジ
スト層を貫通し上記ビアホール内に充填されるアンカー
部と、上記ソルダーレジスト層の表面よりも外側に突出
する接続部とを有する半田バンプと、を含み、上記半田
バンプのアンカー部は、上記ソルダーレジスト層の表層
寄りが細径で、且つ上記導体層寄りが太径である、こと
を特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has been made with the idea of physically engaging the bottom of a solder bump in a solder resist layer. That is, the wiring board of the present invention includes a conductor layer formed on the insulating layer, and a surface layer formed on the insulating layer and the conductor layer.
The narrow part surrounded by the light-cured layer closer to it and the large diameter closer to the conductor layer
A solder resist layer having a via hole having a portion, an anchor portion formed on the conductor layer and penetrating the solder resist layer and filling the via hole, and outside the surface of the solder resist layer. wherein the solder bumps having a connection portion projecting anchor portion of the solder bumps, the surface layer side of the above solder resist layer is thin, and the upper Symbol conductor layer nearer is thick diameter, and wherein the I do.
【０００７】これによれば、半田バンプは、光硬化層に
囲まれた表層寄りを細径とし且つ導体層寄りを太径とし
たアンカー部がソルダーレジスト層内に位置するため、
例えばその接続部に何らかの外力が加わっても、揺らい
だり変位しにくなる。従って、半田バンプと導体層との
密着強度が損なわれないため、配線基板内部の導体層と
その表面上に実装する集積回路(ＩＣ)素子等との導通を
確実に取ることができる。尚、上記の導体層には、その
表面に被覆する薄いＮｉメッキ層及びＡｕメッキ層から
なるメッキ層も含まれる。[0007] According to this, solder bumps, the light-cured layer
The enclosed surface toward the small diameter and the conductor layers near the large-diameter
The anchor part located in the solder resist layer
For example, even if some external force is applied to the connection portion, the connection portion will not swing or be displaced. Therefore, since the adhesion strength between the solder bumps and the conductor layer is not impaired, conduction between the conductor layer inside the wiring board and an integrated circuit (IC) element mounted on the surface thereof can be ensured. The above-mentioned conductor layer includes a plating layer made of a thin Ni plating layer and an Au plating layer covering the surface thereof.
【０００８】尚、前記ソルダーレジスト層は、表層のみ
に光硬化層が形成される感光性の樹脂からなる。これに
より、半田バンプのアンカー部における前記ソルダーレ
ジスト層の表層寄りの光硬化層に囲まれた部分を、その
導体層寄りの部分よりも細径に形成することが容易とな
り、上記アンカー部を確実に形成することが可能とな
る。[0008] Incidentally, the solder resist layer, ing from a photosensitive resin photocured layer is formed only in the surface layer. Ri by <br/> thereto, a portion which is surrounded by the photocurable layer of the surface near the solder resist layer in the anchor portions of the solder bumps, also it is easy to form a small diameter than the portion of the conductive layer nearer Thus, the anchor portion can be reliably formed.
【０００９】一方、上記配線基板を得るための製造方法
は、絶縁層及びその表面に形成した導体層の上に少なく
とも表層に光硬化層を形成可能なソルダーレジスト層を
形成する工程と、上記導体層の上方の所定位置をマスク
した状態で、上記ソルダーレジスト層に露光を施し、こ
のレジスト層の表層に光硬化層を形成する工程と、上記
ソルダーレジスト層を現像し、このレジスト層内に上記
光硬化層内が細径で且つ上記導体層寄りが太径となるビ
アホールを形成する工程と、上記ビアホール内及びその
上方に突出するように半田バンプを形成する工程と、を
含むことを特徴とする。これによれば、前記アンカー部
を有する半田バンプを確実に形成した配線基板を容易に
製造することができる。On the other hand, the manufacturing method for obtaining the wiring board includes a step of forming a solder resist layer capable of forming a photocurable layer at least on a surface layer on an insulating layer and a conductor layer formed on the surface thereof, A step of exposing the solder resist layer to light with a predetermined position above the layer being masked, forming a photocurable layer on the surface of the resist layer, and developing the solder resist layer, Forming a via hole in which the inside of the photocurable layer has a small diameter and the conductor layer has a large diameter near the conductor layer, and a step of forming a solder bump so as to protrude in and above the via hole. I do. According to this, it is possible to easily manufacture a wiring board on which the solder bumps having the anchor portions are securely formed.
【００１０】尚、上記ソルダーレジスト層を形成する感
光性の樹脂には、後述するように露光によってその表層
のみに光硬化層を形成する特性を有する１種類の樹脂を
用いても良いが、底層と表層とで感光性が相違する２種
類の樹脂を併用することもできる。この場合、２種類の
樹脂塗料を平行してコーティングする他、予め２種類の
樹脂フィルムをラミネートしたものを被覆して用いるこ
とも可能である。As the photosensitive resin forming the solder resist layer, one kind of resin having a property of forming a photocured layer only on the surface layer by exposure as described later may be used. It is also possible to use two types of resins having different photosensitivities between the resin and the surface layer. In this case, in addition to coating two kinds of resin paints in parallel, it is also possible to coat and use two kinds of resin films laminated in advance.
【００１１】また、前記光硬化層の厚みが、これを含む前
記ソルダーレジスト層の厚みの１０％〜３０％の範囲内
である、配線基板の製造方法も含まれる。更に、前記ソ
ルダーレジスト層が感光性樹脂からなり、その表層から
当該レジスト層の厚みの１０％〜３０％の厚みを光硬化
させる前記工程により、前記光硬化層を形成する、配線
基板の製造方法も含まれる。これらによれば、揺らいだ
り変位しにくい半田バンプを一層確実に形成することが
できる。尚、光硬化層の厚みがソルダーレジスト層の厚
みの３０％を超えると、アンカー部の太径部分が小さく
なって半田バンプが外力により揺らぎ易くなり、且つ半
田バンプにするための半田ペーストをビアホール内に充
填しにくくなる。また、ビアホール内へのメッキ液の流
入が低下して、導体層の表面へのメッキが困難となる。
一方、レジスト層の厚みの１０％未満では、光硬化層自
体が脆弱になり得るため、これらを除外した上記の範囲
としたものである。[0011] The present invention also includes a method of manufacturing a wiring board, wherein the thickness of the photocurable layer is in the range of 10% to 30% of the thickness of the solder resist layer including the photocurable layer. In addition,
The rudder resist layer is made of photosensitive resin, and the surface layer
Photocuring the thickness of 10% to 30% of the thickness of the resist layer
Forming the photocurable layer by the step of
A method for manufacturing a substrate is also included. According to these, it is possible to more reliably form the displacement hard solder bumps Guests shaken. When the thickness of the photo-cured layer exceeds 30% of the thickness of the solder resist layer, the large diameter portion of the anchor portion becomes small, so that the solder bump is easily fluctuated by an external force, and the solder paste for forming the solder bump is formed in a via hole. It becomes difficult to fill inside. In addition, the flow of the plating solution into the via hole is reduced, and it becomes difficult to perform plating on the surface of the conductor layer.
On the other hand, if the thickness of the resist layer is less than 10%, the photo-cured layer itself may be fragile.
【００１２】[0012]
【発明の実施の形態】以下において本発明の実施に好適
な形態を図面と共に説明する。図１(Ａ)は、本発明の配
線基板１の要部を示す端面図である。この配線基板１
は、厚さ方向の中央に位置するコア基板２と、その両表
面に公知のフォトリソグラフィ技術により形成した第１
の導体層６，６と、それらの上に形成した絶縁層８,８
とを有する。また、絶縁層８,８の上に形成した第２の
導体層１２,１２、及びその上に形成したソルダーレジス
ト層１０,１０も有する。上記コア基板２は絶縁板であ
り、ビスマレイミド・トリジアン(ＢＴ)樹脂とガラス繊
維との複合材からなり、両表面の各導体層６同士を導通
するため、予め穿設されたスルーホール３内にスルーホ
ール導体４を形成している。Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is an end view showing a main part of a wiring board 1 of the present invention. This wiring board 1
Is a core substrate 2 located at the center in the thickness direction, and a first substrate formed on both surfaces thereof by a known photolithography technique.
Conductor layers 6, 6 and insulating layers 8, 8 formed thereon.
And The semiconductor device also has second conductor layers 12, 12 formed on the insulating layers 8, 8, and solder resist layers 10, 10 formed thereon. The core substrate 2 is an insulating plate, is made of a composite material of bismaleimide-trizian (BT) resin and glass fiber, and has a through hole 3 formed in advance to electrically connect the conductor layers 6 on both surfaces. Are formed with through-hole conductors 4.
【００１３】また、上記絶縁層８はエポキシ系樹脂から
なり、その内部に形成したビアホール７内に第１と第２
の各導体層６，１２を導通する略円錐形状のビア導体９
を形成している。更に、第２の導体層１２上の所定の位
置には、ソルダーレジスト層１０内に形成したビアホー
ル１９内を貫通して半田バンプ２０を形成している。
尚、図１(Ａ)で下側のソルダーレジスト層１０の適所に
は、開口部１４が形成され、その底部に露出した第２の
導体層１６は、表面にＮｉ及びＡｕメッキを被覆され、
図示しないマザーボードとの導通を取る接続端子とされ
る。The insulating layer 8 is made of an epoxy resin, and the first and second insulating layers 8 are formed in via holes 7 formed therein.
Substantially conical via conductor 9 that conducts through the respective conductor layers 6 and 12
Is formed. Further, solder bumps 20 are formed at predetermined positions on the second conductor layer 12 so as to penetrate through the via holes 19 formed in the solder resist layer 10.
In addition, an opening 14 is formed at an appropriate position of the lower solder resist layer 10 in FIG. 1A, and the surface of the second conductor layer 16 exposed at the bottom is coated with Ni and Au plating.
It is a connection terminal for establishing conduction with a motherboard (not shown).
【００１４】図１(Ｂ)に示すように、半田バンプ２０
は、導体層１２の表面に薄く被覆したメッキ層２６の上
にそのアンカー部２２を固着させている。即ち、ソルダ
ーレジスト層１０内の表層には後述する露光により光硬
化層１１が形成されており、光硬化層１１の端部１８，
１８が上記アンカー部２２に倣った形状のビアホール１
９の狭い開口部に位置する。従って、導体層１２寄りが
太径で表層の光硬化層１１寄りが細径のビアホール１９
内に、これに倣った形状の半田バンプ２０におけるアン
カー部２２が形成される。一方、ソルダーレジスト層１
０の表面上には、半田バンプ２０における半球形状の接
続部２４が突出し、基板１の表面上に実装される集積回
路(ＩＣ)素子やその他の電子部品との導通に使用され
る。As shown in FIG. 1B, the solder bump 20
The anchor portion 22 is fixed on a plating layer 26 which thinly covers the surface of the conductor layer 12. That is, the photocurable layer 11 is formed on the surface layer in the solder resist layer 10 by exposure to be described later, and the end portions 18 of the photocurable layer 11,
Reference numeral 18 denotes a via hole 1 having a shape following the anchor portion 22.
Nine narrow openings. Therefore, the via hole 19 having a large diameter near the conductor layer 12 and a small diameter near the light curing layer 11 on the surface layer.
Inside, the anchor portion 22 of the solder bump 20 having a shape corresponding to this is formed. On the other hand, solder resist layer 1
A hemispherical connection portion 24 of the solder bump 20 protrudes from the surface of the substrate 1 and is used for conduction with an integrated circuit (IC) element and other electronic components mounted on the surface of the substrate 1.
【００１５】この半田バンプ２０は、上記アンカー部２
２をソルダーレジスト層１０内に位置させ、且つアンカ
ー部２２の底面で導体層１２と固着している。このた
め、上記接続部２４が何らかの外力を受けても、アンカ
ー部２２の細径部分がソルダーレジスト層１０の光硬化
層１１に挟持されているため、図１(Ｂ)で左右方向に揺
らいだり変位したりせず、且つ上方に移動したり抜けた
りしない。従って、係る半田バンプ２０により、配線基
板１内の導体層６，１２と表面上に実装する電子部品と
の導通を確実且つ安定的に取れ、基板１内外に渉っ形成
される回路の信頼性を保つことができる。The solder bump 20 is connected to the anchor 2
2 is located in the solder resist layer 10 and is fixed to the conductor layer 12 on the bottom surface of the anchor portion 22. For this reason, even if the connecting portion 24 receives some external force, the small-diameter portion of the anchor portion 22 is sandwiched by the light-cured layer 11 of the solder resist layer 10, so that it swings in the left-right direction in FIG. Does not displace and does not move upwards or fall out. Therefore, the conductive connection between the conductor layers 6 and 12 in the wiring board 1 and the electronic components mounted on the surface can be ensured and stably provided by the solder bumps 20, and the reliability of the circuit formed inside and outside the board 1 is improved. Can be kept.
【００１６】図２は、上記半田バンプ２０を主体とした
配線基板１の製造方法に関する。図２(Ａ)に示すよう
に、絶縁層８の上に銅からなる第２の導体層１２が形成
され、これらの上に厚さ２０μｍのソルダーレジスト層
１０が形成される。このレジスト層１０は、感光性樹脂
(例えば、日本ペイント(株)製の商品名プロビコート５５
００、或いは、チバガイギー社製のプロビマー５２等)か
ら形成される。次に、ソルダーレジスト層１０に対し一
次熱処理を施す。この一次熱処理は、ソルダーレジスト
層１０とパターニングのためのマスクＭとを付着させな
いために行う。FIG. 2 relates to a method of manufacturing the wiring board 1 mainly using the solder bumps 20. As shown in FIG. 2A, a second conductor layer 12 made of copper is formed on the insulating layer 8, and a solder resist layer 10 having a thickness of 20 μm is formed thereon. This resist layer 10 is made of a photosensitive resin
(For example, Provicoat 55 (trade name, manufactured by Nippon Paint Co., Ltd.)
00 or Provimer 52 manufactured by Ciba-Geigy). Next, primary heat treatment is performed on the solder resist layer 10. This primary heat treatment is performed so as not to attach the solder resist layer 10 and the mask M for patterning.
【００１７】次いで、図２(Ｂ)に示すように、導体層１
２上の所定の位置で且つソルダーレジスト層１０に近接
してマスクＭを配置する。この状態で、レジスト層１０
に対し図中の矢印のように紫外線等を照射して露光す
る。すると、図示のように、マスクＭに遮蔽されていな
いレジスト層１０の表層に沿って、厚さ４〜５μｍ程度
の光硬化層１１が形成される。一方、マスクＭ直下のレ
ジスト層１０及び光硬化層１１下側の内部は光硬化され
ていない。Next, as shown in FIG.
The mask M is arranged at a predetermined position on the substrate 2 and close to the solder resist layer 10. In this state, the resist layer 10
Is exposed to ultraviolet light or the like as indicated by the arrow in the figure. Then, as shown in the figure, a photocured layer 11 having a thickness of about 4 to 5 μm is formed along the surface layer of the resist layer 10 which is not shielded by the mask M. On the other hand, the inside of the lower part of the resist layer 10 and the photocurable layer 11 immediately below the mask M is not photocured.
【００１８】更に、マスクＭを除去した露光後のソルダ
ーレジスト層１０に対し、現像液を約５.０ｋｇ／ｃｍ2
の圧力で噴射して約３０秒間現像する。すると、図２
(Ｃ)に示すように、光硬化していないマスクＭ直下のレ
ジスト層１０内に、表層の光硬化層１１内にその端部１
８に周囲を囲まれた細径(マスクＭの径に略相当する)
で、且つ導体層１２寄りが太径の略球形状を呈するビア
ホール１９が形成される。これは、ソルダーレジスト層
１０の内部には光硬化が及んでいないため、現像による
エッチングの際、レジスト層１０の厚み方向と共にこれ
と直角する方向にもエッチングが進行するからである。
尚、現像後のソルダーレジスト層１０の表面及びビアホ
ール１９の内面を整えるため、リンス液を約２.０ｋｇ
／ｃｍ2の圧力で約１５秒間噴射する。また、リンス後
のソルダーレジスト層１０に対し、これを完全に硬化さ
せるための二次熱処理(キュア)を施す。Further, a developing solution is applied to the exposed solder resist layer 10 from which the mask M has been removed by about 5.0 kg / cm 2.
And develop for about 30 seconds. Then, Figure 2
As shown in (C), the end portion 1 is placed in the photo-cured layer 11 in the surface layer in the resist layer 10 immediately below the mask M that has not been photo-cured.
Small diameter surrounded by 8 (approximately equivalent to the diameter of mask M)
Thus, a via hole 19 having a substantially spherical shape with a large diameter near the conductor layer 12 is formed. This is because the photo-curing has not reached the inside of the solder resist layer 10, and therefore, during the etching by development, the etching proceeds in the thickness direction of the resist layer 10 as well as in the direction perpendicular thereto.
In order to prepare the surface of the solder resist layer 10 after development and the inner surface of the via hole 19, about 2.0 kg of a rinsing liquid was used.
/ Cm 2 for about 15 seconds. Further, a second heat treatment (curing) for completely curing the solder resist layer 10 after the rinsing is performed.
【００１９】次いで、図２(Ｄ)に示すように、ビアホー
ル１９内に露出した導体層１２の表面上に、Ｎｉメッキ
層及びＡｕメッキ層を薄く被覆し、メッキ層２６を形成
する。これらは、導体層１２の一部になってその表面を
保護すると共に、次述する半田との密着性を高めるため
に用いられる。そして、図２(Ｅ)に示すように、ビアホー
ル１９内に充填し且つその上方に突出するように、半田
ペースト２５を図示しないメタルマスクを用いて印刷す
る。この際、ビアホール１９内にはこれに倣った形状の
アンカー部２２が形成される。Next, as shown in FIG. 2D, a Ni plating layer and an Au plating layer are thinly coated on the surface of the conductor layer 12 exposed in the via hole 19, and a plating layer 26 is formed. These are used to protect the surface as a part of the conductor layer 12 and to enhance the adhesion to the solder described below. Then, as shown in FIG. 2E, the solder paste 25 is printed using a metal mask (not shown) so as to fill the via hole 19 and protrude upward. At this time, an anchor portion 22 having a shape following the via hole 19 is formed in the via hole 19.
【００２０】最後に、上記半田ペースト２５を加熱(リ
フロー)すると、ソルダーレジスト層１０の外側に突出
した半田ペースト２５は、図２(Ｆ)に示すように、その
表面張力により略半球形状の接続部２４となって硬化
し、半田バンプ２０を得ることができる。この際メッキ
層２６内のＡｕメッキ層は半田中に拡散して吸収され
る。以上のように、本発明の配線基板１の製造方法によ
れば、ソルダーレジスト層１０に露光によって表層のみ
に光硬化層１１を形成する感光性樹脂を用いたので、ア
ンカー部２２を有する半田バンプ２０を容易且つ確実に
形成できる。従って、半田バンプ２０と基板１との密着
強度が高く安定すると共に、表面上に実装する電子部品
との導通も確実且つ安定して取ることが可能となる。Finally, when the solder paste 25 is heated (reflowed), the solder paste 25 protruding outside the solder resist layer 10 has a substantially hemispherical connection due to its surface tension as shown in FIG. The portion 24 is cured and the solder bump 20 can be obtained. At this time, the Au plating layer in the plating layer 26 is diffused and absorbed in the solder. As described above, according to the method for manufacturing the wiring board 1 of the present invention, since the photosensitive resin that forms the photocured layer 11 only on the surface layer by exposing the solder resist layer 10 is used, the solder bump having the anchor portion 22 is used. 20 can be formed easily and reliably. Therefore, the adhesion strength between the solder bumps 20 and the substrate 1 is high and stable, and the conduction with the electronic components mounted on the surface can be reliably and stably obtained.
【００２１】本発明は、以上に説明した形態に限定され
るものではない。例えば、図３(Ａ)に示すように、絶縁
層８の上に第２の導体層１２が形成され、これらの上に
厚さ２０μｍのソルダーレジスト層３０を形成する。該
ソルダーレジスト層３０は、非感光性樹脂からなる第１
のレジスト層３２の上に感光性樹脂からなる第２のレジ
スト層３４を形成したものである。第２のレジスト層３
４の厚さは４〜５μｍ程度である。尚、各レジスト層３
２，３４は、各樹脂塗料を個別にコーティングして２層
構造のレジスト層３０を形成する他に、予め所定厚さの
フィルムにした各樹脂をラミネートした積層フィルムを
図示しない加熱ローラ等を用いて、絶縁層８及び導体層
１２の上に被覆しても良い。The present invention is not limited to the embodiment described above. For example, as shown in FIG. 3A, a second conductor layer 12 is formed on the insulating layer 8, and a solder resist layer 30 having a thickness of 20 μm is formed thereon. The solder resist layer 30 is made of a first non-photosensitive resin.
A second resist layer 34 made of a photosensitive resin is formed on the resist layer 32 of FIG. Second resist layer 3
The thickness of 4 is about 4 to 5 μm. In addition, each resist layer 3
Reference numerals 2 and 34 each use a heating roller or the like (not shown) to form a two-layer resist layer 30 by individually coating each resin paint, and a laminated film obtained by laminating each resin previously formed into a film having a predetermined thickness. Thus, the insulating layer 8 and the conductor layer 12 may be covered.
【００２２】次に、図３(Ｂ)に示すように、第２のレジ
スト層３４に近接してマスクＭを配置した状態で、レジ
スト層３４に対し図中の矢印のように紫外線等を照射し
て露光する。すると、マスクＭに遮蔽されていないレジ
スト層３４は光硬化層３５になる。一方、マスクＭ直下
のレジスト層３４及び第１のレジスト層３２は光硬化し
ていない。更に、露光後のレジスト層３４，３２及び光
硬化層３５に対し、前記同様に現像液を噴射してエッチ
ングする。すると、図３(Ｃ)に示すように、光硬化層３
５の端部３８に囲まれた光硬化層３５内が細径で、且つ
導体層１２寄りのレジスト層３２が太径のビアホール３
６を形成することができる。その後、ビアホール３６内
をリンスして前記図２(Ｄ)〜(Ｆ)に示した各工程を行う
ことによって、配線基板１を得ることができる。Next, as shown in FIG. 3B, with the mask M arranged close to the second resist layer 34, the resist layer 34 is irradiated with ultraviolet rays or the like as shown by arrows in the figure. And expose. Then, the resist layer 34 that is not shielded by the mask M becomes the photocurable layer 35. On the other hand, the resist layer 34 and the first resist layer 32 immediately below the mask M are not photo-cured. Further, the exposed resist layers 34 and 32 and the photo-cured layer 35 are etched by spraying a developer in the same manner as described above. Then, as shown in FIG.
5, the inside of the photo-cured layer 35 surrounded by the end 38 has a small diameter, and the resist layer 32 near the conductor layer 12 has a large diameter via hole 3.
6 can be formed. Thereafter, the inside of the via hole 36 is rinsed and the steps shown in FIGS. 2D to 2F are performed, whereby the wiring substrate 1 can be obtained.
【００２３】また、本発明のアンカー部には、前記アン
カー部２２のような略球形状に限らず、垂直断面が略三
角形、逆向きの三角形、又は菱形を呈する形状も含まれ
る。更に、前記コア基板２には、前記形態で使用したＢ
Ｔ樹脂−ガラス複合材の他、ガラス−エポキシ材、ガラ
ス−ＰＰＥ材や、紙−エポキシ等の複合樹脂材、或いは
エポキシ、ＢＴレジン、ポリイミド、ＰＰＥ、ＰＴＦＥ
等の樹脂を用いても良い。或いは、これらに替えてセラ
ミック基板を用いることも可能である。また、本発明の
配線基板には、絶縁層とソレダーレジスト層との間に導
体層を有し、且つ導体層の上に半田バンプが形成される
形態を有するものであれば、上記コア基板を欠いた配線
基板も含まれる。Further, the anchor portion of the present invention is not limited to a substantially spherical shape like the anchor portion 22, but also includes a shape having a vertical cross section of a substantially triangular, inverted triangle, or rhombus. Further, the core substrate 2 has B
In addition to T-resin-glass composite materials, glass-epoxy materials, glass-PPE materials, composite resin materials such as paper-epoxy, or epoxy, BT resin, polyimide, PPE, PTFE
May be used. Alternatively, a ceramic substrate can be used instead. In addition, the wiring board of the present invention may be any of the above-described core substrates as long as the wiring board has a conductor layer between the insulating layer and the solder resist layer and has a form in which solder bumps are formed on the conductor layer. Includes wiring boards lacking.
【００２４】更に、前記各導体層６,１２には銅に限ら
ず、Ｎｉ及びその合金(Ｎｉ−Ｐ,Ｎｉ−Ｂ,Ｎｉ−Ｃｕ−
Ｐ)、Ｃｏとその合金(Ｃｏ−Ｐ,Ｃｏ−Ｂ,Ｃｏ−Ｎｉ−
Ｐ)、Ｓｎとその合金(Ｓｎ−Ｐｂ,Ｓｎ−Ｐｂ−Ｐｄ)、
或いはＡｕ,Ａｇ,Ｐｄ，Ｐｔ,Ｒｈ,Ｒｕ等及びそれらの
合金の何れを用いることも可能である。尚、本発明の半
田バンプと接続される電子部品には、一つの集積回路や
半導体素子の他、複数個の半導体素子を固着して用いる
マルチチップモジュールも適用することができる。ま
た、トランジスタ、ＦＥＴ等の半導体素子やコンデン
サ、抵抗、インダクタ、ＳＡＷフィルタ、その他の電子
部品も含まれる。Further, the conductor layers 6 and 12 are not limited to copper, but Ni and alloys thereof (Ni-P, Ni-B, Ni-Cu-).
P), Co and its alloys (Co-P, Co-B, Co-Ni-
P), Sn and its alloys (Sn-Pb, Sn-Pb-Pd),
Alternatively, any of Au, Ag, Pd, Pt, Rh, Ru and the like and alloys thereof can be used. The electronic component connected to the solder bump of the present invention may be a single integrated circuit or a semiconductor element, or a multichip module in which a plurality of semiconductor elements are fixedly used. Also included are semiconductor elements such as transistors and FETs, capacitors, resistors, inductors, SAW filters, and other electronic components.
【００２５】[0025]
【発明の効果】以上において説明した本発明の配線基板
によれば、半田バンプを基板本体に強固に固着でき、そ
の耐久性を高めると共に、内部の導体層との導通も確実
且つ安定して取ることができる。また、本発明の製造方
法によれば、上記のような半田バンプを有する配線基板
を容易且つ確実に製造することができる。According to the wiring board of the present invention described above, the solder bumps can be firmly fixed to the board main body, the durability thereof is improved, and the conduction with the internal conductor layer is reliably and stably obtained. be able to. Further, according to the manufacturing method of the present invention, it is possible to easily and reliably manufacture a wiring board having the above-described solder bumps.
【図１】(Ａ)は本発明の配線基板の要部を示す端面図、
(Ｂ)は(Ａ)中の一点鎖線部分Ｂの拡大図。FIG. 1A is an end view showing a main part of a wiring board of the present invention,
(B) is an enlarged view of an alternate long and short dash line portion B in (A).
【図２】(Ａ)乃至(Ｆ)は本発明の配線基板の各製造工程
を示す概略図。FIGS. 2A to 2F are schematic views showing respective manufacturing steps of a wiring board of the present invention.
【図３】(Ａ)乃至(Ｃ)は別形態の各製造工程を示す概略
図。FIGS. 3A to 3C are schematic views showing respective manufacturing steps of another embodiment.
【図４】(Ａ)は従来の配線基板の要部を示す断面図、
(Ｂ)は(Ａ)中の一点鎖線部分Ｂの拡大図。FIG. 4A is a cross-sectional view showing a main part of a conventional wiring board,
(B) is an enlarged view of an alternate long and short dash line portion B in (A).
１……………配線基板 ８……………絶縁層 １０，３０…ソルダーレジスト層 １１，３５…光硬化層 １２…………導体層１９…………ビアホール ２０…………半田バンプ ２２…………アンカー部 ２４…………接続部 Ｍ……………マスクDESCRIPTION OF SYMBOLS 1 ... Wiring board 8 ... Insulating layer 10, 30 ... Solder resist layer 11, 35 ... Photocurable layer 12 ...... Conductor layer 19 ... Via hole 20 ... Solder bump 22 anchor part 24 connection part M mask
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鬼頭 直樹 愛知県名古屋市瑞穂区高辻町14番18号 日本特殊陶業株式会社内 (72)発明者 平野 聡 愛知県名古屋市瑞穂区高辻町14番18号 日本特殊陶業株式会社内 (56)参考文献 特開 平１−181596（ＪＰ，Ａ) 特開 平８−228070（ＪＰ，Ａ) 特開 平７−273439（ＪＰ，Ａ) 特開 平８−18239（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/34 502 H01L 21/60 311 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Naoki Kito 14-18, Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture Inside Japan Specialty Ceramics Co., Ltd. (72) Inventor Satoshi Hirano 14-18, Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture No. Japan Special Ceramics Co., Ltd. (56) References JP-A-1-181596 (JP, A) JP-A-8-228070 (JP, A) JP-A-7-273439 (JP, A) JP-A-8- 18239 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H05K 3/34 502 H01L 21/60 311
Claims (4)
化層に囲まれた細径部分と導体層寄りの太径部分とを備
えたビアホールを有するソルダーレジスト層と、 上記
導体層の上に形成され且つ上記ソルダーレジスト層を貫
通し上記ビアホール内に充填されるアンカー部と、上記
ソルダーレジスト層の表面よりも外側に突出する接続部
とを有する半田バンプと、を含み、 上記半田バンプのアンカー部は、上記ソルダーレジスト
層の表層寄りが細径で、且つ上記導体層寄りが太径であ
る、 ことを特徴とする配線基板。A conductor layer formed on the insulating layer; and a light hardening layer formed on the insulating layer and the conductor layer, the surface being closer to the surface.
With a small-diameter part surrounded by an oxide layer and a large-diameter part near the conductor layer.
A solder resist layer having the obtained via hole; an anchor portion formed on the conductor layer and penetrating the solder resist layer to be filled in the via hole; and a connecting portion projecting outside the surface of the solder resist layer. wherein the solder bumps having the bets, the anchor portions of the solder bumps, the wiring board surface layer side of the above solder resist layer is small in diameter, a top Symbol conductive layer near the large diameter and it is characterized.
に少なくとも表層に光硬化層を形成可能なソルダーレジ
スト層を形成する工程と、 上記導体層の上方の所定位置をマスクした状態で、上記
ソルダーレジスト層に露光を施し、このレジスト層の表
層に光硬化層を形成する工程と、 上記ソルダーレジスト層を現像し、このレジスト層内に
上記光硬化層内が細径で且つ上記導体層寄りが太径とな
るビアホールを形成する工程と、 上記ビアホール内及びその上方に突出するように半田バ
ンプを形成する工程と、を含むことを特徴とする配線基
板の製造方法。2. A step of forming a solder resist layer capable of forming a photocurable layer at least on a surface layer on an insulating layer and a conductor layer formed on the surface thereof, and in a state where a predetermined position above the conductor layer is masked. Exposing the solder resist layer to form a photo-cured layer on the surface of the resist layer; and developing the solder resist layer. The photo-cured layer has a small diameter in the resist layer and the conductor A method for manufacturing a wiring board, comprising: a step of forming a via hole having a large diameter near a layer; and a step of forming a solder bump so as to protrude in and above the via hole.
ルダーレジスト層の厚みの１０％〜３０％の範囲内であ
る、 ことを特徴とする請求項２に記載の配線基板の製造方
法。The thickness of wherein the photocurable layer is said in the range of 10% to 30% of the thickness of the solder resist layer, manufacturing method of a wiring board according to claim 2, characterized in that it comprises the same .
なり、その表層から当該レジスト層の厚みの１０％〜３
０％の厚みを光硬化させる前記工程により、前記光硬化
層を形成する、 ことを特徴とする請求項２又は３に記載の配線基板の製
造方法。4. The method according to claim 1, wherein the solder resist layer is made of a photosensitive resin.
By the step of photocuring 0% of the thickness, to form the photocurable layer, a manufacturing method of a wiring board according to claim 2 or 3, characterized in that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28611798A JP3057156B2 (en) | 1998-10-08 | 1998-10-08 | Wiring board and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28611798A JP3057156B2 (en) | 1998-10-08 | 1998-10-08 | Wiring board and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000114698A JP2000114698A (en) | 2000-04-21 |
| JP3057156B2 true JP3057156B2 (en) | 2000-06-26 |
Family
ID=17700162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28611798A Expired - Fee Related JP3057156B2 (en) | 1998-10-08 | 1998-10-08 | Wiring board and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3057156B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1387604A1 (en) * | 2002-07-31 | 2004-02-04 | United Test Center Inc. | Bonding pads of printed circuit board capable of holding solder balls securely |
| DE10235332A1 (en) * | 2002-08-01 | 2004-02-19 | Infineon Technologies Ag | Multiple layer switch support used in flip-chip technology comprises a semiconductor chip and/or a discrete component, a rewiring layer, an insulating layer with through-structures, and outer contact surfaces |
| JP4504925B2 (en) * | 2004-01-30 | 2010-07-14 | イビデン株式会社 | Multilayer printed wiring board and manufacturing method thereof |
| KR101031620B1 (en) * | 2006-05-29 | 2011-05-02 | 가부시키가이샤후지쿠라 | Wiring board |
| TWI367697B (en) * | 2009-08-17 | 2012-07-01 | Nan Ya Printed Circuit Board | Printed circuit board and fabrication method thereof |
-
1998
- 1998-10-08 JP JP28611798A patent/JP3057156B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000114698A (en) | 2000-04-21 |
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