JP3054816U - Reset circuit - Google Patents

Abstract

(57) [Problem] To provide a dedicated port for reset control in order to control a reset sequence of a plurality of ICs or the like, which may increase the cost. SOLUTION: Resistances R1 and R2 are connected in parallel to a power supply line from a power supply VDD, and capacitors C1 and C2 are connected in series to the power supply line, respectively. The system controller 10 and the DSP 20 are activated at a time difference by using the same. When the power supply voltage decreases, the reset IC 30 pulls the reset terminal voltages of the system controller 10 and the DSP 20 to a low level through the diode D1 and simultaneously resets the capacitors C1, Since the charge of C2 is discharged, the charge of the capacitor C2 is completely discharged at the time of reset.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a reset circuit for issuing a reset request to a plurality of ICs and the like, and more particularly to a reset circuit that activates each IC and the like with a predetermined time difference and simultaneously resets each IC and the like when a reset request is made. About.

[0002]

[Prior art]

 Conventionally, when a plurality of ICs are started with a predetermined delay time, a predetermined start signal is appropriately delayed by a delay circuit and input to a reset terminal of each IC, thereby starting each IC with a desired time difference. Various configurations are known. Here, when an error such as an instantaneous interruption occurs and each IC is reset, it is usual to reset each IC at the same time. However, as described above, each IC is started with a time difference. Therefore, it has been difficult to control a reset sequence such as resetting each IC or the like at the same time in the event of an abnormality with a predetermined reset circuit.

[0005] Therefore, there has been known a device in which a dedicated port for reset control is provided in each IC or the like, and the reset sequence of a plurality of ICs or the like is controlled using the dedicated port. For example, in Japanese Unexamined Utility Model Publication No. 57-179754, among microcomputers capable of mutually transferring data, the output terminal of the main microcomputer is connected to the reset terminal of the slave microcomputer. In addition, the slave microcomputer is reset by the output signal of the master microcomputer.

[Problems to be solved by the invention]

 The conventional technique described above has the following problems. Since a dedicated port for reset control is provided to control the reset sequence of a plurality of ICs, the cost may increase.

The present invention has been made in view of the above-mentioned problem, and it is intended to start a plurality of ICs and the like at a predetermined time difference with an inexpensive configuration and to simultaneously reset the plurality of ICs and the like when a reset request is made. It is an object of the present invention to provide a reset circuit capable of performing the above.

[0005]

[Means for Solving the Problems]

 In order to achieve the above object, the invention according to claim 1 comprises a plurality of time constant circuits connected to a predetermined signal transmission line and provided with a predetermined capacitor and having different time constants from each other; In each of the time constant circuits, a plurality of reset terminal connection terminals, which are branched from a wire line on the former stage side of the capacitor and are connected to a reset terminal of an IC or the like, and a high-level signal is transmitted to the signal transmission line when the IC or the like is started up. And a reset request circuit that simultaneously pulls the voltage level of each reset terminal connection terminal to a low level at the time of a reset request and discharges the charge of each capacitor in the plurality of time constant circuits.

In the invention according to claim 1 configured as described above, when activating a plurality of ICs and the like, the reset request circuit outputs a high-level signal to a predetermined signal transmission path. Then, a current flows through the plurality of time constant circuits, and charging of the capacitors in each time constant circuit is started. When the charging is completed, the voltage level of the reset terminal connection end branched from the previous line of the same capacitor is obtained. Becomes high level, and an IC or the like in which the reset terminal is connected to the reset terminal connection terminal is activated. Here, the time required to charge each capacitor is determined by the time constant of each time constant circuit, but the time constant of each time constant circuit is different. Start up at the appropriate time difference. On the other hand, when the reset request circuit requests a reset, the voltage level at the connection terminal of each reset terminal is pulled to a low level. Then, the ICs and the like connected to the respective reset terminal connection terminals are simultaneously reset, and the capacitors in the respective time constant circuits are discharged.

That is, there are a plurality of ICs and the like, and each IC and the like are started with a predetermined time difference so as to be delayed from a start request from a reset request circuit. It takes. Specifically, it is suitable for use when a single reset request circuit controls reset processing of a plurality of ICs or the like that require different reset periods. As described above, which time difference is used to start up is determined by the time constant of each time constant circuit, and these values may be appropriately selected so that a desired time difference is obtained. After resetting as described above, each IC and the like are started up in the same manner, but since the charge of the capacitor in each time constant circuit is completely discharged and no charge remains, The determined time constant of each time constant circuit is always constant, and each IC can be started with a desired time difference.

The number of ICs or the like to which the reset circuit is applied is not particularly limited, but as an example of a simple configuration, the invention according to claim 2 is based on the reset circuit according to claim 1. The constant circuit includes first and second time constant circuits, and the first time constant circuit includes first and second resistors connected in parallel to each other with respect to the signal transmission path; A diode connected to the second stage of the first resistor as a cathode and the second stage of the second resistor as an anode, and a first capacitor connected in series to the first resistor. And the second time constant circuit includes the second resistor and a second capacitor connected in series to the second resistor. No. By pulling the voltage level at the front stage of one capacitor to a low level, the voltage level at the front stage of the second capacitor is pulled to a low level via the diode.

In the invention according to claim 2 configured as described above, when the reset request circuit outputs a high-level signal for activating an IC or the like, the reset request circuit connects to the first resistor connected to the signal transmission line. The current flows through the second resistor, but the current flowing through the second resistor flows through the diode, so that only the first capacitor is charged. At this time, the time constant of the first time constant circuit having such a configuration is determined by the resistance values of the first and second resistors and the capacitance of the first capacitor, and resetting of the first time constant circuit An IC or the like with a reset terminal connected to the terminal connection terminal starts up with a further delay by that time constant. Thereafter, when the charging of the first capacitor is completed and the voltage level of the preceding stage becomes high level, no current flows through the first resistor and the diode. Then, next, the second capacitor is charged by the current flowing through the second resistor. At this time, the time constant of the second time constant circuit having such a configuration is determined by the resistance value of the second resistor and the capacitance of the second capacitor, and the reset terminal connection terminal of the second time constant circuit. The IC or the like to which the reset terminal is connected is activated with a delay corresponding to the time constant. On the other hand, when the reset request circuit makes a reset request, the reset terminal connection end of the first time constant circuit is pulled to a low level, and an IC or the like having the reset terminal connected to the reset terminal connection is reset. Then, the charge of the first capacitor is discharged. At the same time, the reset terminal connection end of the second time constant circuit is pulled to a low level via the diode to reset the IC or the like having the reset terminal connected to the reset terminal, and to reset the second terminal. The charge of the capacitor is discharged.

[0010]

[Effect of the invention]

 As described above, according to the present invention, a plurality of ICs and the like are activated with a time difference by using a difference in time constants of a plurality of time constant circuits, and at the same time, the reset terminal connection terminals of the respective ICs and the like are simultaneously set to a low level when a reset is requested. By pulling in, the capacitor of each time constant circuit is discharged while simultaneously resetting each IC etc., so that the time constant of each time constant circuit when the IC etc. starts up next changes. However, it is possible to provide a reset circuit which can always start each IC with a desired time difference.

Further, according to the invention of claim 2, a specific circuit configuration can be provided.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an electrical connection form of a main part of a CD player to which a reset circuit according to an embodiment of the present invention is applied. In FIG. 1, a system controller 10 controls various operations such as reproduction and stop of a CD based on an instruction from a remote controller or an operation panel (not shown), and a DSP 20 converts various types of digital signals read from the CD into digital signals. The DSP 20 is also provided with a servo IC such as a spindle servo or a feed servo.

The DSP 20 is connected to a power supply line from a predetermined power supply VDD and receives power supply. The power supply line is connected to a reset IC 30 and connected to resistors R1 and R2 which are in a parallel relationship with each other. ing. Capacitors C1 and C2 are connected in series with the respective resistors R1 and R2, and the connection end of the resistance R1 and the capacitor C1 is set to the cathode side, and the connection end of the resistance R2 and the capacitor C2 is set to the anode side. The diode D1 is bypass-connected, and the cathode side is connected to the open collector terminal 31 of the reset IC 30.

Each of the system controller 10 and the DSP 20 is provided with reset terminals 11 and 21. The reset terminals 11 and 21 are activated when the input level of the reset terminals 11 and 21 becomes high, and a predetermined reset process is performed when the input level of the reset terminals 11 and 21 becomes low. It is supposed to run. Here, the reset terminal 11 of the system controller 10 is connected to the cathode side of the diode D1, and the reset terminal 21 of the DSP 20 is connected to the anode side of the diode D1.

When the power supply is turned on and the voltage level of the power supply line goes high, a current flows through the resistors R1 and R2. The anode of the diode D1 is connected to the connection end of the resistor R2 and the capacitor C2. Therefore, the current flowing through the resistor R2 flows through the diode D1. Then, the capacitor C1 is charged by the current flowing through the resistors R1 and R2, and when the charging is completed, the voltage level on the cathode side of the diode D1 becomes a high level, and the capacitor 10 having the reset terminal 11 connected to the cathode side. Starts.

When the voltage level on the cathode side of the diode D1 becomes a high level, current no longer flows through the resistor R1, the capacitor C1, and the diode D1, and charging of the capacitor C2 is started by the current flowing through the resistor R2. When the charging of the capacitor C2 is completed, the voltage level on the anode side of the diode D1 becomes high level, and the DSP 20 having the anode connected to the reset terminal 21 is activated.

That is, as shown in the timing chart of FIG. 2, when the power is turned on and the power supply voltage goes to a high level, the voltage level on the cathode side of the diode D1 goes to a high level later than this, and Starts. At this time, the delay time T1 is determined by a time constant determined by the resistance values of the resistors R1 and R2 and the capacitance of the capacitor C1. Further, when the voltage level on the cathode side of the diode D1 becomes high level, the voltage level on the anode side of the diode D1 becomes high level later, and the DSP 20 is started. At this time, the delay time T2 is determined by a time constant determined by the resistance value of the resistor R2 and the capacitance of the capacitor C2, and the total delay time T3 from power-on is the sum of T1 and T2.

The reason for providing a time difference between the activation of the system controller 10 and the DSP 20 is as follows. As described above, the DSP 20 is provided with a servo IC such as a spindle servo or a feed servo, and it is known that it takes some time from power-on until the circuit is stabilized. Therefore, if the reset period is not sufficiently provided, it is considered that the device does not operate normally. Therefore, the time difference is provided as described above. Of course, how much delay time is provided can be set by the respective resistance values of the resistors R1 and R2 and the respective capacitances of the capacitors C1 and C2. Is selected in advance.

After turning on the power, the reset IC 30 monitors the power supply voltage, and can detect a voltage drop such as an instantaneous interruption. Upon detecting such a voltage drop, an input voltage is applied to an internal open collector circuit (not shown). Then, the voltage level on the cathode side of the diode D1 is immediately pulled down to the low level via the open collector terminal 31, the electric charge of the capacitor C1 is discharged, and the system capacitor 10 is reset. In addition, the voltage level on the anode side is also pulled down to a low level via the diode D1, thereby discharging the charge of the capacitor C2 and resetting the DSP 20.

That is, as shown in FIG. 2, when the reset IC 30 detects a drop in the power supply voltage, the voltage levels on the cathode side and the anode side of the diode D1 go low at substantially the same time, and accordingly, the system capacitor 10 and the The DSP 20 is reset at the same time. At this time, since the electric charge of the capacitor C2 is completely discharged through the diode D1, no electric charge remains. Next, when the system controller 10 is started as described above and the DSP 20 is started, a predetermined value is determined. There is no deviation in the set time constants, and they are always started with a fixed delay time.

As described above, in the present embodiment, the resistors R1 and R2 connected in parallel to the power supply line from the power supply VDD and the resistors R1 and R2 are connected in series to each other. Using the difference in the time constants of the capacitors C1 and C2, the system controller 10 and the DSP 20 are activated with a time difference. When the power supply voltage decreases, the reset IC 30 resets the reset terminal voltages of the system controller 10 and the DSP 20 via the diode D1. The electric charge of the capacitors C1 and C2 is discharged while being pulled to a low level. In this sense, the power supply VDD and the reset IC 30 constitute a reset request circuit in one body.

By the way, from the viewpoint that the system controller 10 and the DSP 20 are started with a time difference by using the difference of the time constants and that both are reset at the same time when a reset request is made, the circuit configuration shown in FIG. is there. The configuration shown in the figure is configured by replacing the diode D1 with a resistor R3 in the circuit configuration shown in FIG. That is, in such a configuration, the system controller 10 and the DSP 20 are activated with a time difference by a time constant difference determined by the resistance values of the resistors R1, R2, R3 and the capacitances of the capacitors C1, C2. Then, when a reset is requested by the reset IC 30, the reset terminal voltages of the system controller 10 and the DSP 20 are simultaneously pulled down to low level, resetting is performed, and the charges of the capacitors C1 and C2 are also discharged.

When the instantaneous interruption test was repeatedly attempted for such a circuit configuration, the time constant determined in advance by the resistance values of the resistors R1, R2, and R3 and the capacitances of the capacitors C1 and C2 showed a deviation. It has been found that the system controller 10 and the DSP 20 cannot be started with a predetermined time difference. This is because the electric charge of the capacitor C2 is discharged via the resistor R3, so that the electric charge of the capacitor C2 is not completely discharged, and a substantial time constant shift occurs at the next start-up. Therefore, in the present embodiment, the circuit configuration shown in FIG. 3 is not adopted. However, such a circuit configuration is also applicable if the reset period can be used practically even if a slight change occurs.

Next, the operation of the present embodiment configured as described above will be described. When the power is turned on and the voltage level of the power supply line (power supply VDD) becomes a high level, a current flows through the resistors R1 and R2, and the current flowing through the resistor R2 is bypassed by the diode D1. The charging of the capacitor C1 is started by the current flowing through the capacitor C1. When the charging of the capacitor C1 is completed, the voltage level on the cathode side of the diode D1 becomes high level, and the system controller 10 having the cathode connected to the reset terminal 11 is activated. At this time, the system controller 10 is activated with a delay of a time constant (T1) determined by the resistance values of the resistors R1 and R2 and the capacitance of the capacitor C1 when the power is turned on.

When the voltage level on the cathode side of the diode D1 becomes a high level, current no longer flows through the resistor R1, the capacitor C1, and the diode D1, and charging of the capacitor C2 is started by the current flowing through the resistor R2. When the charging of the capacitor C2 is completed, the voltage level on the anode side of the diode D1 becomes high level, and the DSP 20 having the anode connected to the reset terminal 21 is activated. At this time, the DSP 20 starts with a delay of a time constant (T2) determined by the resistance value of the resistor R2 and the capacitance of the capacitor C2 with respect to the start of the system controller 10.

Thereafter, when the reset IC 30 detects a voltage drop such as an instantaneous interruption, it supplies an input voltage to an internal open collector circuit (not shown). Then, the voltage level on the cathode side of the diode D1 is immediately pulled down to the low level via the open collector terminal 31, the electric charge of the capacitor C1 is discharged, and the system capacitor 10 is reset. At about the same time, the voltage level on the anode side is also pulled down to a low level via the diode D1, the electric charge of the capacitor C2 is discharged, and the DSP 20 is reset. At this time, since the electric charge of the capacitor C2 is completely discharged, the time constant applied to the capacitor C2 is constant even when the system controller 10 and the DSP 20 are started next, and the system controller 10 and the DSP 20 are started with the above time difference. Is done.

As described above, the resistors R1 and R2 are connected in parallel to the power supply line from the power supply VDD, and the capacitors C1 and C2 are connected in series to the respective power supply lines. The system controller 10 and the DSP 20 are activated with a time difference utilizing the difference between the two, and when the power supply voltage drops, the reset terminal voltage of the system controller 10 and the DSP 20 is pulled down to a low level via the diode D1 by the reset IC 30 to reset simultaneously. In addition, since the charges of the capacitors C1 and C2 are discharged, the charge of the capacitor C2 is completely discharged at the time of reset, and the time constant is always constant. And start each with a desired reset period. It is possible to provide a capability reset circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical connection configuration of a main part of a CD player to which a reset circuit according to an embodiment of the present invention is applied.

FIG. 2 is a timing chart showing a relationship between a predetermined power supply voltage and voltage levels on a cathode side and an anode side of a diode in the CD player.

FIG. 3 is a block diagram illustrating an electrical connection configuration of a main part of a CD player to which a reset circuit according to a modification is applied.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 system controller 11 reset terminal 20 DSP (digital signal processor) 21 reset terminal 30 reset IC 31 open collector terminal VDD power supply R1, R2 resistor C1, C2 capacitor D1 diode

Claims (2)

[Utility model registration claims] 1. A plurality of time constant circuits connected to a predetermined signal transmission line and having a predetermined capacitor and having different time constants from each other; A plurality of reset terminal connection terminals which are branched from an electric line and are connected to reset terminals such as ICs; a high-level signal is output to the signal transmission line when the IC etc. is activated; And a reset request circuit for simultaneously pulling the voltage level of each of the plurality of low-level circuits to a low level to discharge the charge of each capacitor in the plurality of time constant circuits. 2. The reset circuit according to claim 1, wherein said plurality of time constant circuits comprise first and second time constant circuits, and wherein said first time constant circuit comprises: A first and a second resistor connected in parallel to each other with respect to the transmission line; a diode connected to the rear side of the first resistor as a cathode and connected to the rear side of the second resistor as an anode; A first capacitor connected in series to the first resistor, and the second time constant circuit is connected in series to the second resistor and the second resistor. A second capacitor, wherein the reset request circuit pulls a voltage level on a preceding stage of the first capacitor to a low level at the time of a reset request, thereby setting the voltage level before the second capacitor via the diode. Reset circuit, characterized by drawing the voltage level of the side to a low level.