JP3050901B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (DRAM) using a memory cell composed of one transistor and one capacitor.

(Prior Art) Among MOS semiconductor memories, a dynamic RAM (DRAM) having one transistor and one capacitor has been most highly integrated. Recent DRAMs are equipped with high-speed access modes such as a page mode, a nibble mode, and a static column mode, in addition to a normal access mode. On the other hand, there is also a strong demand from the field of image processing or the field of computer systems using a cache memory for serial access that can access one row of data at high speed and serially.

The conventional page mode is a mode in which a selected row of data can be accessed randomly and at high speed. By serially giving an address from the outside using this page mode, serial access can be performed in which one row of data is accessed serially at high speed. However, in serial access using this page mode, the column address must be fetched from the outside each time in response to the toggle of ▲ ▼, so there is a limit in speed.

On the other hand, nibble and
There is a mode. FIGS. 13 and 14 show timing charts of a read cycle and a write cycle in the nibble mode, respectively. The nibble mode is similar to the page mode described above in that high-speed access of consecutive bits in the column direction is performed only by the toggle of ▼. However, in nibble mode, ▲
From the second cycle onward, the fetch of the column address is not required. In this regard, nibble mode is generally faster than page mode, which is a major advantage.

However, the nibble mode has the greatest difficulty in that the number of bits that can be accessed is limited, and cannot be applied to serial access. The number of bits that can be accessed is limited for the following reasons. In the nibble mode, a plurality of data are collectively sent to the data latch register in the first cycle of ▲, and from there, ▲
High-speed access is realized by sequentially transferring data to the output port by the toggle of ▼. Therefore, the number of data latch registers is limited to the number of bits that can be accessed. Number of registers and 1
If the number of rows of data is the same, one row of data can be accessed serially at high speed, but 4-bit nibbles are now common, mainly due to chip area constraints.

Next, the problem when the nibble mode is applied to the serial access mode will be specifically described with reference to FIG. FIG. 15 is a timing chart at the time of reading when serial access is performed using the nibble mode.
In the figure, CSLi (i = 0, 1,...) Represents a column selection line which is determined and activated by a column address, and QSE is a sense of a data latch register which is an intermediate buffer connected to an input / output data line. Represents a signal. In the nibble mode, a plurality of data are transferred to a data latch register by selecting one column selection line, and a sensing operation is performed here. Its bit length is the same as the accessible bits in nibble mode. The figure shows that 4-bit data is transferred by one column selection line CSL. Therefore, assuming that a column address counter is built in on-chip and serial access is realized by sequentially increasing the internal address, as shown in FIG. 15, 4n + 1 (n = 1, 2,...) In the cycle of ▼, it is necessary to switch the column selection line and activate the sense signal QSE in the data latch register. Therefore, the access in the 4n + 1th cycle
The time becomes longer as compared with other cycles as shown in the figure. Generally, the extended access time is about twice that of other cycles. This is a major obstacle in achieving uninterrupted high-speed serial access.

By the way, in general-purpose DRAMs, it is common to mount redundant bits for the purpose of improving the yield by relieving a defective bit such as a single bit defect. A spare column decoder for controlling selection / non-selection of a redundant column is also mounted in the column direction. In this case, the address of the defective column is stored in the chip as fuse data, and when a defective column address is selected, it is replaced with a spare column selection line. Will be long.

(Problems to be Solved by the Invention) As described above, in the conventional DRAM, if the serial access mode for serially accessing one row of data at a high speed is to be realized by the application of the nibble mode, the column address is increased. There is a problem that a waste occurs at the time of switching between the devices and that continuous high-speed serial access cannot be performed.

An object of the present invention is to provide a semiconductor memory device which solves such a problem and realizes high-speed and continuous serial access.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device according to the present invention comprises: a memory cell array in which a plurality of memory cells are arranged; an address buffer for receiving an external address; A row decoder for selecting a row of the memory cell array based on the input row address; and a column selection for the memory cell based on a column address captured by the address buffer, and raising a selected column selection line. A column decoder having a function of starting up a column selection line to be selected by the next column address before the arrival of the column address; and a column address and a defective column taken in by the address buffer.・ Defective column from fuse data for redundant column indicating address A spare column having a function of starting a spare column selection line corresponding to a defective column address before the arrival of the defective column address by using the system address and the address immediately before the defective column address. A decoder, and a sense amplifier for exchanging data with a memory cell selected by the row decoder and the column decoder or the spare column decoder.

(Operation) According to the present invention, when a column selection line determined by a column address rises, the column selection line to be selected by the next column address is changed to the column selection line.
It is started up before the arrival of the address. In other words, in the present invention, the column decoder has a look ahead function. Then, the data to be selected by the next address is already transferred to the data register by the previously selected column selection line before the arrival of the address. This eliminates the conventional time loss at the time of column address switching, and realizes uninterrupted high-speed serial access.

Further, according to the present invention, the address immediately before the defective column is also generated in the chip using, for example, a subtractor that receives the address of the defective column, so that the spare data is output by the address data of the subtracter. By performing a look-ahead operation on the spare column selection line of the column decoder, even in a system with redundant columns,
An uninterrupted serial access mode can be realized.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a column decoder and a spare column decoder section in a DRAM having a redundant circuit system according to an embodiment of the present invention. The configuration is shown. FIG. 2 is a diagram showing the entire configuration of the DRAM, and FIG. 3 is a diagram showing a specific configuration from the memory cell array to the data output unit.

As shown in FIG. 2, the DRAM of this embodiment comprises a row address buffer 1, a column address buffer 2 for taking in an external address, clock generators 3 and 4 for driving these address buffers 1 and 2, A column decoder 5 and a row decoder 6 for decoding a fetched address, a memory cell array 7 in which a 1-transistor / 1-capacitor dynamic memory cell driven by these decoder outputs is arranged, and data is exchanged with the memory cell array 7. Amplifier and input / output (I / O)
It has a gate 8, an input / output buffer 9 for latching input / output data, a substrate bias generation circuit 10, and a refresh counter 11 for self-refreshing the memory cell array. In this embodiment, in addition to these, a serial address counter 12 for generating a serial address in the column direction is incorporated. This serial address counter 12 counts in response to the
The output is input to the column address buffer 2. The output of serial address counter 12 is column
The data may be directly input to the output unit instead of the input unit of the address buffer 2.

Although not shown, the memory cell array 7 has a spare column selection line of a redundant column in addition to the column selection line, and a spare column selection line adjacent to the column decoder 5 for selecting the spare column selection line. There is a decoder 18. A fuse 13 for a redundant column controlled by an address of a defective column, a fuse data register 14 for holding the fuse data in a chip, a fuse data register 14 and an output of a column address buffer 2 are used. , Column selection circuit / spare column selection circuit 17
The column decoder 5 and the spare column decoder 18 controlled thereby select the memory cell array 7 in the column direction. Further, in this embodiment, in order to provide the spare column decoder 18 with a look-ahead function, the output line of the fuse data register 14 is used as an input, and the subtractor 15 and the output data of the subtracter 15 are held in the chip. The fuse data register 16 is built-in, and the fuse data register 16
The output of the column selection circuit and spare column selection circuit 17
Has been entered.

In this way, the address data of the defective column (fuse
Using a subtracter 15 to which the input of the data register 14 is input, an address immediately before the defective column is also generated and held in the chip (the fuse data register).
16 outputs), the spare column selection line can also perform a look-ahead operation. As will be described in detail later, if the spare column select line is activated when the address held in the fuse data register 16 matches the chip internal address of the serial counter output,
Look ahead.

As is well known, the memory cell array 7 includes a plurality of word lines and bit line pairs intersecting each other, and a memory cell is arranged at the intersection. In FIG. 3, one word line WL of such a memory cell array 7 and a memory cell MC arranged along the word line WL, and a plurality of bit line pairs BL and BL for exchanging data with these memory cells MC are shown.
▲ ▼ is shown. In particular, here, the column selection line CSL selected by the column decoder 5 and the spare
The portion of the spare column select line SCL selected by the column decoder 18 is shown. Further, in this embodiment, as shown in FIG. 3, four pairs of I / O data lines 21 of DQ0, 〜 to DQ3, 配 are provided. I / O data line 21
The data latch registers 22 (221 to 224) provided corresponding to the respective I / O data lines 21 as corresponding to the input / output buffer 9 in FIG. It has a multiplexer 23 for sequentially selecting an output, and a data output buffer 24 connected to an external output terminal. Column selection line selected by column decoder 5
The spare column select line SCSL selected by the CSL and the spare column decoder 18 is branched into two lines, respectively, and I / Os corresponding to two pairs of adjacent bit lines
The O gate 8 is driven at the same time. That is, two bit line pairs selected by one column selection line CSLn are connected to the first and second I / O data line pairs DQ0, ▲ and DQ1, ▲, respectively, and the next column selection is performed. The next two bit line pairs selected by the line CSLn + 1 are connected to the third and fourth I / O data line pairs DQ2, ▲ and DQ3, ▼, respectively. When the spare column select line SCSL1 is selected corresponding to the defective column, the two bit line pairs selected by this select the first and second I / O data line pairs DQ0, ▲ ▼ and DQ1, ▲, respectively. Connected to ▼,
Similarly, when the spare column selection line SCSL0 is selected, the next two bit line pairs selected by the selection are respectively
Third and fourth I / O data line pairs DQ2, ▲ ▼ and D
Q3, connected to ▲ ▼.

The column decoder 5 has a look-ahead function of simultaneously selecting not only the column selection line determined by the address of the own cycle but also the column selection line selected by the next address. Spare column decoder
Similarly, the subtracter 15 and the fuse data register 16
Has a look-ahead function that is activated before a defective column held as fuse data is selected. FIG. 1 shows a configuration example of such a column decoder 5 and a spare column decoder 18. The column decoder 5 includes a plurality of NAs for decoding column addresses similar to those in a normal decoder.
In addition to the address decoding section composed of the ND gates G1 (G11, G12, G13,...), A plurality of 2-input NAND gates G2 (G21, G22, G23,...) Provided at the output section of the address decoding section.
And a column selection line driving unit composed of Each of the NAND gates G2 of the column selection line driving unit has one of two input terminals connected to the output terminal of the corresponding NAND gate G1 of the address decoding unit, and the other input terminal connected to the previous column address. The output terminal of the address decode unit corresponding to the branch is connected in a branched manner. Signal lines indicated by bold lines in FIG.
▼ is a so-called look ahead signal line. The spare column decoder 18 has an inverter I and a spare column selection line driving unit including a two-input NAND gate G3 provided at an output unit thereof. The spare column selection line driving unit is also connected to the output terminal of the inverter I corresponding to one of the two input terminals, and to the other input terminal.
The output terminal of the address decoding unit corresponding to the address is branched and connected. That is, ▲ is a look ahead signal line.

Column decoder 5 and spare column decoder
In 18, not only the selection / non-selection is determined by the column addresses Y 0 to Ym, but also the operation state is controlled by the two output signal lines EVEND and ODDD of the column selection circuit / spare column selection circuit 17. In this case, it is assumed that two columns including a defective column are replaced with a spare column. The signal EVEND is normally at “L” level, but the even-numbered column selection line CSL is spared. When the column selection line SCSL0 is replaced, the signal ODDD becomes “H” level. When the odd-numbered column selection line CSL is replaced with the spare column selection line SCSL1, the signal ODDD becomes “H” level. In this way, depending on the outputs EVEND and ODDD of the column selection circuit / spare column selection circuit 17, whether the output of the decoding unit of the column decoder 5 is output to the column selection line CSL or the spare column selection line SCSL is output. The selection is made by the gate circuit at the driver output stage of FIG.

The most significant feature of the column decoder 5 and the spare column decoder 18 in this embodiment is that the output signals EVEND and ODDD of the column selection circuit / spare column selection circuit 17 are close to the output stage of the column selection line, not the address decoding unit. This is at the point input to the column selection line driving unit. Thus, even when a spare column is selected, the selection line of the defective column can be deselected while the look-ahead signal in the column decoder is activated. Thus, in the spare column selection cycle, the look-ahead signal generated by the address decoding unit of the defective column as in the normal column selection cycle.
By ▼, a column selection line to be selected in the next cycle can be set to a selected state.

Next, specific operations of the column decoder and the spare column decoder will be described.

First, the operation of the column decoder 5 shown in FIG. 1 will be described without considering a redundant circuit. In the address decoding section, the output terminal of one of the NAND gates G1 goes to "L" level in order to select one column selection line according to the input column address. Now, for example, it is assumed that the output terminal of the NAND gate G11 has become “L” level. Then, the "L" level of this output goes to one input terminal of the corresponding NAND gate G21 of the column selection line driving unit, and at the same time, the look ahead signal line
Through to one input terminal of the next KNAND gate G22.
As a result, the output terminals of the two NAND gates G21 and G22 become “H” level, and the column selection line CSLn-2 corresponding to the input column address and the column selection line corresponding to the next column address simultaneously CSLn-1 will be selected. When the next column address is input, the output of the NAND gate G11 returns to the “H” level in the address decoding unit, and the output terminal of the next NAND gate G12 goes to the “L” level. As a result, the NAND gate G2
The output of 1, that is, the column selection line CSLn-2 returns to "L" level. At this time, the NAND gate G2 corresponding to the selected address
In 2, since one input returns to "H" level and the other input goes to "L" level, its output, that is, the column select line CSLn-1 is kept at "H" level. Also, at this time, one input terminal of the next NAND gate G23 goes to the “L” level through the look-ahead signal line ▲ ▼, so that the column selection line CSLn to be selected by the next column address becomes “L”. H "level. In the same manner, the column selection lines are started in advance before their own column addresses arrive, and the selection that the two column selection lines always go to the “H” level is sequentially performed.

FIG. 4 is an operation timing chart of a read cycle in the serial access mode by the DRAM of this embodiment. Row address strobe signal ▲ ▼ is “L”
Level, and enters an active cycle to take in a row address. In the first cycle of the column address strobe signal ▼ (the first toggle in ▼), the column selection line CSL0 determined by the column address and the column determined by the column address one bit ahead of that address. Two selection lines CSL1 rise at the same time. As a result, 4-bit data is read out and transferred to the data latch register 22 via the I / O data line 21. Then, at the rising edge A1 of the sense activation signal QSE, the transferred 4-bit data is latched. This 4-bit data is referred to as ▲ ▼
Are sequentially transferred to the output terminal via the multiplexer 23 and output to the outside. At the end of the second cycle of ▲ ▼, the serial address counter 13
Increments the column address. At this time, the internal column address should be in a state of selecting the column selection line CSL1, but within the chip, the column selection line CSL1 is already selected by the look-ahead function of the column decoder 5 described above. Being “L”
Level. Then, at the same time that the next column selection line CSL2 is selected, the first column selection line CSL0 is not selected. As a result, new 2-bit data is read out to the I / O line 21 and transferred to the data latch register 22.
This data is sensed and latched at the second rising edge A2 of the sense activation signal QSE.

Similarly, the nibble mode is applied in a state where a column selection line is newly selected every two cycles of ▲ ▼ according to the increment of the internal column address and two column selection lines are always selected. Data reading in the serial access mode is performed. According to this embodiment, there is no longer an extended access during column address switching as in the prior art, and continuous serial access is possible. Note that the column selection line has been selected in advance, but remains selected until the end of its own cycle. Therefore, although detailed description is omitted, this method can be similarly used in the read / write cycle mode.

FIG. 5 is a timing chart for explaining operations of a column decoder and a spare column decoder in consideration of a redundant circuit. FIG. 5 shows a case where defective columns CSLn and CSLn + 1 are replaced with spare columns SCSL0 and SCSL1, respectively. Further, a case is shown in which 2-bit cell data is selected by one column selection line CSL or spare column selection line SCSL. Therefore, the bits connected to the spare column select line SCSL0 in the fifth and sixth cycles of ▼ are changed to the spare column select line in the seventh and eighth cycles of ▼
The bit connected to SCSL1 will be selected. The operation will be described below using this timing chart. ▲
In the first cycle of ▼, as described above, two columns of the column selection line CSLn-2 determined by the column address and the column selection line CSLn-1 determined by the address one ahead of the address representing the current cycle. Stand up at the same time. Thereby, 4-bit data is transferred to the data latch register and sensed and latched. ▲ ▼
With the end of the second cycle, the chip internal address is incremented by the column address counter mounted inside the chip. The figure shows the lowest column address Y0
Is incremented and the state transits from the “L” level to the “H” level. At this timing, the output of the subtracter 15, that is, the address of the fuse data register 16 and the internal address become equal. This means that the next increment of the column address counter makes the fuse data register 14, which is the address of the defective column, equal to the internal address. Therefore, the look-ahead operation of the spare column selection line SCSL0 must be started at this timing. Therefore, out of the two output lines of the column selection circuit / spare column selection circuit 17, only EVEND transitions from "L" level to "H" level. At the end of the fourth cycle of ▼, the column address counter is incremented again, and the internal address becomes equal to the fuse data register 14 which is the address of the defective column. At this timing, ODDD is also “L”
Transition from level to “H” level, spare column select line
SCSL1 also looks ahead. Further, in the increment of the column address counter synchronized at the end of the sixth cycle of ▲ ▼, EVEND changes from “H” level to “L”.
Level, the spare column select line SC
SL0 becomes unselected, and at the same time, the column selection line CSLn + 2 looks ahead. In the increment of the column address counter synchronized at the end of the eighth cycle of ▲ ▼, ODDD also changes from “H” level to “L” level, the spare column selection line SCSL1 is not selected and the column selection line C
SLn + 3 looks ahead. Thus, the spare column selection cycle is completed, and thereafter, the look-ahead operation is repeated only in the column decoder section.

FIG. 6 shows an example of a specific circuit of the column selection circuit spare column selection circuit 17 for obtaining the control signals EVEND and ODDD as described above. The input signal Yφ means the lowest address of the column address. In addition, the input signal ▲
▼ is an output signal from the comparator of the fuse data register 14 and the chip internal address (column address counter output). When all of the two addresses except for the lowest Yφ match, “一致” is output. This is a signal which becomes "L" level and becomes "H" level otherwise. Also, input signal ▲
▼ is an output signal from the comparator of the fuse data register 16 and the internal address of the chip, which is "L" level when all two addresses except the lowest Yφ match, and "H" otherwise. "This is a level signal.

FIG. 7 is a timing chart for explaining the operation of the circuit shown in FIG. ODDD is the reverse phase signal of ▲ ▼, while EVEND takes the logic that satisfies the following conditions. Ie Becomes Thus, the column selection circuit / spare column selection circuit shown in FIG. 6 is used, and its output lines EVEND, ODDD
Is input to the column decoder / spare column decoder shown in FIG. 1 so that the spare column selection line can also have a look-ahead function.

FIG. 8 shows the fuse data register 14 described above.
2 shows an example of a circuit of a comparator for the address of the chip and the internal address of the chip. The detection of the match / mismatch between the fuse data and the internal address is made by connecting two NMOS transistors, each of which has its gate input, in series.
This can be done by connecting to d-or type.

As a result, ▲ ▼ and ▲ ▼ are “L” only when all fuse data and internal address match.
Level, otherwise the level is "H". In addition, the PMOS transistor, Q1,
Q2 is a transistor for charging nodes A and B, and Q3 and Q4 are transistors for preventing nodes A and B from floating.

FIG. 9 is a circuit diagram showing an example of the subtractor 15 which is a point of the present embodiment. The input signal CFSi (i = 0 to m) is the address of the fuse data register 14. The address subtracted from this address, that is, the address CFPi of the fuse data register 16, is generated. CCi is a carry of the subtractor 15 and controls carry down.

A predetermined number of circuits shown in FIG.
By connecting CCi, a subtractor having an arbitrary bit length can be made.

FIG. 10 is a main block diagram of a column system of a DRAM according to another embodiment of the present invention. The same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description is omitted. The difference from FIG. 2 lies in that a fuse 19 for a redundant column is added instead of the subtractor 15.

The redundant column fuse 19 cuts the fuse so that the address data decremented by one from the address data of the defective column is transferred to the fuse data register 16, thereby performing the same operation as the subtractor 15 in FIG. Can be done.

In addition, the simplest example as shown in each drawing is shown for the column decoder, spare column decoder, and column selection circuit / spare column selection circuit, which are the minimum necessary components of the present invention. Modifications can be freely made without departing from the purpose of the original circuit by evolving from the specific example shown here.

By the way, an image-only memory having a pointer function has been developed. The pointer function is a so-called cueing function that enables serial access from an arbitrary address to a column address. Such a function is extremely useful, for example, in facilitating horizontal dot scrolling in an image memory. Therefore, by adding this function to a general-purpose DRAM capable of serial access mode, high value-added DRAM
Can be obtained.

FIG. 11 shows the configuration of the column decoder section of the DRAM according to the embodiment to which such a pointer function is added, corresponding to FIG. The difference from FIG. 1 is that the output line of the address decode unit for the column selection line CSL2n (▲
▼) is used as a look-ahead signal line ▲ ▼ for the column selection line CSL0.

As a result, as indicated by the arrow in FIG. 11, the column selection line CSL0 is selected after the column selection line CSL2n, and as a result, the pointer function is obtained.

In the configuration of FIG. 11, the selection of the column selection line moves sequentially from the top to the bottom on the drawing. Therefore, the look ahead signal line for the uppermost column selection line CSL0 is extremely longer than the other rec ahead signal lines. This causes the look-ahead operation of the column selection line CSL0 to be extremely delayed due to wiring delay. This may lead to a reduction in the operating margin.

FIG. 12 shows a column decoder according to an embodiment in which the configuration of FIG. 11 is modified in consideration of such a problem. In this embodiment, the physical order of access of the column selection lines is changed as indicated by the arrow in the figure. That is, as the look ahead signal lines, a downward one and an upward one are prepared, and these are arranged alternately. In other words, the column selection line is CS
L0, CSL2n, CSL1, CSL2n-1, CSL2,... In other words, the column selection line corresponding to the one-bit increment from the physical lowest address and the column selection line corresponding to the one-bit decrement from the highest address are alternately and arranged in a line. .

With such a configuration, the lengths of all the look-ahead signal lines are equal, and it is possible to prevent a decrease in the operation margin due to the above-described wiring delay.

Further, in the embodiments of the present invention, the description has been made centering on the general-purpose DRAM. However, the image-only memory having the dynamic memory cell is, of course, a static memory (SRAM) having a serial access mode or a nonvolatile memory ( EPROM) can also be applied.

[Effects of the Invention] As described above, according to the present invention, a redundant circuit can be mounted in a serial access mode having a look-ahead function on a column selection line. In particular, according to the present invention, even if a redundant bit is selected, the access speed does not decrease, so that it is possible to greatly improve the yield of a general-purpose DRAM having a high added value called a serial access mode.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a column decoder and a spare column decoder section in a DRAM according to an embodiment of the present invention, FIG. 2 is a block diagram showing an entire configuration of the DRAM of the embodiment, and FIG. FIG. 4 is a timing chart for explaining the operation of the DRAM, FIG. 5 is a timing chart for explaining the operation of a column decoder and a spare column decoder, and FIG. FIG. 7 is an equivalent circuit diagram of a column selection circuit / spare column selection circuit. FIG. 7 is a timing diagram for explaining the operation. FIG. 8 is an equivalent circuit diagram of a comparator for comparing fuse data with an internal address. 9 is an equivalent circuit diagram of a subtractor, FIG. 10 is a diagram showing a configuration of a column system of a DRAM of another embodiment, FIG. 11 is a diagram showing a configuration of a column decoder of still another embodiment, FIG. The diagram shows yet another implementation FIG. 13 is a diagram showing a configuration of an example column decoder, FIG. 13 is a timing diagram for explaining a conventional nibble mode read cycle, FIG. 14 is a timing diagram for similarly explaining a nibble mode write cycle, FIG. 15 is a timing chart for explaining a problem when the serial access mode is realized by applying the nibble mode. 1... Row address buffer, 2... Column address buffer, 3... ▲ ▼ system clock generator, 4.
5 column decoder, 6 row decoder, yam memory cell array, 8 sense amplifier / I / O gate, 9 input / output buffer, 10 substrate bias circuit,
11 ... Refresh counter, 12 ... Serial counter, 13 ... Fuse for redundant column, 14 ... Fuse
Data register, 15 Subtractor, 16 Fuse data register, 17 Column selection circuit / spare column selection circuit, 18 Spare column decoder, 19
Fuse for redundant column.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/407

Claims (6)

(57) [Claims] A memory cell array in which a plurality of memory cells are arranged; an address buffer for receiving an external address; and a row decoder for selecting a row of the memory cell array based on a row address fetched by the address buffer. And selecting a column of the memory cell according to the column address taken in by the address buffer, raising a selected column selection line, and setting a column selection line to be selected by the next column address to the column. A column with a function to start up before an address arrives
A decoder, a column address fetched by the address buffer, a defective column address from the redundant column fuse data, and a spare column corresponding to the defective column address by an address immediately before the defective column address. A spare column decoder having a function of starting up a selection line before the arrival of a defective column address, and a memory cell and data selected by these row decoder and column decoder or spare column decoder And a sense amplifier for exchanging data. 2. A memory cell array having a plurality of pairs of word lines and bit lines arranged crossing each other, and a dynamic memory cell disposed at each crossing position thereof, and A plurality of sense amplifiers and input / output gates respectively provided; a plurality of pairs of input / output data lines selectively connected to the bit line pair via the sense amplifiers and the input / output gates; A plurality of data latch registers provided for each of the lines, an address buffer for taking in an external address, a row decoder for selecting a row of the memory cell array based on a row address taken in by the address buffer, The column selection of the memory cell array is performed by the column address taken by the address buffer. A column having a function of starting up a selected column selection line for driving the input / output gate and starting up a column selection line to be selected by the next column address before the arrival of the column address. A decoder, and a spare column corresponding to the defective column address by the column address fetched by the address buffer, the defective column address from the redundant column fuse data, and the address immediately before the defective column address. A spare column decoder having a function of starting up a column selection line before the arrival of a defective column address; and a spare column decoder. 3. A memory cell array having a plurality of pairs of word lines and bit lines arranged crossing each other, and a dynamic memory cell arranged at each crossing position between the word lines and bit lines. A plurality of sense amplifiers and input / output gates respectively provided; a plurality of pairs of input / output data lines selectively connected to the bit line pair via the sense amplifiers and the input / output gates; A plurality of data latch registers provided for each line, an address buffer for taking in an external address, and an internal column address which is counted up by a column address strobe signal and sequentially generates an internal column address for serial access The address counter and the row address captured by the address buffer A row decoder for selecting a row of the memory cell array; and a selection for selecting a column of the memory cell array based on a column address fetched by the address buffer or output from the address counter, and driving the input / output gate. A column decoder having a function of starting up the selected column selection line and starting up a column selection line to be selected by the next column address before the arrival of the column address; The spare column selection line corresponding to the defective column address is determined by the defective column address from the redundant column fuse data indicating the defective column address and the defective column address and the address immediately before the defective column address. Before the arrival of the bad column address And a spare column decoder having a function of starting and starting up. 4. The function of previously activating a spare column selection line is realized by holding a defective column address and a column address immediately before the defective column address in a chip. 3. The semiconductor memory device according to any one of 3. 5. The semiconductor memory according to claim 4, wherein a column address immediately before said defective column address is generated from a defective column address held in a fuse by using a subtractor. apparatus. 6. The semiconductor memory device according to claim 4, wherein said defective column address and a column address immediately before said defective column address are held in a fuse, respectively.