JP3049837B2 - Semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device effective for use in a high-frequency pulse power supply.

[0002]

2. Description of the Related Art As a power source of various lasers such as a copper vapor laser and an excimer laser, a current of several kA is discharged at a frequency of several kHz from a capacitor charged to several tens kV with a pulse width of several hundred ns. There is a need for a switch that can do this. At present, an electron tube such as a thyratron is used for this switch, but its life is as short as about 10 ⁸ shots. In order to extend the life of the switch, research on solidifying the switch (making it a semiconductor) is being conducted.

In this research, thyristors, GTO, S
I thyristors, IGBTs, MAGTs, MOSFETs and the like are used. These semiconductor elements are desired to have high withstand current rise rate at turn-on, short turn-on time, low turn-on energy, high withstand voltage, and the like. Here breakdown voltage, N serves as a current path of the device ^- so obtained by widening the depletion layer in the layer, in order of the high breakdown voltage generally N ^-
The layers need to be thick. However, turn-on energy, N ^- from increasing when the thickness of the layer exponential relationship to, N ^- has to be high withstand voltage without increasing as possible layers. To solve this, currently N ^- anode layer (collector, drain) side N ^- is provided with a high N ⁺ buffer layer impurity concentration than the layer. Since stopping the spread of the depletion layer extending to the layer, N ^{- -} The N ⁺ buffer layer N may high breakdown voltage without increasing the thickness of the layer.

[0004]

SUMMARY OF THE INVENTION Thyristors, GTOs, SI thyristors, IGBTs, MAGs of the aforementioned semiconductor devices
T utilizes conductivity modulation to carry large currents. Therefore, a P ⁺ layer is formed on the anode (collector, drain) of the device. The injection efficiency in the P ⁺ layer is P ⁺
It becomes worse as the impurity concentration of the N layer forming a junction with the layer is higher.

Since the N ⁺ buffer layer forms a junction with the P ⁺ layer, the injection efficiency is reduced and the turn-on characteristics are deteriorated as compared with the junction with the N ^- layer.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a high-performance semiconductor device which solves the above-mentioned conventional problems.

[0007]

According to the present invention, in order to achieve the above object, the N base region of a semiconductor body is formed with a low concentration of I.
Formed by an (N ⁻ ) base and a high concentration of N ⁺ buffer,
The N ⁺ buffer, a depletion layer caused by the turn-on voltage exceeds the peak value of the N ⁺ buffer layer, and the N ⁺
The thickness of the depletion layer extending in the N ⁺ buffer from the thickness of the buffer layer
The distance obtained by subtracting only the length is longer than the diffusion length from the adjacent P emitter layer.

[0008]

According to the present invention, a semiconductor switch that can be turned on from a very high voltage in a very short time can be realized. Since a short turn-on time means a short time during which the current flowing through the element is suppressed, a high anode current increase rate and low turn-on energy can be achieved. Further, since the switch is a solid-state switch, the life can be extended as compared with a conventional thyratron.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a gate turn-off thyristor (hereinafter abbreviated as GTO) embodying the present invention, and FIG. 1 is a sectional view thereof.

As shown in FIG. 1, a semiconductor body 1 has an N base 2, a P emitter layer 3, a P base layer 4, an N emitter layer 5 formed in the P base layer 4, and a high concentration P ⁺ layer. The N base 2 is formed by an I base layer 2a, which is a low concentration N layer, and an N ⁺ buffer layer 2b having a relatively high concentration. Further, an anode electrode A is formed on the P emitter layer 3, a cathode electrode K is formed on the N emitter 5, and a gate electrode G is formed on the P ⁺ layer 6.

That is, as shown in FIG. 2, the impurity concentration of the P base is also made lower than that of the normal GTO for optimization, and the gate current is made uniform and the gate electrode is made uniform around the cathode and immediately below the gate electrode. , A high-concentration P layer is formed. Also, the N base is replaced with a low concentration of N
A PIN structure formed of an I base as a layer and a relatively high concentration of N buffer was employed. This is to suppress an increase in the thickness of the N base due to an increase in breakdown voltage of the element. To form the N buffer, a diffusion and epitaxy using a combination of a diffusion technique and an epitaxial technique is used.
alBuffur) process. By this process, an N buffer having a gentle concentration gradient in both directions on the I base side and the P emitter side in a short time is formed. The dotted line in FIG. 2 indicates the impurity concentration of the conventional N ⁺ buffer layer. The I base corresponds to a conventional N ^- layer, and the P emitter corresponds to a conventional P ⁺ layer.

In the semiconductor device having the above-described structure, a design is made such that the end of the depletion layer which spreads at a specified turn-on voltage exceeds the peak value of the N ⁺ buffer layer 2b, and the breakdown voltage due to the diffusion length of the P emitter layer 3 does not decrease. . A turn-on test is performed on the semiconductor device thus designed using a circuit as shown in FIG .

FIG. 3 shows a turn-on measurement circuit.
The turn-on voltage V _D is the voltage charged from the power source E to the capacitor C, and the anode current rise rate d is the inductance L.
When i / dt resonates under the condition of the resistance LR, a freewheel diode FWD is connected in antiparallel with the element so that no reverse bias is applied to the element. Furthermore, since the element prototyped this time is designed on the assumption that unlike a normal GTO thyristor, almost no turn-off capability is required, a high resistance R is provided between the power supply E and the capacitor C, and the ON period is sufficiently long. It is made long so that only a current of about several A is turned off.

Using this circuit, extremely high di / dt
In order to perform high-speed pulse energization that turns on at
It is necessary to minimize the inductance of the R-element- (L) -C path. For example, in order to turn on di / dt at 12 kA / μs from 3 kV, it must be 0.25 μH including the internal impedance of the device. To realize this, a high-speed pulse energization test was performed. FIG. 4 shows the results of this energization test.

[0016] That is, FIG. 4 shows the turn-on characteristics, I _G is the gate current, V _A is the anode voltage of the device, I
_A is the anode current. Also, I _GM 4 is a time until the peak gate current, I _P is anodic peak current, V _D is the anode peak voltage, t _gt anode voltage is turned time V _A = 0.1V _D.

There is a turn-on time in the turn-on characteristics, and the relationship between the turn-on time and the turn-on voltage is as shown in FIG. 5 when the constant of the circuit is fixed. Since it turns on from a high voltage, an inductance L was inserted in the measurement circuit to suppress di / dt. Anodic peak current value in accordance with the anode peak voltage is increased is increased substantially linearly, V _D in the difference in the inductance L can be seen the higher tends to increase. On the other hand, di / dt is V
It rises at a gentle slope until _D reaches a predetermined value, but it rises sharply from here. The effect of L is also
While V _D was hardly seen up to the specified value,
Beyond this becomes noticeable. This is presumably because when V _D is equal to or less than the predetermined value, the internal impedance of the element becomes dominant over the inductance of the circuit until the anode current increases to at least half of the peak value, thereby suppressing the anode current. Conversely, when the value is equal to or more than the predetermined value, the influence of the internal impedance of the element decreases, and the value approaches di / dt due to the inductance of the circuit.
It is considered that the difference of / dt has become remarkable. As for the turn-on energy E _ON , the behavior changes when V _D has increased to about a predetermined value, but when the V _D exceeds the predetermined value. This is also di / dt
Similarly, we consider whether not to influence the internal impedance of the element is decreased rapidly as the boundary a predetermined value of V _D. The turn-on time t _gt is rapidly reduced until V _D reaches the lower limit value, is very slow from this value to a predetermined value, and is further reduced rapidly beyond that value. This tendency does not change even if L changes. The depletion layer formed between the P base and the I base of this device is N
Since reaching the buffer, the turn-on time is considered to be related to the impurity distribution of the I base-N buffer and the depletion layer formed there. The delay time was very short because the anode voltage waveform at the time of turn-on had a phenomenon that the voltage temporarily decreased momentarily after the gate current was input.

[0018] That is, in FIG. 5 (1) (2) while the anode current is suppressed to the extent that a half of the peak value is between, or approximately 10% of the anode current in (3)
And a high di / dt is obtained.
The electric field intensity distribution in (1) to (5) is as shown in FIG. 6, and as shown in FIG. 5, when the peak value of the N ⁺ buffer layer is exceeded , the turn-on time is sharply shortened, Will be better.

[0019]

As described above, according to the present invention, since the N base region of the semiconductor element is formed by the low-concentration I base and the high-concentration N ⁺ buffer, it is turned on from a very high voltage in a very short time. A semiconductor switch that can be realized can be realized. Since a short turn-on time means a short time during which the current flowing through the element is suppressed, a high anode current increase rate and low turn-on energy can be achieved. In addition, since it is a solid-state switch, it can have a longer life than conventional thyratrons, etc., can carry a large current with a high withstand voltage, has high-speed turn-on characteristics, and is used as a pulse power source for plasma control, various lasers for accelerators, etc. An effective semiconductor device is obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a gate turn-off thyristor embodying the present invention.

FIG. 2 is an impurity concentration distribution diagram of the gate turn-off thyristor of FIG.

FIG. 3 is a circuit diagram of a turn-on measurement circuit.

FIG. 4 is a turn-on characteristic diagram of the gate turn-off thyristor of FIG.

FIG. 5 is a turn-on time characteristic diagram of the gate turn-off thyristor of FIG. 1;

FIG. 6 is an impurity concentration distribution and electric field intensity distribution diagram.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor body, 2 ... N base, 2a ... I base layer, 2
b ... N ⁺ buffer layer, 3 ... P emitter layer, 4 ... P base layer, 5 ... N emitter layer, 6 ... P ⁺ layer, A ... anode electrode, K ... cathode electrode, G ... gate electrode.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/332 H01L 29/74-29/749

Claims (1)

(57) [Claims] 1. A semiconductor element in which a P layer and an N layer are alternately formed and a high voltage is applied by applying a high voltage using electric conductivity modulation, and an N base region of the semiconductor element has a low concentration. I
Formed by an (N ⁻ ) base and a high concentration of N ⁺ buffer,
The N ⁺ buffer, a depletion layer caused by the turn-on voltage exceeds the peak value of the N ⁺ buffer layer, and the N ⁺
A semiconductor device characterized in that a distance obtained by subtracting a thickness of a depletion layer spreading over an N ⁺ buffer from a thickness of a buffer is longer than a diffusion length from an adjacent P emitter layer.