JP3048007B2 - A / D conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog signal input to an integrator, an output of which is converted to a digital signal via a quantizer, and the digital signal is converted to an analog signal via a digital / analog converter. The present invention relates to a ΔΣ analog-to-digital conversion circuit for realizing high resolution by converting the signal back to an integrator. In this specification,
The analog / digital converter is called an A / D converter, and the digital / analog converter is called a D / A converter.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a configuration example of a conventional Δ-Δ A / D conversion circuit. In the figure, an analog signal X input from an input terminal 91 is input to an analog integrator 93 via an analog subtractor 92, and its output is quantized by a quantizer 94 and output as a digital signal Y to an output terminal 95. It is taken out and input to the D / A converter 96. The output of the D / A converter 96 is input to the analog subtractor 92, where a subtraction process with the analog signal X is performed.

FIG. 11 is a signal flow chart showing a Δ-Σ type A / D conversion circuit having such a configuration expressed by a Z function. In the Z function expression, the analog integrator 93 is 1 / (1−
Z ^-1), and the so D / A converter 96 outputs an analog signal by one timing delayed with respect to the input digital signal a Z ^-1. The quantizer 94 outputs a digital signal Y obtained by adding a quantization noise Q to an input signal (output signal of the analog integrator 93). Therefore, the relational expression of P = (X−YZ ⁻¹ ) / (1−Z ⁻¹ ) (1) Y = P + Q (2) holds, and solving this for Y yields Y = X + Q (1−Z ^-1 )… (3)

Here, the coefficient (1-Z ^-1 ) of Q represents a first-order differentiation, and the quantization noise Q added by the quantizer 94 is distributed more on the high frequency side and suppressed on the low frequency side. Noise shaping characteristics. The quantization noise is １ ／ fs from the DC region (DC) regardless of the sampling frequency fs.
And its power is a constant value determined by the resolution of the quantizer 94. Therefore, a high-precision A / D conversion circuit can be realized by performing oversampling on a necessary band using a sufficiently high sampling frequency and extracting only the necessary band with a low-pass filter.

In a conventional .DELTA .-. SIGMA. A / D conversion circuit, the oversampling rate is increased and the circuit shown in FIG. 10 is connected in multiple stages by a multi-stage noise suppression system (for example, Japanese Patent Application No. 60-18506). By obtaining a high-order noise shaping characteristic, it is possible to achieve high accuracy even when a low-resolution quantizer is used in an audio band.

[0006]

In order to increase the bandwidth of such a Δ-Σ type A / D conversion circuit in order to cope with an image signal or the like, it is necessary to use oversampling. Assuming that the operation speed is higher by an oversampling rate than that of an A / D conversion circuit that does not use oversampling, and an ultra-high speed circuit is required. For example, when an oversampling rate of 64 times generally used for audio is applied to an A / D conversion circuit of about 50 Msps for HDTV, the sampling rate is required to be as high as 3.2 Gsps. Is done. In order to realize this as an integrated circuit, an advanced LSI manufacturing technology with excellent high-frequency characteristics, an expensive mounting technology, and the like are indispensable, and become extremely expensive. Furthermore, an increase in power consumption has been inevitable with the increase in speed.

[0007] In the high-speed operating conditions, the transition time of the output of the D / A converter on the feedback loop, i.e. t _r (rise
time) and t _f (fall time) cannot be ignored with respect to the time during which the steady output is output, so that the linearity of the feedback signal amount is degraded and the S / N ratio of the A / D conversion circuit is limited. Was a factor. The present invention multiplexes a comparator and a D / A converter on a feedback loop, which are limiting factors of the conversion speed of a Δ-Σ type A / D converter, to reduce the required speed and to increase the operation speed. A that can suppress the deterioration of the conversion accuracy due to the high speed and achieve high accuracy
It is an object to provide a / D conversion circuit.

[0008]

According to the present invention, there is provided an integrator for performing an integration process by inputting an analog signal, a quantizer for quantizing an output signal of the integrator and converting the output signal to a digital signal, To an analog signal, and a D / A converter that feeds back to the input of the integrator.
In the D conversion circuit, the quantizer includes a plurality of N quantizers that take in parallel output signals of the integrator,
The D / A converter is configured to generate N corresponding to the N quantizers.
D / A converters, one quantizer divides the time t required for quantization by N, sets the conversion time of each quantizer sequentially, and sets the conversion time of the quantizer to the conversion time. The D / A converter that takes in the output outputs an analog signal corresponding to the time t / N from the conversion time, and the other D / A converter outputs 0.
A conversion operation control means for outputting a level is provided.

[0009]

The plurality of N quantizers sequentially perform a quantization operation at a conversion time obtained by dividing the time t required for quantization by one quantizer into N. Each D / A converter also outputs an analog signal corresponding to t / N time from the conversion time assigned to each quantizer, and the other D / A converters are reset and output 0 level. I do.

As described above, the operation is sequentially performed by using the N multiplexed quantizers and D / A converters, and the signals obtained by the respective D / A converters are superimposed on the time axis to be analogized. By feeding back the signal to the integrator, an A / D conversion circuit having a conversion speed N times one conversion period can be realized.
Further, each D / A converter outputs an analog signal corresponding only to the assigned conversion time and is reset at other conversion times, so that the amount of feedback signal synthesized according to the bit output pattern changes. That can be avoided.

[0011]

FIG. 1 is a block diagram showing a basic configuration of an A / D conversion circuit of the present invention having a 1-bit quantization resolution. In the figure, an analog signal X input from the input terminal 11 is input to an analog integrator 13 via an analog subtractor 12, quantizer 14 ₁ to 1 its output is the N
4 is distributed to _N. The output of each quantizer 14 ₁ to 14 _N, as well is extracted to output terminals 15 ₁ to 15 _N, is input to the corresponding D / A converter 16 ₁ ~ 16 _N. The analog signals output from the respective D / A converters 16 _{1 to} 16 _N are synthesized and fed back to the analog integrator 13 via the analog subtractor 12.

As shown in FIG. 2, the conversion operation control means 17 sets each of the quantizers 14 as conversion times T _{1 to} T _N by dividing a time t required for one quantizer by N into conversion times T _{1 to} T _{N. 1}
Controls to 14 _N, and each D / A converter 16 ₁ ~ 16 _N
Respect, the conversion time T ₁ through T _N from the amount of time interval t ₁ ~t _N with time for each t / N to output an analog signal corresponding to the digital signal input, the time interval allocated to each In other cases, control for outputting the 0 level is performed.

That is, at the conversion time T ₁ , first, the quantizer 1
4 ₁ performs quantization of a signal output from the analog integrator 13 and outputs the obtained digital signal Y ₁ to an output terminal 15 ₁
Output to Further, the D / A converter 16 ₁ outputs an analog signal corresponding to the digital signal Y ₁ input only for the time interval t ₁ . Further, the other D / A converters 16 ₂ to 16 1
In 6 _N, and outputs a zero level regardless of the output of the quantizer 14 ₂ to 14 _N at that time. Similarly, the conversion time T
_The corresponding quantizers 14 _{2 to} 14 _N operate sequentially from _{2 to} T _N , and each of the D / A converters 16 _{1 to} 16 _N outputs the corresponding analog signal or 0 level in each time section.

Thus, each of the D / A converters 16 ₁ to 16 ₁
6 _N are superimposed on the time axis on the analog signal and fed back to the analog integrator 13 so that one quantizer has a conversion speed N times the time t required for quantization. And a D / A converter. FIG. 3 is a block diagram showing the configuration of the embodiment when N = 2 in the present invention.

It should be noted that the corresponding relationship with each unit in FIG. Resistor 31, operational amplifier 32
And capacitor 33 correspond to analog subtractor 12 and analog integrator 13. The comparators 35 ₁ and 35 ₂ for comparing the voltage with the voltage of the comparison voltage source 34 include the quantizer 1
4 _1, corresponding to 14 _2. AND circuits 36 ₁ and a resistor 37 _1, the AND circuit 36 ₂ and the resistor 37 ₂ respectively correspond to the D / A converter 16 _1, 16 _2. The clock signal source 38 and the inverter circuit 39 correspond to the conversion operation control means 17. In such a configuration, the output of the operational amplifier 32 forming the analog integrator is quantized by the comparison operation in the comparators 35 ₁ and 35 ₂ ,
Becomes an AND circuit 36 _1, 36 ₃ of the input signal together with taken out to the output terminal 15 _1, 15 ₂ as a digital signal, the output signal is a voltage-to-current conversion resistor 37 _1, 37 _2, further synthesized analog integrator Returned to the vessel.

The operation of this embodiment will be described below with reference to a time chart shown in FIG. Clock signal source 3
8 rising edge A of the clock signal output from
In, first comparator 35 ₁ performs the determination operation, and outputs the result to the output terminal 15 ₁ and the AND circuit 36 _1. AND circuit 36 _1, the falling edge of the clock signal B
The section up, operates as a D / A converter generates a voltage corresponding to the output of the comparator 35 _1. On the other hand, the second AND circuit 36 _2, the clock signal inputted via the inverter circuit 39 is at zero level, it is reset regardless of the output of the second comparator 35 _2, section output level 0 And

Next, the falling edge B of the clock signal
Then, the second comparator 35_TwoPerforms the judgment operation, and
Output terminal 15_TwoAnd AND circuit 36_TwoOutput to A
Circuit 36_TwoIs the rising edge A of the clock signal.
Up to the comparator 35 _TwoGenerates a voltage corresponding to the output of
And operates as a D / A converter. On the other hand, the first Ann
Circuit 36₁Since the clock signal is at the 0 level,
First comparator 35₁Is reset regardless of the output of
In the section, the output level is set to 0.

In this way, each D / A converter 16 ₁ , 1
62. The analog signal obtained in step ₂ is superimposed on the time axis and fed back to the analog integrator 13, so that a quantizer having a conversion speed twice as long as the clock signal period and D / D
An A-converter can be configured. Each D / A converter 16 _1, 16 _2, 1/2 Since the output clock signal period is reset forced to zero, feedback by t _r, t _f characteristics becomes a problem in the high speed operating conditions The bit output dependency of the linearity of the signal amount can be eliminated.

FIG. 5 shows an output example of the D / A converter in the configuration having no 0 reset function and an output example of the D / A converter in the configuration having the 0 reset function as in the present invention. In FIG. 5, t _r, when considering t _f characteristic, 1 signal amount that is fed back into the conversion section, the signal quantity fed back to the interval in which the output level changes from 0 level to 1 level, before and after The signal amount can be classified into three types: a signal amount fed back in a section where both levels are 1 level, and a signal amount fed back in a section where the output level changes from 1 level to 0 level. 5 (1) and (2), the output pattern is 01110
If it is 0, the total feedback amount is represented by +++ in the configuration having no 0 reset function, and the total feedback amount is represented by +++++ in the configuration having the 0 reset function. 5 (3) and (4), the output pattern is 01
If it is 0110, the total feedback amount is represented by +++++ in the configuration having no 0 reset function, and the total feedback amount is +++++ in the configuration having the 0 reset function.
It is represented by +.

As described above, the D / A which does not perform the 0 reset operation
When the converter is used, the total feedback amount differs depending on the bit output pattern, and has a nonlinearity. On the other hand, when a D / A converter that performs a 0 reset operation is used, when the output pattern becomes 11, the output level changes to 10 and 01 in each D / A converter, and these are combined. Therefore, + is fed back by the number of times of one-level output, and the total feedback amount does not depend on the bit output pattern. That is, it is possible to greatly mitigate the effects of t _r, t _f characteristics when operated at high speed.

[0021] Incidentally, the AND circuit 36 _1, 36 ₂ constituting the D / A converter 16 _1, 16 _2, it is also possible to change the NAND circuit, an OR circuit or a NOR circuit. FIG.
, The D / A converters 16 ₁ , 16 ₂ by the OR circuit
FIG. 6 shows the configuration of an embodiment in which the above is realized. 6, the OR circuit 61 _1, 61 _2, receives the output of the comparator 35 _1, 35 ₂ via the inverter circuits 62 _1, 62 _2,
The output through the inverter circuit 63 _1, 63 ₂ is inverted. The clock signal output from the clock signal source 17, as it is input to the comparator 35 ₁ and an OR circuit 61 _2, the comparator 35 ₂ and an OR circuit 61 ₁ via the inverter circuit 64 _2, 64 ₁ Invert and enter. With such a configuration, operation can be performed in a manner similar to that of the A / D conversion circuit illustrated in FIG.

FIG. 7 shows the configuration of the embodiment shown in FIG. 3 (N = 2).
FIG. 2 is a block diagram showing an example of a generalized configuration of FIG. The feature of the present embodiment is that the time t required for one quantizer to perform quantization is one cycle, and N clock signals C _{1 to} C _N having a phase difference of t / N are sequentially compared. Vessels 35 _{1 to} 35
Uptake in _N and the decoder 71, supplied to the AND circuits 36 ₁ ~ 36 _N to create a control signal D ₁ to D _N decoder 71 corresponding to each phase difference. Here, the relationship between the clock signals C _{1 to} C _N and the control signals D _{1 to} D _N is shown in FIG.

Each comparator 35 having such a configuration₁~ 3
5_NAnd AND circuit 36₁~ 36 _NThe operation of
This is the same as the embodiment shown. FIG. 9 shows the k-bit quantized component.
In the A / D conversion circuit of the present invention having a resolution, FIG.
FIG. 4 is a block diagram showing a configuration example corresponding to the embodiment configuration shown.
You. In the figure, a comparator 35₁, 35_Two, And circuit 3
6₁, 36_Two, Resistor 37 ₁, 37_Two, Output terminal 1
5₁, 15_TwoAnd an inverter circuit 39
This block is used as a conversion unit for 1 bit.
2^kComparison voltage to be supplied to each block
Is generated via the voltage dividing resistor 81,
Quantization resolution can be realized.

[0024]

The present invention described above, according to the present invention, the speed performance required of the D / A converter that is on the feedback loop can be greatly relaxed, and D / A converter of t _r, of t _f characteristic The requirements can be relaxed, and the speed and accuracy of the Δ-Σ A / D converter can be increased.

[Brief description of the drawings]

FIG. 1 shows A / A of the present invention having a 1-bit quantization resolution.
FIG. 3 is a block diagram illustrating a basic configuration of a D conversion circuit.

FIG. 2 is a diagram showing operation timing in the present invention.

FIG. 3 is a block diagram showing a configuration of an embodiment when N = 2 in the present invention.

FIG. 4 is a time chart showing an operation example of the embodiment shown in FIG. 3;

[5] t _r, a D / A converter output example when considering t _f characteristics.

FIG. 6 is a block diagram showing an embodiment using an OR circuit in the embodiment shown in FIG. 3;

FIG. 7 is a block diagram showing an embodiment configuration obtained by generalizing the embodiment configuration shown in FIG. 3;

FIG. 8 is a time chart for explaining the operation of the embodiment in FIG. 7;

FIG. 9 shows the A / of the present invention with k-bit quantization resolution.
FIG. 4 is a block diagram showing a configuration example corresponding to the configuration of the embodiment shown in FIG. 3 in the D conversion circuit.

FIG. 10 is a block diagram showing a configuration example of a conventional Δ-Σ A / D conversion circuit.

FIG. 11 is a signal flowchart illustrating a Δ- し た type A / D conversion circuit expressed by a Z function.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 12 Analog subtracter 13 Analog integrator 14 Quantizer 15 Output terminal 16 D / A converter 17 Conversion operation control means 31 Resistor 32 Operational amplifier 33 Capacitor 34 Comparison voltage source 35 Comparator 36 AND circuit 37 Resistor Reference Signs List 38 Clock signal source 39 Inverter circuit 61 OR circuit 62, 63, 64 Inverter circuit 71 Decoder 81 Voltage dividing resistor 91 Input terminal 92 Analog subtractor 93 Analog integrator 94 Quantizer 95 Output terminal 96 D / A converter

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/02

Claims (1)

(57) [Claims] An integrator for inputting an analog signal to perform an integration process; a quantizer for quantizing an output signal of the integrator to convert the digital signal into a digital signal; reconverting the digital signal into an analog signal; D feedback to the input of the integrator
In the A / D conversion circuit including the / A converter, the quantizer includes a plurality of N quantizers that take in parallel the output signals of the integrator, and the D / A converter includes: The N
It is composed of N D / A converters corresponding to the quantizers,
The time t required for one quantizer to divide by N is divided into N, and the conversion time of each quantizer is sequentially set. An A / D conversion circuit comprising a conversion operation control means for outputting an analog signal corresponding to t / N time from a conversion time and outputting a 0 level to another D / A converter.