JP3045415B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device . More particularly, the present invention relates to a method for manufacturing a non-destructively readable semiconductor device using a ferroelectric film.

[0002]

2. Description of the Related Art A conventional semiconductor memory device using a ferroelectric capacitor has a structure as shown in FIG. In this figure, 1 is a semiconductor substrate, 2 is a source region, 3 is a drain region, 4 is a field oxide film for element isolation, 5 is a gate insulating film, 6 is a channel region, 7 is a ferroelectric film, and 8 is a gate. Electrode film, 9 is an interlayer insulating film, 10,
Reference numerals 11 and 12 denote aluminum wirings of source, gate and drain electrodes, respectively, and reference numeral 13 denotes a passivation film.

In the structure of the prior art, when a voltage is applied between the gate electrode film 8 and the semiconductor substrate 1 to polarize the ferroelectric, the ferroelectric has hysteresis. The polarization remains, and the polarization remaining in the ferroelectric film 7 by applying a voltage between the source and the drain induces electrons or holes in the channel region 6 on the surface of the semiconductor substrate 1, and accordingly, between the source and the drain. ON, OF
The switching action of F occurs, and the stored data can be read out nondestructively.

In the conventional method of manufacturing a semiconductor memory device, a field oxide film 4 is first formed on a semiconductor substrate 1, a gate insulating film 5, a ferroelectric film 7, and a gate electrode film 8 are formed.
After patterning such that they are formed on the channel region 6, impurity ions are implanted using the mask as a mask to form the source region 2 and the drain region 3. After that, an interlayer insulating film 9, electrodes and the like are formed.

[0005]

However, the ferroelectric used for this semiconductor memory element is usually PZT (Pb (Zr _1-x Ti _x ) O).
₃ ) A perovskite structure such as PbTiO ₃ is used because of its large spontaneous polarization, but these materials have poor workability by etching or the like.

Therefore, dry etching such as ion milling must be used to perform fine processing. However, since ion milling is performed by ion beam etching such as argon ion, the ferroelectric film and other insulating materials are used. It is not possible to obtain a large selection ratio with a film or a semiconductor material. Therefore, it is easy to damage surrounding semiconductor materials. If the ferroelectric film 7 formed on the particularly thin gate insulating film 5 is processed by dry etching, if the etching is performed too long, the gate insulating film 5 is broken and the semiconductor substrate 1 is damaged, thereby deteriorating the characteristics of the transistor. If the etching is insufficient, there is a problem that the ferroelectric film 7 remains.

If wet etching is used as an etching method that does not cause much damage, sufficient fine processing cannot be performed, and it cannot be used for a recent semiconductor device that requires processing on the order of submicron, which is a super LSI. .

In view of such circumstances, an object of the present invention is to enable processing of a ferroelectric which is difficult to perform fine processing without affecting the characteristics of a semiconductor device .

[0009]

Preparation of a semiconductor device SUMMARY OF THE INVENTION The present invention includes the step of patterning the protective film on the channel area of the semiconductor substrate, a source region and a drain region by diffusing impurities into both sides of the protective film Forming a low dielectric constant film on a semiconductor substrate after removing the protective film.
A step of, dividing the low dielectric constant film on the channel region
The ferroelectric a step of removed by the steps of forming or directly ferroelectric film via a gate insulating film on the removed surface of a semiconductor substrate, and planarizing the ferroelectric film only in the channel area a step of leaving the body membrane, thereby exposing the ferroelectric said low dielectric constant film <br/> by removing part of the semiconductor substrate surface in the boundary region between the low dielectric constant film on both sides of the membrane
When, is intended to include forming an impurity diffusion region in the semiconductor substrate that has issued the exposed.

[0010]

According to the present invention, a low-dielectric-constant dielectric film (hereinafter, referred to as a dielectric film) is formed on source and drain regions on both sides of a channel region.
After forming a ferroelectric film after forming a low dielectric constant film), the semiconductor region may be damaged by ion milling etc. even if the low dielectric constant film is etched. And does not affect the characteristics of the semiconductor element.

Further, since the protective film for forming the source and drain regions is formed of a protective film which is easily corroded and the alignment is performed again when the ferroelectric film is formed, misalignment may occur. After the body film is formed, the source and drain regions are formed again using the ferroelectric film as a mask, so that the channel length can be accurately formed, the device characteristics can be maintained at a high level, and the etching due to removal of the protective film can be prevented. Even if the semiconductor region is not damaged, the characteristics of the semiconductor element are maintained at a high level from that aspect.

[0012]

Next, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings. 1 to 7 are cross-sectional explanatory views showing the respective manufacturing steps. In these figures, 1 to 13 indicate the same parts as in FIG.

First, as shown in FIG. 1, a field oxide film 4 for element isolation is formed on a semiconductor substrate 1 by patterning with a nitride film or the like, and then a protective film 16 is formed by patterning at a place where a channel region 6 is to be formed. I do. At this time, it is desirable that the width of the protective film 6 be larger than the width of the channel region for the reason described later. As a specific example, a resist film was formed on the p-type semiconductor substrate 1 on which the field oxide film 4 was formed by applying a resist to form a resist film having a thickness of about 1.6 μm, and developed to form a protective film 16.

Next, as shown in FIG. 2, impurities are diffused on both sides of the protective film 16 to form a source region 2 and a drain region 3. As a specific example, As ions are implanted at a dose of 5 × 10 ¹⁵ cm ⁻² by ion implantation,
Diffusion was performed by heat treatment for 30 minutes to form an n ⁺ -type source region 2 and a drain region 3.

Next, as shown in FIG. 3, the protective film 16 is removed, a low dielectric constant film is formed on the entire surface of the semiconductor substrate, and the low dielectric constant film on the channel region 6 is removed. Rate membrane
Leave 14, 15. As a specific example, after removing the resist film with a resist clearing liquid, SiH ₄ gas and N
_A gas phase reaction was conducted at about 800 ° C. by introducing ₂ O gas to form a silicon oxide film of about 0.6 μm.

After that, patterning is performed again with a resist film, and a hole 17 having a width equal to the width of the necessary channel region 6 is formed.
Was formed on a low dielectric constant film. Here, if the protective film 16 in the step of FIG. 1 is formed to have a width corresponding to the width of the channel region 6 and the position and the formation position of the hole 17 in this step match, Although it is preferable to perform the alignment separately, if they are to be formed with the same width, they are shifted as shown by a dotted line A in FIG. 3 and one is formed on the source region 2 or the drain region 3 so that the channel length can be accurately adjusted. There is a problem that it cannot be controlled. Therefore, in the present embodiment, the width of the protective film 16 is formed relatively large in the process of FIG. 1 and the distance between the source region 2 and the drain region 3 is formed relatively large.

On the other hand, if the protection film 16 in the step of FIG. 1 is formed of a heat-resistant material such as a nitride film in order to solve such an alignment problem, the protection film 16 is formed after forming the low dielectric constant film. By removing 16, an accurate width of the channel region 6 can be formed by self-alignment. However, when a nitride film or the like is formed, the surface of the semiconductor substrate is roughened, crystal defects are generated, and the source region 2 and the drain region 3 are formed. After the formation of the semiconductor element region such as described above, it is not possible to perform a process for removing defects, which is not preferable in terms of semiconductor characteristics. For this reason, in the present embodiment, the source and drain regions are formed using a resist film that can be easily removed while preparing for misalignment.

Subsequently, as shown in FIG. 4, a gate insulating film 5 and a ferroelectric film 7 are sequentially formed, and the surface is flattened. As a specific example, a silicon oxide film of about 0.6 μm is formed by the CVD method using TEOS, and then PbTiO ₃ is formed by 0.5 μm by sputtering.
18 was applied to flatten the surface. When the ferroelectric film does not react with the semiconductor substrate, the gate insulating film 5 is not required.

Next, as shown in FIG. 5, the ferroelectric film 7 is left only on the place where the channel region 6 is formed by etch back. As a specific example, dry etching was performed by ion milling until the low dielectric constant films 14 and 15 were exposed, and the ferroelectric film 7 was formed between the low dielectric constant films 14 and 15. At this time, the etching by ion milling removes the resist and the ferroelectric film in the same manner, and the surface is flattened, so that the ferroelectric film 7 and the low dielectric constant films 14 and 15 are also formed on the same plane. At this time, even if the low dielectric constant films 14 and 15 were damaged by ion milling, the semiconductor region was not damaged, so that the characteristics were not affected at all.

Next, as shown in FIG. 6, a part of the remaining low dielectric constant films 14 and 15 around the ferroelectric film 7 is removed to form impurity diffusion regions 2a and 3a. As a specific example, a resist film 20 is formed by applying a resist on the entire surface, and patterning is performed on both sides of the ferroelectric film 7 so as to have a width of about 0.5 μm, and etching is performed with an HF solution to form a hole 19. did. After that, a dose of 6 × 10 ¹⁵ of As ions is ion-implanted.
Ion implantation was performed at cm ⁻² and heat treatment was performed at about 900 ° C. for about 30 minutes to form n ⁺ -type diffusion regions 2a and 3a. This diffusion area
2a and 3a have the same conductivity type as the source region 2 and the drain region 3, respectively, and the new diffusion regions 2a and 3a also become the source region 2 and the drain region 3, respectively, and are formed by self-alignment with the width of the ferroelectric film 7, A channel region 6 having an accurate channel length can be formed.

Finally, the gate electrode film 8 and the interlayer insulating film 9 are formed to fill the opening 19, and the source electrode 10 and the gate electrode 1 are formed by the usual semiconductor process.
1. By forming an aluminum wiring for the drain electrode 12 and forming the passivation film 13, a semiconductor memory element having a structure as shown in FIG. 7 can be formed. As a specific example, a silicon oxide film is formed as an interlayer insulating film 9 by a CVD method, an electrode contact hole is punched by a reactive ion etching (RIE) method, and an aluminum film is formed by sputtering to form each electrode. Further, a silicon oxide film was formed as a passivation film by a CVD method.

[0022]

As described above, according to the present invention,
A low dielectric constant film is formed on the source and drain regions so as not to harm the semiconductor region when the ferroelectric film is etched, and is used as a protective material when the ferroelectric film is etched. , The semiconductor memory device with high characteristics can be obtained.

As a result, the problem of processing a conventional semiconductor memory device using a ferroelectric film is solved, and a semiconductor memory device having high characteristics can be easily formed.

[Brief description of the drawings]

FIG. 1 is an explanatory sectional view showing a manufacturing process of a semiconductor memory element according to one embodiment of the present invention.

FIG. 2 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 3 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 4 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 5 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 6 is an explanatory sectional view showing a manufacturing step of the semiconductor memory element according to one embodiment of the present invention;

FIG. 7 is an explanatory sectional view showing a final step of the manufacturing process of the semiconductor memory element according to one embodiment of the present invention;

FIG. 8 is an explanatory sectional view showing the structure of a conventional semiconductor memory element.

[Description of Signs] 1 semiconductor substrate 2 source region 3 drain region 5 gate insulating film 6 channel region 7 ferroelectric film 8 gate electrode film 10 source electrode 11 gate electrode 12 drain electrode 14, 15 low dielectric constant film 16 protective film

Claims (1)

(57) [Claims] And 1. A step of patterning the protective film on the semiconductor substrate in the channel area on the steps of forming a source region and a drain region by diffusing impurities into both sides of the protective film, after removing the protective film Forming a low dielectric constant film on a semiconductor substrate, and removing the low dielectric constant film on the channel region
If, forming a or directly ferroelectric film via a gate insulating film on the removed surface of the semiconductor substrate, the ferroelectric film only in planarizing the ferroelectric film the channel area on a step of leaving, the boundary region between both sides of the low dielectric constant film of the ferroelectric film
Removing part of the low dielectric constant film in the semiconductor substrate
A method of manufacturing a semiconductor device , comprising: exposing a surface; and forming an impurity diffusion region in the exposed semiconductor substrate .