JP2939865B2 - Thin film semiconductor device and display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a thin film semiconductor device which can manufacture at low cost with a few manufacturing process by a method wherein the semiconductor device is composed of the transistors of the same conductive type. SOLUTION: A liquid crystal display panel 42, a drain driver 44 and a gate driver 45 of a liquid drive circuit are integrally formed on a glass board 46. The thin film transistor, which constitutes the above-mentioned drain driver 44 and the gate driver 45, and the thin film transistor of switching elements, provided on each picture element of the liquid crystal display panel, are formed using the same conductive type PMOS transistor. Consequently, as a drive circuit and a display part can be formed simultaneously on a sheet of glass board 46 and the formation of the same conductive transistors is sufficient, the time of ion-doping can be saved, and the cost of manufacture can be cut down.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film semiconductor device and a display device using the same, and more particularly, to a thin film semiconductor device constituted by thin film transistors of the same conductivity type and a display device using the same .

[0002]

2. Description of the Related Art Conventionally, a driver circuit of a liquid crystal display device or the like is provided with a thin film transistor (TFT).
, A CMOS circuit is usually used. In addition to the driver circuit of the liquid crystal display device, a driver circuit using a CMOS circuit includes a print head such as a thermal printer or a driver circuit of a photo sensor. This CMOS circuit has advantages such as low power consumption and proper output, and is widely used.

For example, FIG. 14 is a diagram showing a configuration of a CMOS inverter circuit. As shown in FIG.
S1 uses two types of transistors, PMOS2 and NMOS3, in pairs. In the CMOS1, when IN (input) is "0", the NMOS3 is turned off and the PMOS3 is turned off.
2 is turned on and "1" is output (output) from the power supply Vdd. When the input is “1”, the PMOS 2 is turned off and the NMOS 3 is turned on, thereby turning “0” from the ground.
Is output. In this way, the CMOS inverter circuit outputs a logic opposite to the logic that is input.

In the above conventional example, an example is shown in which an inverter circuit is formed using CMOS. However, a driver circuit using a latch circuit, an AND circuit, a NAND circuit, a tristate circuit, or the like is also formed. In this case, CMOS is used.

[0005]

However, in such a conventional thin-film semiconductor device, the C-type semiconductor device shown in FIG.
Since the MOS1 is composed of two types of transistors, the PMOS2 and the NMOS3, it is necessary to make both the PMOS and the NMOS when manufacturing the CMOS, which complicates the element structure and increases the impurity implantation step and the number of masks. Therefore, there was a problem that the cost was increased.

Accordingly, the present invention has been made in view of the above-mentioned problems, and has been made in consideration of one of the P-type and N-type conductivity types.
It is an object of the present invention to provide a thin-film semiconductor device which can be manufactured at a low cost with a small number of manufacturing steps and a skin device using the thin-film semiconductor device by forming an entire circuit using the thin film transistor.

[0007]

A thin film semiconductor device according to claim 1, wherein SUMMARY OF THE INVENTION, the entire thin film transistor included in the thin film transistor circuit formed on a single substrate is composed of only one of the thin film transistor P-type or N-type, the Thin film tiger
The transistor circuit is connected to the non-inverting and
Inverter circuit with inverted and inverted signal output ends
The source and drain of the inverter circuit are connected in series.
Non-inverting and inverting inputs to each gate
Signal is applied, and one of the input and output terminals is
A first thin film connected to each other and the other to a high potential
A second thin film transistor, the other of which is connected to a low potential;
A first inverter circuit composed of a membrane transistor,
One of the power ends is connected to each other via a capacitor,
A third thin film transistor connected to a high potential and others
Is the fourth thin film transistor connected to the lower potential.
A second inverter circuit, and the first thin film transistor
Non-inverting signal is applied to the
Means, the second thin film transistor and the third thin film transistor.
Means for applying an inversion signal to the film transistor .

As described above, when the thin film transistor circuit is composed of P
Since it is composed of only one of the N-type and N-type conductivity type thin film transistors, the number of times of ion doping for implanting an impurity portion and the number of masks are greatly reduced, and the manufacturing cost can be reduced.

The display device according to the first aspect of the present invention is, for example, a thin film transistor as described in the second aspect.
A shift register circuit including a plurality of latch circuits, and the latch circuit includes the inverter circuit.
A non-inverting output signal output end of the inverter circuit.
Means for connecting the input terminal with the non-inverting input signal input terminal;
Connect the inverted signal output terminal to the inverted signal input terminal.
Means.

In the display device according to the third aspect , a large number of the display devices are provided on a substrate.
Pixels and a switching thin film transistor connected to each pixel.
Transistor and drive circuit for driving the thin film transistor
In the display device in which the portion is formed, it is formed on the substrate.
Switching thin film transistor and driving circuit section
Whether the entire thin film transistor contained in the P-type or N-type
Composed of only one type of thin film transistor
The drive circuit section includes a non-inverting and an inverting input signal input terminal.
Having an output section and a non-inverted and inverted signal output end
Circuit, and the inverter circuit has a source / drain
Connected to the column and each gate has non-inverted and inverted
Input signal is applied and one of the input / output terminals
Connected to each other via the other, and the other connected to a high potential.
Thin film transistor and the other in which the other is connected to a low potential.
A first inverter circuit comprising two thin film transistors,
And one of the input and output terminals are connected to each other via a capacitor
And a third thin-film transistor, the other of which is connected to a high potential.
And a fourth thin film transistor having the other connected to a low potential.
A second inverter circuit comprising a first thin film and the first thin film
Non-inverted signal to the transistor and the fourth thin film transistor
Means for applying a signal, the second thin film transistor and
Means for applying an inversion signal to the third thin film transistor;
It is characterized by having.

The display device according to claim 3 is, for example,
In this case, as described in claim 4, the driving circuit unit includes:
A shift register circuit composed of multiple latch circuits
And the latch circuit includes the inverter circuit, and
The non-inverted output signal output end of the inverter circuit and the non-inverted output signal
Means for connecting the inverted input signal input terminal to the input terminal;
Means for connecting an output terminal and the inverted signal input terminal.
You can do it.

Further, in the display device according to the third aspect, polysilicon can be used for a semiconductor layer of the thin film transistor.

[0013]

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 13 are diagrams showing an embodiment of a thin film semiconductor device and a method of manufacturing the same according to the present invention. Here, a liquid crystal driving circuit and a thin film transistor (TFT: Thin Film Tran
A switching element composed of a cistor is integrally formed to implement a drive circuit integrated type liquid crystal display device. In the present embodiment, the liquid crystal drive circuit and the switching element for each pixel are provided with the same conductivity type TFT (PMO).
(S transistor).

(Manufacturing Process of Thin Film Transistor) FIGS. 1 and 2 are diagrams showing a manufacturing process of a thin film transistor of the same conductivity type according to the present embodiment, wherein at least a thin film transistor in a pixel portion has a plurality of gates. The structure is adopted.

A feature of the present invention is that by forming a driver circuit including a latch circuit using thin-film transistors of the same conductivity type, the number of impurity implantation steps is reduced as compared with the case of manufacturing a conventional CMOS, and the impurity implantation step is reduced. Since the number of masks required for the process is reduced, the cost can be reduced. In particular, the thin film transistor formed in FIGS. 1 and 2 employs a multi-gate structure as a thin film transistor in a pixel portion of a liquid crystal display device.
The S / D (source / drain) withstand voltage is improved to reduce the leak current.

First, as shown in FIG. 1A, after cleaning a glass substrate 10, a silicon oxide film is formed as a base transparent insulating film 11 using a sputtering apparatus to a thickness of about 1000 Å. The base insulating film is not limited to the silicon oxide film described above, and other films may be used. Then, a base insulating film 1 made of a silicon oxide film
Further, an amorphous silicon film 12 is formed on the substrate 1 using a plasma CVD apparatus to a thickness of about 500 Å. The method of forming the amorphous silicon film 12 is not limited to this, and other methods can be used.

Next, the amorphous silicon film 12 shown in FIG. 1A is subjected to a dehydrogenation treatment in a nitrogen atmosphere at 450 ° C. for about 2 hours. This dehydrogenation step can be omitted. Next, as shown in FIG. 1 (b), the amorphous silicon film 12 is irradiated with laser twice at an energy density of about 350 mJ / cm ² in vacuum using an excimer laser device to perform laser annealing and poly-polishing. To form polysilicon 12 '. The laser device described above,
The laser irradiation conditions and the method of poly-polishing (laser annealing method) are not limited to those described above. For example, poly-polishing may be performed using a solid phase growth method.

Next, as shown in FIG. 1C, a photoresist (PR) is applied on the polysilicon film 12 'and is exposed to UV light through a mask having a predetermined pattern to thereby form a photoresist mask. 13 is formed. And
Using a not-shown ion doping apparatus, the flow rate ratio of B ₂ H ₆ diluted with 1% hydrogen to hydrogen gas was 5/45 (cc).
m) and 2 × 10 ¹⁵ (ions / c) at an acceleration energy of 10 KeV through the photoresist mask 13.
An impurity of about m ² ) is implanted. Further, the apparatus, conditions, or implantation method used in the above-described impurity implantation step is not limited to the above, and any other than the above may be employed.

Next, as shown in FIG. 1D, after boron is selectively implanted into the polysilicon film 12 ', which is a semiconductor layer, impurity atoms are activated by laser annealing, and here, holes are formed. Are selectively formed. In the region where the impurity is not implanted,
An i region remains as an intrinsic semiconductor, and a channel of a MOS transistor described later is formed.

Next, as shown in FIG. 1E, the polysilicon film 1 is activated by selectively implanting impurities.
By selectively etching 2 ', element isolation for forming a source region, a channel region, and a drain region for each MOS transistor is performed. In the element region 13A shown in FIG. 1E, two intrinsic semiconductor regions (i-regions) each serving as a channel region are formed between three divided P regions, and a pixel portion having a dual gate structure is formed. It is configured to form a TFT. In the element regions 13B and 13C, the sources and drains of the two PMOS transistors are connected in series to form, for example, an inverter circuit in a driver circuit.

Then, as shown in FIG. 2A, a silicon oxide film 14 and a silicon nitride film 15 are formed on the semiconductor layers separated from each other to a predetermined thickness, respectively.
A gate insulating film is formed.

Next, as shown in FIG. 2B, a metal chromium film 16 is further formed on the silicon nitride film 14 to a predetermined thickness and selectively etched to form a gate electrode or the like. To form Next, as shown in FIG.
An indium oxide film (ITO: Indioxide) forming a pixel electrode 17 of a pixel portion arranged in a matrix on a liquid crystal display panel
um Tin Oxide) with a predetermined film thickness.

Next, as shown in FIG.
A silicon nitride film 18 serving as an interlayer insulating film is formed on the entire surface including the pixel electrode 17 made of TO. Then, FIG.
In (e), a contact hole for making contact with the source region and the drain region of each PMOS transistor is formed by performing selective etching via the interlayer insulating film and the gate insulating film. Then, after an aluminum (Al) film is formed inside and on the surface of the contact hole, it is patterned into a predetermined shape to form an S / D (source / drain) electrode 19.

As described above, on the glass substrate of the liquid crystal display device of the present embodiment, the liquid crystal drive circuit composed of PMOS transistors of the same conductivity type and the switching element for each pixel are integrally formed. As a result, the number of times of ion doping is smaller than that of a conventional liquid crystal driving circuit using a CMOS transistor, and the number of masks for ion doping can be reduced, so that the manufacturing cost can be reduced.

The TF of the pixel portion shown in FIGS.
As shown in FIG. 2E, the switching element of T connects the source and the drain of two PMOS transistors in series to the element region 13A, and connects the gate electrodes 16 and 16 of the two PMOS transistors to a common gate. Because we adopted a dual gate structure that connects to the line,
The S / D (source / drain) withstand voltage is improved, and the leakage current can be reduced.

Further, the TF formed in FIG. 1 and FIG.
Since the semiconductor layer of T is made of polysilicon obtained by polycrystallizing amorphous silicon, the aperture ratio can be improved particularly in the pixel portion and the gate applied voltage can be reduced, so that power consumption can be reduced. Become.

FIG. 3 is a diagram for explaining an ion doping process in the case where the thin film transistors of the same conductivity type according to the present embodiment are formed in an LDD structure. In FIG. 3, the element region 21 of the TFT forming the switching element in the pixel portion has low-level source and drain regions inscribed at both ends of the channel region 24 in place of the dual gate structure described with reference to FIGS. The high concentration impurity diffusion layers 25 and 26 are formed, and the high concentration impurity diffusion layers 27 and
In this case, a so-called LDD structure is formed.

The manufacturing process at the preceding stage in FIG.
1A and 1B, after the amorphous silicon film 12 has been poly-crystallized, an oxidation of, for example, about 200 angstroms is applied between the polysilicon film 12 'and the photoresist 30 applied thereon. Silicon film 29
And selectively etching it into the shape shown in FIG.

As shown in FIG. 3, the silicon oxide film 29 '
Since the width of the photoresist 30 ′ is smaller than the width of the photoresist 30, two types of masks having different ion implantation concentrations can be formed. Then, by implanting impurities with an energy of 20 KeV in the state of FIG. 3, an intrinsic semiconductor in which impurities are not implanted in a thick mask portion (channel region 24), and a P minus region in which a low concentration impurity is implanted in a thin mask portion. 25 and 26, and P-plus regions 27 and 28 into which high-concentration impurities are implanted are formed in portions without a mask, and an LDD structure can be formed by one ion doping process. Further, other manufacturing conditions may be the same as those in FIGS.

As described above, when the LDD structure is adopted for the TFT in the pixel portion shown in FIG. 3, there is an advantage that the leak current can be reduced without increasing the number of times of ion doping.

(Liquid Crystal Driving Circuit Using Thin Film Transistor) FIG. 4 shows a driving circuit integrated TFT according to this embodiment.
FIG. 2 is a schematic configuration diagram of an LCD 41. This drive circuit integrated type TFT-LCD 41 is a liquid crystal display panel (TFT-LC
D: Thin Film Transistor-Liquid Crystal Display)
As a switching element of each pixel 42, a TFT 43 having a dual gate structure formed in FIG. 2 is formed, and a liquid crystal driving circuit including a drain driver 44 and a gate driver 45 is integrally formed on a glass substrate 46.

As shown in FIG. 4, a driving circuit integrated TFT
LCD 41 is a liquid crystal display panel 4 on a glass substrate 46
2, a plurality of TFTs 43 are formed for each pixel, and a scanning signal is applied to a gate line 47 of each TFT 43 of the liquid crystal display panel 42 to create a selected state and a non-selected state by a gate driver 45. The TFT 43 that has been selected by the
A display signal is applied from 4 through a drain line 48, and the liquid crystal of each pixel is driven.

(Drain Driver) FIG. 5 is a diagram showing an example of a circuit configuration of a part of the drain driver 44 of FIG.
The drain driver 44 shown in FIG.
, And NAND circuits 61, 62, and latch circuits 71, 7, respectively.
, Latch circuits 81, 82,..., And tri-state circuits 91, 92,.

The latch circuits 51, 52, and 53 constituting the shift register 50 receive control signals (XSCL) and a horizontal synchronizing signal (@XSCL) input from a controller (not shown) at control signal input terminals (XSCL). L) and the inverted control signal input end (￣L) are input at opposite phases, and when “1” enters the control signal input end (L), the input signal is output through. When "0" is entered, the previous input signal is latched.

As an input signal to the latch circuit 51, an XD clock and an inverted XD clock (￣XD) are input, and an output signal corresponding to a through state and a latch state is output to an output terminal (O).
And the inverted output terminal (￣O), and is input to the AND terminal 61 and the input terminal of the next-stage latch circuit 52.

Similarly, the output signal of the latch circuit 52 is supplied to the AND circuits 61 and 62 and the next-stage latch circuit 5.
3 is input to the input terminal. The AND circuit 61 receives the output (OUT) of the latch circuit 51 and the inverted output (￣OUT) of the latch circuit 52 and outputs a logical product and its negation to a control signal input terminal of the latch circuit 71. (L) and the inverted control signal input terminal (￣L). Similarly, the AND-and-NAND circuit 62
Output (￣OUT) and the output of latch circuit 53 (OU
T) and the logical product and its negation are input to the control signal input terminal (L) and the inverted control signal input terminal (￣L) of the latch circuit 72.

The latch circuit 71 and the latch circuit 72 latch the data of each pixel input from the data conversion circuit (not shown) in accordance with the timing of the output signals from the AND circuits 61 and 62. The latched data is output to the next-stage latch circuits 81 and 82, respectively. The latch circuits 81 and 82 latch the data for each pixel input at the timing of the clock OP and output the output to the respective tri-state circuits 91 and 92.

The tristate circuits 91 and 92 appropriately select three types of power supply voltages VH, VC and VL according to a combination of the input signals from the latch circuits 81 and 82 and the AC signal WF. As a result, an alternating display signal is generated. Tri-state circuit 91
Is output to D1 of the drain line, and the converted display signal output from the tri-state circuit 92 is output to D2 of the drain line.
Is output to

In FIG. 5, only a part of the configuration of the drain driver 44 for supplying the drain lines for two lines has been described. Actually, the above circuits are connected in the horizontal scanning direction according to the number of pixels. It is arranged. This allows
A display signal corresponding to a pixel position can be supplied to each drain line.

As described above, the drain driver 44 composed of the shift register, the latch circuit, the AND circuit, and the tristate circuit has the same conductivity type MO.
It can be configured using an S-transistor (here, PMOS) and a capacitor, so that the transistor structure is simplified, the number of times of ion doping is reduced, and If the driving circuit and the TFT used for the switching element of the pixel are of the same conductivity type, a driving circuit integrated TFT-LCD can be simultaneously formed on the glass substrate 46, so that the cost can be further reduced. There is.

The drain driver 4 according to the present embodiment
As described with reference to FIGS. 1 to 3, the TFT used in No. 4 has a dual gate structure or an LDD structure, and thus has a small leakage current and low power consumption. In addition, the logic circuit of the liquid crystal drive circuit includes "pass transistor logic" and "bootstrap method" described later.
, An appropriate output level can be obtained and power consumption can be reduced.

(Latch Circuit) FIG. 6 is a diagram showing an example of a circuit configuration of the latch circuit 51 constituting the drain driver 44 of FIG. First, the configuration will be described. As a basic circuit configuration of the latch circuit 51 shown in FIG. 6, two-input type inverter circuits 101 and 102 are included.

That is, the inverter circuit 101
From the power supply Vdd, two PMOS transistors Q16 and Q1
7 are connected in series to the source / drain and grounded to the ground, and the logic input from the input end (I) is
The inverted logic input to the gate electrode of the transistor Q16 and input from the inverted input terminal (￣I) is output to the PMOS transistor Q15 via the channel of the PMOS transistor Q15 whose gate is grounded.
Input to the gate electrode of S transistor Q17. One end of the capacitor C11 is connected to the connection between the PMOS transistors Q16 and Q17, the other end is connected to the gate electrode of the PMOS transistor Q17, and the connection between the PMOS transistors Q16 and Q17 is connected to the inverted output end. (￣O), and outputs the inverted logic of the logic input from the input terminal (I).

The inverter circuit 102 has the same configuration as the above-described inverter circuit 101 except that the gates of the PMOS transistors Q19 and Q20 are connected to the input terminal (I) and the inverted input terminal (￣I). Are connected in reverse. The input terminal (I) and the inverted input terminal (端
The input data input from I) is controlled by switching the PMOS transistors Q11 and Q12 by the inverted clock signal (@clk) from the inverted control signal input terminal (@L).

The output data of the inverter circuits 101 and 102 is converted into a PMOS by a clock signal (clk) input from the control signal input terminal (L).
Data switching is controlled by switching the transistors Q13 and Q14.

That is, the output of the inverter circuit 101 is supplied to the PMOS transistor Q14 through the channel of the PMOS transistor Q14.
The output of the inverter circuit 102 is connected to the drain side of the PMOS transistor Q11 via the channel of the PMOS transistor Q13 to form a feedback loop.

In the latch circuit 51 configured as shown in FIG. 6, an inversion control signal input terminal (￣L) from the outside.
In accordance with the control signal from the control signal input terminal (L), the latch circuit 51 is switched between a through operation and a latch operation.

As described above, the latch circuits 51 to 53 constituting the inverter circuit 50 of FIG. 5 and the other latch circuits 71, 72, 81 and 82 have the same configuration as the latch circuit of FIG. For this reason, since a circuit conventionally configured by CMOS can be configured by PMOS transistors of the same conductivity type, the number of times of ion doping is reduced,
Since the number of masks is reduced, manufacturing costs can be reduced.

Next, the operation will be described. In the latch circuit 51 shown in FIG. 6, the clock signal (clk) input to the control signal input terminal (L) is high “1”, and the inverted clock signal (Δclk) at the inverted control signal input terminal (ΔL). ) Is low “0”, a through state occurs. Conversely, the clock signal (clk) input to the control signal input terminal (L) is low “0” and the inverted control signal input terminal (￣L If the inverted clock signal (@clk) of ()) is high "1", the latch state is established.

The above-mentioned through state means that the input end (I)
Is output as an output signal (OUT) of the output terminal (O) as it is, and the inverted input terminal (￣
The state in which the inverted input signal (信号 IN) from I) is output as it is as the inverted output signal (￣OUT) at the inverted output end (￣O). Further, the above-mentioned latch state means that the output state before the latch is maintained.

More specifically, when the clock signal (clk) is high "1" and the inverted clock signal (@clk) is low "0", a through state is established, and the PMOS transistors Q13 and Q14 in FIG. 6 are turned off. Then, the PMOS transistors Q11 and Q12 are turned on. Therefore, the input signal (IN) is “0” and the inverted input signal (￣IN) is “1”.
, The PMOS transistors Q17 and Q19 are turned off, and the PMOS transistors Q16 and Q20 are turned on, so that the output signal (OUT) becomes “0” and the inverted output signal (￣OUT) becomes “0”. 1 "is output.

Next, the clock signal (clk) is low "0" and the inverted clock signal (@clk) is high "1".
In the case of, the latch state is established, and the PMOS transistors Q13 and Q14 in FIG.
11 and Q12 are turned off. For this reason, regardless of the input signals at the input terminal (I) and the inverting input terminal (） I), “0” of the output signal (OUT) in the previous through state passes through the PMOS transistor Q13 and the PMOS transistor Q1.
6 and Q20 are turned on, and "1" of the inverted output signal (@OUT) is output to the PMOS transistor Q14 via the PMOS transistor Q14.
Since the S-transistors Q17 and Q19 are turned off, the previous output state is maintained, the output signal (IN) is "0", and the inverted input signal (@IN) "1" is output as it is.

As described above, the latch circuit shown in FIG.
The gates of the PMOS transistors Q11 to Q14 are switched between a through operation and a latch operation in accordance with an external control signal.

The latch circuit shown in FIG. 6 includes inverter circuits 101 and 102. In the inverter circuits, capacitors C11 and C12 and PMOS transistors Q15 and Q18 are formed, and the PMOS transistors Q and Q18 are formed.
Since the "bootstrap method" is adopted in which the gate capacitance on the side of the transistor 17 or Q20 is increased and switching is performed reliably, the loss of the output level is eliminated, the DC leakage current is eliminated, and the power consumption can be reduced. In the latch circuit 51, the circuit is formed by PMOS transistors. However, the present invention is not limited to this. The entire TFT on the substrate may be formed by NMOS transistors.

(And-Nand Circuit) FIG. 7 shows an AND-and circuit 61 constituting the drain driver 44 of FIG.
FIG. 8 is a diagram showing a symbol of the AND circuit 61 of FIG. 7. First, the configuration will be described. The four PMOS transistors Q21 to Q24 shown in FIG. 7 generate a logical product with respect to an input and its negation by using pass transistor logic. That is, when there are two inputs a and b, inverted a (￣a) and inverted b (￣b), which are negated, are also input. Then, a PMOS is provided between the input terminal of a and the ground.
The transistors Q21 and Q22 are connected in series, and a PM is connected between the input terminal of the inverted terminal a and the power supply (Vdd).
The OS transistors Q23 and Q24 are connected in series.

The PMOS transistors Q22 and Q2
Switching is performed by inputting b to the gate of No. 4 and switching is performed by inputting inverted b to the gates of the PMOS transistors Q21 and Q23. Then, according to the result of the switching, a high-level "1" or low-level "0" signal is output between the PMOS transistors Q21 and Q22 and between the PMOS transistors Q23 and Q24.

However, the PMOS transistor Q2
With only 1 to Q24, a loss occurs in the output of the low level by the threshold voltage of the transistor. Therefore, in the AND-and-NAND circuit 61 of the present embodiment, the output level is corrected by adding inverter circuits 111 and 112 having the same configuration as the inverter circuit described in FIG. That is, in this case, the low level output via the PMOS transistors Q27 and Q30 is reduced until the potential becomes equal to the ground level. FIG. 8 shows the correspondence between the symbols of the AND-AND circuit 61 of FIG. 7 and the input / output signals at each end.

Next, the operation will be described. When the input a is “0” (the inverted a is “1”) and b is “0” (the inverted b is “1”), the PMOS transistors Q21 and Q21
23 is turned off and Q22 and Q24 are turned on, so that the PMOS transistors Q26 and Q30 on the inverter circuit are turned off, but the PMOS transistors Q27 and Q29 are turned on, the AND output is "0", and the NAND output is "1". Becomes

Similarly to the above, when the input a is "0" (the inverted a is "1") and the b is "1" (the inverted b is "0"), the AND output is "0", The NAND output becomes “1”.

When the input a is "1" (the inverted a is "0") and b is "0" (the inverted b is "1"),
The AND output is “0” and the NAND output is “1”. Further, when the input a is “1” (the inverted a is “0”) and the b is “1” (the inverted b is “0”), the AND output is “1” and the NAND output is “0”. Becomes

As described above, the AND-AND circuit 61 shown in FIG. 7 performs a predetermined logical product (AND) and its negation in accordance with a combination of the input a, inverted a, b, and inverted b. (NAND) is output. When a low level is output by an AND output or a NAND output, the output level can be corrected by combining the inverter circuits 111 and 112 as in the present embodiment, so that the ground level (0 V) can be reliably obtained. An equivalent potential can be output.

In addition, the above-mentioned AND-NAND circuit 61
Adopts the inverter circuits 111 and 112 employing the “bootstrap method”, so that DC leakage current is eliminated and power consumption can be reduced. In the AND circuit 61, a circuit is formed using PMOS transistors.
The entire circuit may be configured by NMOS transistors.

(Tristate Circuit) FIG. 9 shows a tristate circuit 91 constituting the drain driver 44 of FIG.
FIG. 10 is a diagram showing a symbol of the tri-state circuit of FIG. 9. This tri-state circuit 91 is used, for example, when driving a liquid crystal by a liquid crystal driving device, when a direct current voltage is applied to the liquid crystal, the liquid crystal is deteriorated, and thus a driving voltage that is converted into an alternating current is generated.

First, the configuration will be described. As shown in FIG. 9, the eight PMOS transistors Q21 to Q28
a, inversion a (￣a), b, and inversion b (論理 b) based on four input signals, a logic generation unit 12 that generates a predetermined logic
1. In this tri-state circuit 91,
By inputting positive logic and negative logic to a and b respectively, an alternating voltage generated by switching three types of power supply voltages VH, VC and VL is output from an output c (however, VH
>VC> VL). Here, a pass transistor logic method is used in the same manner as in the above-described AND circuit 61.

For example, when this tri-state circuit is used in a liquid crystal driving device, the input signal “a” indicates the presence / absence of write data, that is, whether the liquid crystal is driven or not, and “b” indicates the liquid crystal driving device. It can be used to indicate positive / negative of voltage.

Next, the six PMOS transistors Q39
Q44 and the capacitors C31 and C3 constitute the two inverter circuits described with reference to FIG. 6, and here, capacitors C33 and C34 are further added. As described above, the inverter circuits 122 and 123 supply the power supply voltage VH
, VL are switched and output, thereby optimizing the voltage level of the gate signal applied to the gates of the PMOS transistors Q45 and Q46. For this reason, it is possible to drive each transistor sufficiently to perform on / off control, and to optimize the output voltage value. Further, the PMOS transistors Q45, Q46, Q47 are:
It is a switching transistor that switches and outputs the power supply voltages VH, VL, and VC.

Next, the operation will be described. The tri-state circuit 91 shown in FIG. 9 inputs either a positive logic or a negative logic to each of a and b, so that c to VH,
Either VC or VL is output. In practice, the inputs a,
By changing b, a desired alternating signal can be generated.

First, when the input signals a and b are "0", the PMOS transistors Q45 and Q46 are turned off and the PMOS transistor Q47 is turned on, so that Vc is output from c. Also, when the input signal a is “0”,
When b is "1", Vc is output from c in the same manner as described above. This is because when a is “0”, the PMOS transistors Q31, Q33, Q35, and Q37 of the logic section are turned off, so that the PMOS transistor Q47 is turned on without being affected by the input signal of b, and This is because Vc is output.

When the input signal a is "1", the switching transistor Q47 is turned off, and the logic unit P47 is turned off.
MOS transistors Q32, Q34, Q36, Q38 are turned off, and conversely, PMOS transistors Q3
1, Q33, Q35 and Q37 are turned on. Therefore, b
The output voltage from c changes based on the input signal.

When b is "0", the PMOS transistor Q46 is turned on and Q45 is turned off, so that VL is output from c. If b is “1”, PM
Since OS transistor Q45 turns on and Q46 turns off, VH is output from c.

The capacitor C34 holds the electric charge accumulated in the gate of the PMOS transistor 46, and acts so that the potential of the gate becomes higher than the power supply voltage by capacitive coupling. Therefore, the PMOS transistor Q46 can be reliably turned off.

Conversely, positive logic is applied to the gate of the PMOS transistor Q44, and the PMOS transistor Q4
When negative logic is applied to the gate of No. 3, the PMOS transistor Q43 is turned on, and a ground voltage (0 V) is applied from the ground to the gate of the PMOS transistor Q46. At this time, the capacitor C34 transfers the electric charge accumulated at the gate of the PMOS transistor 46 to the PMOS transistor 46.
The release at once via the transistor Q34 acts to sufficiently lower the gate potential of the PMOS transistor Q46. Therefore, the PMOS transistor Q46 can be turned on.

As described above, the tri-state circuit 91 of the present embodiment can be composed of only the PMOS transistor and the capacitor, so that the structure is simplified and the number of steps can be reduced, so that the cost can be reduced. Although the tristate circuits 71 and 81 are configured using PMOS transistors, they may be configured using NMOS transistors.

(Gate Driver) FIG. 11 is a diagram showing an example of a circuit configuration of a part of the gate driver 45 of FIG. The gate driver 45 shown in FIG.
132, 133 ... AND AND circuits 141, 14
.., Inverter circuits 151, 152,.

The latch circuits 131, 132, and 133 are provided with a vertical synchronizing signal (Y
SCL) and an inverted vertical synchronizing signal (￣YSCL) are input to the control signal input end (L) and the inverted control signal input end (￣L) every other phase with opposite phases. When "1" enters the section (L), the input signal is output as a through signal,
When "0" is entered, the previous input signal is latched.

As the input signal to the latch circuit 131, the YD clock and the inverted YD clock are input, and output signals corresponding to the through state and the latch state are output from the output terminal (O) and the inverted output terminal (￣O). Output and AND circuit 14
1 is input to the input terminal of the next-stage latch circuit 132.
Similarly, the output signal of the latch circuit 132 is input to the input terminals of the AND circuits 141 and 142 and the next-stage latch circuit 133.

The AND circuit 141 is connected to the output (OUT) of the latch circuit 131 and the latch circuit 13.
2 and the inverted output (￣OUT) of the inverter circuit 151 is input to the input terminal (IN) and the inverted input terminal (￣IN) of the inverter circuit 151. Then, from the output terminal of the inverter circuit 151, a scanning signal having a logic negation input from the input terminal (IN) is input to the gate line G.
1 is output. Further, from the output terminal of the inverter circuit 152, a scanning signal whose logic input from the input terminal (IN) is negated is output to the gate line G2.

FIG. 11 illustrates only a part of the configuration of the gate driver 45 that supplies two gate lines. The above circuits are arranged in accordance with the number of lines arranged in the vertical direction. I have. This allows each gate line to be line-scanned by a predetermined scanning method,
Each gate line is set to a selected state or a non-selected state.

As described above, the gate driver 45 constituted by the latch circuit, the AND circuit, and the inverter circuit
Can be configured using PMOS transistors of the same conductivity type as in the case of the drain driver 44 described above, so that the number of times of ion doping is reduced and the number of masks is reduced as compared with the case of configuring with CMOS transistors. Cost can be reduced.

(Inverter Circuit) FIG. 12 is a diagram showing an example of a circuit configuration of the inverter circuit 151 constituting the gate driver 45 of FIG. 11, and FIG. 13 is a diagram showing symbols of the inverter circuit 151 of FIG. is there. First, the configuration will be described. As shown in FIG.
1 is an inverter circuit 161 composed of PMOS transistors Q1, Q2, Q3 and a capacitor C1;
This is a combination of an inverter circuit 162 composed of OS transistors Q4, Q5, Q6 and a capacitor C2.

In the inverter circuit 161, an input (IN) is input to the gate of the PMOS transistor Q 2, and an inverted input (￣IN) is input to the gate of the PMOS transistor Q 3 via the PMOS transistor Q 1. In the inverter circuit 162, an input (IN) and an inverted input (１６IN) are input to the gates of the PMOS transistors Q5 and Q6 in a manner opposite to that of the inverter circuit 161.

Next, the operation will be described. The inverter circuit 151 in FIG. 12 has, for example, a negative logic “0” at the input (IN).
When positive logic “1” is input to the inverting input (入 力 IN), the PMOS transistor Q2 of the inverter circuit 161 turns on, and “1” is output from the power supply Vdd (OU).
T), and the PMOS transistor Q3 is turned off. Conversely, the inverter circuit 162 includes the PMOS transistor Q
5 is turned off, the PMOS transistor Q6 is turned on, and the ground level “0” is output as the inverted output (￣OUT).

Further, in the inverter circuit 151, when the logic of the input (IN) and the inverted input ($ IN) are opposite to the above, "0" is output from the output (OUT) side,
“1” is output from the inverted output (￣OUT) side.

As described above, when both the positive logic and the negative logic are input as the input and the inverted input, the inverter circuit 151 of the present embodiment outputs, as the output and the inverted output, the logic negating them.

The inverter circuit 15 of the present embodiment
1 is the PMOS transistor Q of the inverter circuit 161
3 or the PMOS transistor Q6 of the inverter circuit 162 is turned on, the ground level is output as an output or an inverted output, but as shown in FIG.
PMO is connected to the gates of the PMOS transistors Q3 and Q6.
S transistors Q1 and Q4 are provided.
Between the S-transistor Q1 and the output end, and the PMOS
Capacitors C1 and C2 each having a predetermined capacitance are arranged between the transistor Q4 and the inverted output terminal.

For this reason, when outputting a low level as an output or an inverted output, it is possible to prevent the low level from rising, so that the appropriate Vdd level “1” and the ground level “0” are output. Can be output as an output or an inverted output.

FIG. 13 is a circuit diagram of the inverter circuit 151 shown in FIG.
Are input to the input side of the inverter circuit 151 and an inverted input (￣) negating the input (IN).
IN), the output (OUT) whose input logic is inverted from the output side and the inverted output (出力 O)
UT) is output.

As described above, in the inverter circuit 151 shown in FIG. 12, for example, even when a plurality of inverter circuits are connected in series, the loss of the output level such that the low level rises is not observed, and Outputs proper ground level (0V) and power supply level (Vdd) (OU
T) or inverted output (￣OUT).

The inverter circuit 15 of the present embodiment
In No. 1, power consumption can be reduced since there is no output level loss and no DC leakage current as described above. In the above-described inverter circuit 151,
Although an example in which a circuit is configured with PMOS transistors is shown,
However, the present invention is not limited to this, and the entire TFT on the substrate may be formed of NMOS transistors.

As described above, in the thin-film semiconductor device of this embodiment, a driver circuit including a latch circuit and a shift register is configured using TFTs of the same conductivity type.
Since the number of times of ion doping is smaller than that of the conventional CMOS, the manufacturing cost can be reduced.

Further, the S / D can be obtained by forming the TFT of the switching element formed in the pixel portion into a multi-gate structure.
Since the withstand voltage can be increased, the leakage current can be reduced and the power consumption can be reduced. Further, the switching element TFT formed in the pixel portion is replaced with a multi-gate structure,
With the DD structure, the leakage current can be similarly reduced. This LDD structure can be formed by a single ion doping if a double mask is used as in the above embodiment.

In the above embodiment, the TFT adopting the multi-gate structure or the LDD structure has the same structure as the TFT of the pixel portion.
Although the FT is used, it is needless to say that the present invention is not limited to this, and a multi-gate structure or an LDD structure may be employed for a TFT constituting a liquid crystal driving circuit in order to prevent deterioration of a circuit transistor. Further, in the above embodiments (FIGS. 1 and 2), the transistor structure is implemented as a top gate coplanar structure. However, a bottom gate inverted stagger structure or another structure can be adopted.

According to the thin film semiconductor device of [0094] the present invention, the entire thin film transistor included in the thin film transistor circuit formed on a single substrate is composed of only one of the thin film transistor P-type or N-type, the thin film transistor circuit Lee
An inverter circuit, and the inverter circuit includes one of input / output terminals.
Are connected to each other via a capacitor, and the other is
The first thin film transistor connected to
A first thin film transistor connected to
The inverter circuit and one of the input / output terminals are connected via a capacitor.
Connected to each other and the other to a high potential.
A fourth transistor in which the membrane transistor and the other are connected to a low potential;
A second inverter circuit comprising a thin film transistor;
First thin film transistor and fourth thin film transistor
Means for applying a non-inversion signal to the second thin film transistor.
An inversion signal is applied to the transistor and the third thin film transistor.
And means for adding .

As described above, when the thin film transistor circuit is composed of P
Since it is composed of only a thin film transistor of either conductivity type or N type, the number of times of ion doping for implanting impurities and the number of masks are greatly reduced, and the manufacturing cost is reduced , and the transistor is reliably formed. switch
Power consumption and output level does not attenuate.
Inverter circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor of the same conductivity type according to this embodiment.

FIG. 2 is a diagram showing a manufacturing process of the thin film transistor of the same conductivity type according to the embodiment.

FIG. 3 is a diagram illustrating an ion doping step in the case where the same conductivity type thin film transistor according to this embodiment is formed with an LDD structure.

FIG. 4 is a drive circuit integrated TFT-L according to the present embodiment.
FIG. 1 is a schematic configuration diagram of a CD.

FIG. 5 is a diagram showing a circuit configuration example of a part of the drain driver of FIG. 4;

FIG. 6 is a diagram showing a circuit configuration example of a latch circuit forming the drain driver of FIG. 5;

FIG. 7 is a diagram showing an example of a circuit configuration of an AND circuit constituting the drain driver of FIG. 5;

FIG. 8 is a diagram showing symbols of the AND-AND circuit in FIG. 7;

FIG. 9 is a diagram showing a circuit configuration example of a tri-state circuit constituting the drain driver of FIG. 5;

FIG. 10 is a diagram showing symbols of the tri-state circuit of FIG. 9;

FIG. 11 is a diagram showing an example of a circuit configuration of a part of the gate driver shown in FIG. 4;

12 is a diagram illustrating an example of a circuit configuration of an inverter circuit included in the gate driver of FIG. 11;

FIG. 13 is a diagram showing symbols of the inverter circuit in FIG. 12;

FIG. 14 illustrates a configuration of a CMOS inverter circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 glass substrate 11 base transparent insulating film 12 amorphous silicon film 12 ′ polysilicon film 13 photoresist mask 13 A, 13 B, 13 C element region 14 silicon oxide film 15 silicon nitride film 16 metal chromium film (gate electrode) 17 pixel electrode 18 silicon nitride Film 19 S / D (source / drain)
Electrode 21 Element region 24 Channel region 25, 26 Low concentration impurity diffusion layer (P minus region) 27, 28 High concentration impurity diffusion layer (P plus region) 29, 29 'Silicon oxide film 30, 30' Photoresist 41 Drive circuit 1 Body type TFT-LC
D 42 liquid crystal display panel 43 TFT 44 drain driver 45 gate driver 46 glass substrate 50 shift register 51, 52, 53 latch circuit 61, 62 and NAND circuit 71, 72, 81, 82 latch circuit 91, 92 tristate circuit 101, 102 Inverter circuit 151 Inverter circuit 161, 162 Inverter circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 G02F 1/136 500 H03K 17/687 H03K 19/0944

Claims (5)

(57) [Claims] 1. A thin film transistor included in a thin film transistor circuit formed on one substrate is entirely P-type or N-type.
The TFT circuit is composed of only one type of conductive type thin film transistor.
Has signal input end and non-inverted and inverted signal output end
An inverter circuit, wherein the inverter circuit has a source
Rain is connected in series and each gate is
Inverted and inverted input signals are applied, and one of the
Connected to each other via a capacitor and the other connected to high potential
The first thin film transistor and the other
A first inverter comprising a continuous second thin film transistor
Data circuit and one of the input / output terminals
And the other is connected to a high potential.
Transistor and a fourth thin film transistor the other of which is connected to a low potential.
A second inverter circuit comprising a transistor;
The thin film transistor and the fourth thin film transistor
Means for applying an inversion signal, and said second thin film transistor
And applying an inversion signal to the third thin film transistor.
And a thin film semiconductor device. 2. The thin film transistor circuit includes a shift register circuit including a plurality of latch circuits.
A latch circuit including the inverter circuit;
The non-inverting output signal output end of the circuit and the non-inverting input signal
Means for connecting to the signal input end, and the inverted signal output end
2. The thin-film semiconductor device according to claim 1, further comprising: means for connecting the inverted signal input terminal to the inverted signal input terminal . 3. A large number of pixels on a substrate, each pixel being connected
Switching thin film transistor, and the thin film transistor
Display device with a drive circuit for driving the transistor
The switching thin film transistor formed on the substrate.
Thin-film transistors included in transistors and drive circuits
The entire film is a P-type or N-type conductive type thin film transformer.
And the drive circuit section is non-reactive.
Inverted and inverted input signal input end and non-inverted and inverted signal
An inverter circuit having an output terminal;
In the circuit, the source and drain are connected in series, and
Non-inverted and inverted input signals are applied to
One of the output terminals is connected to each other via a capacitor,
A first thin film transistor connected to a higher potential and
The other is from the second thin film transistor connected to a low potential
The first inverter circuit and one of the input / output terminals
Connected to each other via a capacitor and the other connected to high potential
The third thin film transistor and the other are connected to a low potential.
A second invar comprising a fourth thin film transistor connected
Data circuit, the first thin film transistor and a fourth thin film transistor.
Means for applying a non-inverted signal to the thin film transistor;
Second thin film transistor and third thin film transistor
Means for applying an inversion signal to the
Display device. 4. The driving circuit section includes a plurality of latch circuits.
Latch circuit including a shift register circuit comprising
Includes the inverter circuit, and includes the inverter circuit.
Non-inverted output signal output end and the non-inverted input signal input end
Means for connecting the inverted signal output terminal and the inverted signal
Having means for connecting to a signal input end.
The display device according to claim 3. 5. The thin-film transistor according to claim 1, wherein the semiconductor layer is a polysilicon.
5. The method according to claim 3, wherein the silicon is silicon.
Display device.