JP2928485B2 - Phase comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator used for a PLL circuit or the like built in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a phase lock loop circuit (hereinafter, referred to as a PLL circuit) is incorporated on one semiconductor substrate to reduce clock skew between the inside and the outside of the semiconductor integrated circuit and to make each circuit. The frequency of the clock supplied to is multiplied.

FIG. 7 is a block diagram showing a configuration example of a semiconductor integrated circuit having a built-in PLL circuit. 7, reference numeral 50 denotes a PLL circuit, which includes a phase comparator 51, a loop filter 5
2, voltage-controlled oscillator 53, and programmable frequency divider 5
4. Reference numeral 60 denotes a clock buffer, which transmits a clock signal output from the voltage controlled oscillator 53 to the functional blocks A61 and B62 in the semiconductor integrated circuit. The clock signal transmitted to the function block A61 is fed back to the programmable frequency divider 54, and the programmable frequency divider 54 inputs the reference clock signal _Fr to be subjected to the phase comparison to the phase comparator 51. Also, the reference clock signal F _p made by dividing the square wave external crystal oscillator is generated by the frequency divider, is input to the phase comparator 51.

The operation of the semiconductor integrated circuit having a built-in PLL circuit shown in FIG. 7 will be described. The frequency of the reference clock signal F _p to be inputted to the phase comparator 51 and f _1, the frequency of the clock signal fed back from the functional block A61 to the programmable frequency divider 54 and f _2. Voltage controlled oscillator 53, N times the reference clock signal F _p (N is an arbitrary natural number) to output a clock signal having a frequency of.
That is, the clock buffer 6
The frequency of the clock signal output to 0 is f ₁ × N. The programmable frequency divider 54 has a function block A61.
Divides the frequency f _{2 of the} clock signal output from the multiplexed signal by 1 / N, and outputs it to the phase comparator 51 as the reference clock signal _Fr.

When there is no phase difference between the reference clock signal F _p (frequency f ₁ ) and the reference clock signal _Fr (frequency f ₂ / N), the voltage controlled oscillator 53 outputs the frequency (f
Oscillation continues at ₁ × N). When the phase of the reference clock signal F _p and the reference clock signal F _r are different, the phase comparator 51 outputs a difference signal voltage corresponding to the phase difference between the two signals. This difference signal voltage is input to a voltage controlled oscillator 53 after a high frequency component is removed by a loop filter 52,
The oscillation frequency of the voltage controlled oscillator 53 is controlled. As long as the PLL circuit 50 operates normally, the voltage controlled oscillator 53
The frequency of the clock signal output from is kept constant at f ₁ × N. This is called a state where the PLL circuit is locked.

The clock signal output from the voltage controlled oscillator 53 is transmitted to each functional block via the clock buffer 60. That is, the semiconductor integrated circuit will be operated by a clock signal having a frequency N times that of the reference clock signal F _p to be supplied from the outside. Further, by equalizing the delay time to the reference clock signal F _r and the delay time of the reference clock signal F _p which is input from the outside is input to the phase comparator 51, the reduction of clock skew is achieved.

The conventional phase comparator includes a digital phase comparator for detecting a phase difference between two input pulse signals for each lead and lag, a charge pump circuit for changing an output voltage based on a detection result of the digital phase comparator, and (For example, refer to “PLL application circuit”, pages 136 to 139, published by Sogo Denshi Shuppansha on July 10, 1994).

FIG. 8 is a circuit diagram showing a configuration of a conventional phase comparator. In FIG. 8, reference numeral 30 denotes a digital phase comparator, and reference numeral 40 denotes a charge pump circuit.

The digital phase comparator 30 includes a reset circuit 31, a first flip-flop 32, a second flip-flop 33, a first three-input NAND circuit 34, a second three-input NAND circuit 35, and a first three-input NAND circuit 35. Inverter 36,
It comprises a first NAND circuit 37, a second inverter 38, and a second NAND circuit 39.

The reference clock signal _Fp is input to a first NAND circuit 37 via a first inverter 36, while the reference clock signal _Fr is input to a second NAND circuit 39 via a second inverter 38. Is entered. First NA
The output signal of the ND circuit 37 is the first flip-flop 3
Input to the two- and first three-input NAND circuit 34,
The output signal of the NAND circuit 39 is input to the second flip-flop 33 and the second three-input NAND circuit 35. The output signal of the first flip-flop 32 is input to a first three-input NAND circuit 34, and the second flip-flop 32
The output signal of the flop 33 is the second three-input NAND circuit 3
5 is input.

The reset circuit 31 outputs the output signals of the first flip-flop 32 and the second flip-flop 33 and the first NAND circuit 37 and the second NAND circuit 3.
9-input signal and a 4-input NAND circuit 31a
And this output signal is the first flip-flop 3
The reset signal is input to the second and second flip-flops 33 and is also input to the first three-input NAND circuit 34 and the second three-input NAND circuit 35.

[0012] From the first three-input NAND circuit 34, usually is "H", the first phase difference is between "L" of the phase of the reference clock signal F _p is ahead the reference clock signal F _r The detection signal _Pu is output. Second 3-input NAN
From D circuit 35, usually it is "H", the reference clock signal F _p second phase difference detection signal P _d which is between "L" phase is delayed from the reference clock signal F _r of outputs .

The charge pump circuit 40 includes a P-type MOS transistor 41, an N-type MOS transistor 42, and an inverter 43. The source of the P-type MOS transistor 41 is connected to the power supply, and the drain is connected to the source of the N-type MOS transistor 42. The drain of the N-type MOS transistor 42 is grounded. The gate of the P-type MOS transistor 41 has a first
, The first phase difference detection signal _Pu output from the three-input NAND circuit 34 is input, while the gate of the N-type MOS transistor 42 is connected to the second potential output from the second three-input NAND circuit 35. phase difference detection signal P _d is the inverter 43
Are inverted and input. The drain of the P-type MOS transistor 41 (the source of the N-type MOS transistor 42) is connected to the output terminal OUT.

When the first phase difference detection signal _Pu is "L", the P-type MOS transistor 41 is turned on, so that the potential of the drain of the P-type MOS transistor 41 (the potential of the output terminal OUT) increases. When the second phase difference detection signal _Pd is "L", the output signal of the inverter 43 becomes "H" and the N-type MOS transistor 42 is turned on, so that the source potential of the N-type MOS transistor 42 (output The potential of the terminal OUT) decreases. That is, the potential of the output terminal OUT will be reduced when they are elevated delay when the phase of the reference clock signal F _p is ahead the reference clock signal F _r. Therefore, the oscillation frequency of the voltage controlled oscillator 53 in FIG. 7 can be controlled by the output voltage of the phase comparator.

[0015]

However, the conventional phase comparator has the following problems.

FIG. 9 is a graph showing the input / output characteristics of the phase comparator. In the phase comparator, as shown in FIG.
It is desirable that the relationship between the phase difference between the two input signals and the output voltage has linearity. However, in practice, a minute phase difference cannot be detected as shown in FIG. 9B, and there is a dead zone of the phase difference, or the sensitivity is too high as shown in FIG. There may be continuous points.

It has been found that the length of the delay time in the reset circuit has a great effect on the input / output characteristics of the phase comparator. In other words, in order to improve the input / output characteristics of the phase comparator, it is necessary to optimize the delay time in the reset circuit. However, in the conventional phase comparator shown in FIG.
Since the ND circuit 31a is used, the delay time becomes shorter than an appropriate value, and the input / output characteristics as shown in FIG.

Various improvements have already been made to optimize the delay time of the reset circuit. For example, JP
According to the invention disclosed in 3-119318, 4-input N
The output of the reset signal is delayed by reducing the channel width of the transistor constituting the AND circuit.
According to the invention disclosed in U.S. Pat. No. 3,610,954, a plurality of capacitors are used as means for delaying the output of the reset signal. However, in the former case, in recent years when the gate width of the transistor has become less than μm, the yield is inevitably deteriorated due to variations in channel width and the like. In the latter case, there is a problem that the circuit scale of the phase comparator becomes large.

In addition, since the conventional phase comparator uses a four-input NAND circuit to generate a reset signal, there is a problem that it is difficult to operate stably with a low power supply voltage. For example, an NMO as a current source
Assuming that the threshold voltage of S is 0.7 V, a 4-input NAND
The power supply voltage must be (0.7+
Δ) × 4 = (2.8 + 4Δ) V or more is required (Δ is a minute value). At a power supply voltage lower than this, the NMOS is in a non-saturation region and becomes a resistance component, so that the delay time of the reset circuit becomes very long. Therefore, when the power supply voltage is low, the input / output characteristics as shown in FIG.

The charge pump circuit also has a factor that deteriorates input / output characteristics. FIG. 10 shows the reference clock signal F
₁₀ is a graph showing the input / output voltage of the inverter 43 when the phase of _p is slightly delayed from the reference clock signal _Fr. As shown in FIG.
Before it falls between from the rise of the reference clock signal F _r to the reference clock signal F _p rises, the phase difference between the two signals to reach the threshold voltage V _th of the inverter 43 for a negligible Rise again. At this time, since the output voltage B of the inverter 43 remains at 0 V, the output voltage of the phase comparator does not change even though the two input signals have a phase difference. That is, a minute phase difference cannot be detected. Moreover, since such a problem does not occur when the phase of the reference clock signal F _p advances than the reference clock signal F _r, unpreferably the detection accuracy by the phase lead lag different.

In view of the above problems, it is an object of the present invention to provide a phase comparator which has a small dead zone for phase difference, has excellent input / output characteristics, and can operate stably even at a low power supply voltage.

[0022]

In order to achieve the above object, the present invention provides a reset circuit by connecting a plurality of logic gates so as to optimize the delay time thereof and to provide a plurality of logic gates. Since the number of inputs is 3 or less, stable operation is possible at a lower power supply voltage than in the prior art.

Further, the present invention makes it possible to detect a minute phase difference by using a complementary transmission gate in which a phase difference detection signal and its inverted signal are input to two control terminals for a charge pump circuit. And the detection accuracy of the lead and lag of the phase is made equal.

Specifically, a first aspect of the present invention provides a first state holding circuit that receives a first pulse signal input from the outside and outputs a first state signal, A second state holding circuit that receives a second pulse signal to be input and outputs a second state signal;
A reset signal that generates a reset signal based on the first pulse signal and the first and second state signals, and outputs the generated reset signal to the first and second state holding circuits; A signal, a first state signal, and a reset signal, and outputting a first phase difference detection signal indicating that the phase of the first pulse signal is ahead of the phase of the second pulse signal. 1 the phase difference detection circuit and the second pulse signal, the second state signal, and the reset signal are input, and the phase of the first pulse signal is later than the phase of the second pulse signal. in the second phase difference detection circuit and the phase comparator having a to output a second phase difference detection signal indicating the reset circuit is constituted by logic gates of the plurality of stages the number of input is 3 or less And before Out of the first and second state hold circuit
A first logic gate receiving a force signal;
Output signal of the logical gate and the first and second pulse signals.
A second logic which receives the reset signal as an input and outputs the reset signal
And a gate .

According to the first aspect of the present invention, since the reset circuit for generating and outputting the reset signal is realized by a plurality of logic gates, the delay time of the reset circuit for determining the input / output characteristics of the phase comparator is optimized. Is done. Further, since the logic of the reset circuit, which has conventionally been realized by one 4-input NAND circuit, is realized by a logic gate having three inputs or less, the minimum power supply voltage required for stable operation is lower than in the past. .

[0026]

According to a second aspect of the present invention, in the phase comparator of the first aspect, the reset circuit has a two-input circuit that receives an inverted signal of the first state signal and an inverted signal of the second state signal. It is assumed that the circuit includes a NOR circuit, and a three-input NAND circuit which receives an output signal of the two-input NOR circuit and the first and second pulse signals and outputs the reset signal.

According to the third aspect of the present invention, in the first aspect,
A phase comparator having a charge pump circuit that receives the first and second phase difference detection signals as input, and outputs a voltage indicating lead / lag of the phase of the first and second pulse signals. I do.

[0029] In the invention of claim 4, wherein the claim
In the charge pump circuit of the phase comparator of ( 3 ), one terminal is connected to a power supply, the first phase difference detection signal is inputted to one control terminal, and the first phase difference is inputted to another control terminal. A complementary first transmission gate to which an inverted signal of the detection signal is input, one terminal connected to the other terminal of the first transmission gate, and the other terminal grounded;
And a complementary second transmission gate to which one control terminal receives the second phase difference detection signal and another control terminal receives an inverted signal of the second phase difference detection signal. The voltage at the connection point between the other terminal of the first transmission gate and one terminal of the second transmission gate is output.

[0030] According to the fourth aspect of the present invention, when the phase of the first pulse signal is advanced than the second pulse signal,
The complementary first transmission gate is turned on by the first phase difference detection signal and its inverted signal, and the output voltage of the charge pump circuit increases. When the phase of the first pulse signal is later than the phase of the second pulse signal, the second phase difference detection signal and its inverted signal are used to generate a complementary second signal.
, And the output voltage of the charge pump circuit decreases. Since each transmission gate is controlled by the phase difference detection signal and its inverted signal, the output voltage of the charge pump circuit changes even if the phase difference is small and the change in the first and second phase difference detection signals is small. . Also,
The lead and lag of the phases of the input first pulse signal and second pulse signal can be detected equally.

Further, according to the invention of claim 5 , the above-mentioned claim is provided.
In the charge pump circuit in the phase comparator of No. 4, the first phase difference detection signal is output from the first phase difference detection circuit to the input terminal of one of the first transmission gates. The time required is equal to the time required for the first phase difference detection signal to be inverted after being output from the first phase difference detection circuit and to be input to another control terminal of the first transmission gate. The first delay time adjusting means provided between the first phase difference detection circuit and one control terminal of the first transmission gate, and the second phase difference detection signal is the second phase difference detection signal. 2 from the output of the second phase difference detection circuit to the input of one control terminal of the second transmission gate, the second phase difference detection signal from the second phase difference detection circuit Output and then inverted for the second transmission A second phase difference detection circuit and a second control terminal provided between the second transmission gate and one control terminal of the second transmission gate so as to be equal to a time required for input to another control terminal of the second transmission gate. And delay time adjusting means.

According to the fifth aspect of the present invention, the timing at which the phase difference detection signal input to one control terminal of the transmission gate changes and the inverted signal of the phase difference detection signal input to the other control terminal of the transmission gate are changed. Since the change timing coincides, it is possible to prevent output voltage ripple that occurs when the charge pump circuit is driven.

According to a sixth aspect of the present invention, as a phase comparator, the phase comparator compares the phases of a first pulse signal and a second pulse signal which are input from the outside. A first phase difference detection signal indicating that the phase of the pulse signal is ahead of the phase of the second pulse signal, and the phase of the first pulse signal is later than the phase of the second pulse signal. A digital phase comparator that outputs a second phase difference detection signal indicating that the first and second
A charge pump circuit that receives the phase difference detection signal as an input and outputs a voltage indicating the lead and lag of the phase of the first and second pulse signals. The charge pump circuit has one terminal connected to a power supply, A complementary first transmission gate having one control terminal receiving the first phase difference detection signal and another control terminal receiving an inverted signal of the first phase difference detection signal; Is connected to the other terminal of the first transmission gate, and the other terminal is grounded;
And a complementary second transmission gate to which one control terminal receives the second phase difference detection signal and another control terminal receives an inverted signal of the second phase difference detection signal. the first Ri <br/> Oh voltage at the connection point between one terminal of the other terminal of the transmission gate and the second transmission gate in which the output, and the first phase difference detection The signal is the digital
The first transmission gate after being output from the phase comparator
The time required for input to one control terminal is
A first phase difference detection signal from the digital phase comparator;
The output is inverted and then inverted to another of the first transmission gates.
It will be equal to the time required to input to the control terminal
The digital phase comparator and the first transmission gate
Delay time adjustment provided between one of the control terminals
Means, and the second phase difference detection signal is provided at the digital position.
After being output from the phase comparator, one of the second transmission gates
The time required for input to the control terminal of the second
Is output from the digital phase comparator.
Other control of the second transmission gate
So that it is equal to the time required for input to the terminal
One of the digital phase comparator and the second transmission gate;
Delay time adjusting means provided between the control terminal and the control terminal
And that

According to the invention of claim 6 , when the phase of the first pulse signal is ahead of the second pulse signal, the first
The complementary first transmission gate is turned on by the phase difference detection signal and its inverted signal, and the output voltage of the charge pump circuit rises. When the phase of the first pulse signal is later than the phase of the second pulse signal, the complementary second transmission gate is turned on by the second phase difference detection signal and its inverted signal, and the charge pump is turned on. The output voltage of the circuit drops. Since each transmission gate is controlled by the phase difference detection signal and its inverted signal, the output voltage of the charge pump circuit changes even if the phase difference is small and the change in the phase difference detection signal is small. Further, it is possible to equally detect the lead and lag of the phases of the input first pulse signal and second pulse signal. In addition, the transmission gate
Timing when the phase difference detection signal input to the control terminal changes
Phase difference input to other control terminal of transmission and transmission gate
The timing when the inverted signal of the signal changes coincides
Output that occurs when the charge pump circuit is driven.
It is possible to prevent a ripple in the output voltage.

[0035]

[0036]

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A phase comparator according to one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a digital phase comparator constituting the phase comparator according to the present embodiment. FIG.
As shown in the figure, the digital phase comparator comprises a reset circuit 11, a first flip-flop 12 as a first state holding circuit, a second flip-flop 13 as a second state holding circuit, The first as a phase difference detection circuit
, A second three-input NAND circuit 15 as a second phase difference detection circuit, a first inverter 16, a first NAND circuit 17, and a second inverter 1.
8 and a second NAND circuit 19. The difference from the conventional digital phase comparator is that the reset circuit 11 includes a two-input NOR circuit 11a and a three-input NAND circuit 11b.

A reference clock signal F _p as a first pulse signal is supplied to a first NAND 16 via a first inverter 16.
While the input to the circuit 17, the reference clock signal F _r as the second pulse signal is input to the second NAND circuit 19 through the second inverter 18. First NAND
One output signal of the circuit 17 (a reference clock signal F _p and is substantially the same) is input to the first flip-flop 12 and the first 3-input NAND circuit 14, a second NA
The output signal of the ND circuit 19 (substantially the same as the reference clock signal _Fr ) is input to the second flip-flop 13 and the second three-input NAND circuit 15. Output signal S _{1 of} first flip-flop 12 (first state signal)
Is input to the first three-input NAND circuit 14, while the output signal S ₂ (second state signal) of the second flip-flop 13 is input to the second three-input NAND circuit 15. The reset circuit 11 includes a first flip-flop 1
2 and the inverted output signal of the second flip-flop 13 /
A two-input NOR circuit 11a having S ₁ and / S ₂ as inputs,
A three-input NAND circuit 11b receives the output signal of the two-input NOR circuit 11a and the output signals of the first NAND circuit 17 and the second NAND circuit 19, and the output signal _Sr is _supplied to the first flip-flop. The reset signal is input to the flop 12 and the second flip-flop 13 and is also input to the first three-input NAND circuit 14 and the second three-input NAND circuit 15.

[0040] From the first three-input NAND circuit 14, a first phase difference normally is between "H" and is the reference clock signal F _p is advanced in phase than the reference clock signal F _r "L" The detection signal _Pu is output. Second 3-input NAN
From D circuit 15, the second phase difference detection signal P _d is output as a between "L" the phase is delayed from the reference clock signal F _p is the reference clock signal F _r is usually a "H" .

In the digital phase comparator shown in FIG. 1, an internal circuit operates in response to rising edges of two input signals, and does not depend on a duty cycle or an amplitude.
Further, since the sequential circuit includes the storage circuit, the output signal is determined by the input signal and the state of the internal circuit before the input signal is supplied.

[0042]

[Table 1]

Table 1 is a flow table showing the operation of the digital phase comparator shown in FIG. In Table 1, a number with [] indicates a stable state. For example,
F (i.e. if the reference clock signal F _p and the reference clock signal F _r are both "H") _p -F when _r is 1-1, the digital phase comparator [1], [5] or [9] Stable in any state. In the state [1], (P _u , P _d ) = (0, 1), and the first phase difference detection signal P _u is “L” and the second phase difference detection signal P _d is “H”. Become. Similarly, when the state is [5] (P _u ,
P _d ) = (1, 1), and in the state [9], (P _u ,
P _d ) = (1, 0). Also, the numbers without [] indicate an unstable state.
Transition to the stable state of the same number with.

Similarly, when F _p −F _r is 1-0 (ie, when the reference clock signal F _p is “H” and the reference clock signal _Fr is “L”), the digital phase comparator [2], [6] or stable in one of two states: [10], F _p -F when _r is 0-0 (i.e. the reference clock signal F _p and the reference clock signal F _r are both "L"
When it is), [3], reference is [7] or stable in one of two states: [11], when F _p -F _r is 0-1 (i.e. the reference clock signal F _p is "L" (When the clock signal _Fr is "H") [4], [8] or [12]
Stable in any state. In the states [2] to [4], (P _u , P _d ) = (0, 1), and the states [6] to [4]
In the case of [8], (P _u , P _d ) = (1, 1), and in the states [10] to [12], (P _u , P _d ) = (1, 0)
Becomes

FIG. 2 is a timing chart showing the operation of the digital phase comparator. Taking FIG. 2 (a) as an example,
The operation of the digital phase comparator will be described.

First, it is assumed that the input F _p -F _r is 0-0 and is stable in the state [7]. At this time, the output (P _u , P
_d ) = (1, 1). Input F _p -F _r and the reference clock signal F _p rises changes to 1-0, but the state 2 moves to the left in Table 1, the state 2 is moved in the vertical direction for unstable stable state Shift to [2]. For this reason,
Output _{(P u, P d) =} (0,1) , and the only falls first phase difference detection signal P _u. Then the reference clock signal F _r and rises input F _p -F _r is changed to 1-1, although the state 5 moves to the left in Table 1, the state 5 is moved in the vertical direction for unstable Transit to stable state [5]. Therefore, the output _{(P u, P d) =} (1,1) , and the first phase difference detection signal P _u rises again.

Next, the input F _p -F _r and the reference clock signal F _p is falling has changed to 0-1, although the state 8 moves to the right in Table 1, the state 8 is unstable for vertical To the stable state [8]. Therefore, the output (P _u , P _d ) = (1, 1) does not change. Then the reference clock signal F _r is falls as the input F _p -F _r is changed to 0-0, although the state 7 moves to the left in Table 1, the state 7 is moved in the vertical direction for unstable To a stable state [7]. Therefore, the output (P _u , P _d ) =
(1, 1) and does not change.

[0048] Consequently, as shown in FIG. 2 (a), only during the phase of the reference clock signal F _p is ahead the reference clock signal F _r, a first phase difference detection signal P _u is the "L" Become. The second phase difference detection signal _Pd always remains "H". Therefore, according to the first phase difference detection signal _Pu ,
The phase of the reference clock signal F _p it is possible to detect whether advanced than the reference clock signal F _r.

Further, as shown in FIG. 2 (b), the second phase difference detection signal P _d only during the phase of the reference clock signal F _p is delayed from the reference clock signal F _r since become "L" , the second phase difference detection signal P _d, can detect whether the phase of the reference clock signal F _p is delayed from the reference clock signal F _r. Further, as shown in FIG.
Reference frequency of the reference clock signal F _p clock signal F _r
Even when it is higher, it can be detected by the first phase difference detection signal _Pu .

Here, in this embodiment, the reset circuit 1
1 is a two-input NOR circuit 11a and a three-input NAND circuit 1
1b. As described in the section of the problem, although the delay time in the reset circuit has a great effect on the input / output characteristics of the phase comparator, the same logic as that of the conventional four-input NAND circuit is implemented here by a two-stage logic circuit. By realizing, the delay time can be optimized. Therefore, it is possible to realize a phase comparator having a small dead zone of the phase difference and having excellent input / output characteristics. Moreover, unlike the conventional improvement, it is not necessary to reduce the channel width of the transistor, so that the yield does not deteriorate due to variations in the channel width and the like, and the circuit scale of the phase comparator increases because there is no need to use a plurality of capacitors. Never.

Further, since a four-input NAND circuit is not used for the reset circuit, the phase comparator can be operated stably with a lower power supply voltage than the conventional one. For example, the power supply voltage for stably operating the conventional phase comparator is such that the threshold voltage of the NMOS as a current source is 0.7 V (0.
7 + Δ) × 4 = (2.8 + 4Δ) V or more, but in the present embodiment, the power supply voltage for normally driving the three-input NAND circuit, that is, (0.7 + Δ) × 3 =
If a power supply voltage of (2.1 + 3Δ) V or more is supplied, the phase comparator can operate stably.

The reset circuit 11 in the phase comparator according to the present invention is not limited to the configuration shown in FIG. 1, but includes a plurality of stages of logic gates having the same circuit logic and three or less inputs. Any configuration can be used. FIG. 3 is a diagram showing an example of the configuration of the reset circuit 11 in the phase comparator according to the present invention, where (a) is the same circuit as that shown in FIG.
(D) is a circuit of the modified example. As shown in FIG.
A reset circuit having an appropriate delay time may be configured so that the input / output characteristics of the phase comparator become appropriate.

FIG. 4 is a circuit diagram showing a charge pump circuit constituting the phase comparator according to the present embodiment. In FIG. 4, reference numeral 21 denotes a complementary first transmission gate, reference numeral 22 denotes a complementary second transmission gate, and one terminal of the first transmission gate 21 is connected to a power supply, while the other terminal is connected to a power supply. It is connected to one terminal of the second transmission gate 22 and to the output terminal OUT of the charge pump circuit. The other terminal of the second transmission gate 22 is grounded.

The first output from the digital phase comparator
Of the phase difference detection signal P _u, the first transmission gate through a third transmission gate 23 as a first delay time adjustment unit 2
1 Pch gate. Third transmission gate 23
Is always conductive because the Nch gate is connected to the power supply and the Pch gate is grounded. Further, the first phase difference detection signal _Pu is inverted by the inverter 25 and input to the Nch gate of the second transmission gate 21.

The second output from the digital phase comparator
Phase difference detection signal P _d in is inverted by the inverter 26 is input to the Nch gate of the second transmission gate 22.
The signal is also input to the Pch gate of the second transmission gate 22 via the fourth transmission gate 24 as the second delay time adjusting means. The fourth transmission gate 24 is always conductive because the Nch gate is connected to the power supply and the Pch gate is grounded.

Regarding the charge pump circuit shown in FIG.
The operation will be described.

[0057] When the phase of the reference clock signal F _p is more advanced reference clock signal F _r, a first phase difference detection signal P _u
Becomes "L". At this time, P of the first transmission gate 21
An “L” level voltage is applied to the ch gate, and an “H” level voltage is applied to the Nch gate. Therefore, the first
Of the transmission terminal 21 is turned on, so that the output terminal OU
The potential of T rises.

[0058] Further, when the phase of the reference clock signal F _p is delayed from the reference clock signal F _r, the second phase difference detection signal P _d becomes "L". At this time, the first transmission gate 2
A low-level voltage is applied to the Pch gate of N2, and Nch
An “H” level voltage is applied to the ch gate. Therefore, the second transmission gate 22 is turned on, and the potential of the output terminal OUT decreases.

According to the present embodiment, the first transmission gate 21 using the first phase difference detection signal _Pu and its inverted signal as a control signal and the second phase difference detection signal _Pd and its inverted signal as control signals Since the charge transfer circuit is constituted by the second transmission gate 22 and the detection accuracy, there is no difference in detection accuracy due to the phase advance / delay.

Further, even when the phase difference between the reference clock signal _Fp and the reference clock signal _Fr is extremely small, the phase difference can be detected. For example, when the phase of the reference clock signal F _p is slightly delayed from the reference clock signal F _r, which may change in the second phase difference detection signal P _d does not reach the threshold voltage V _th of the smaller inverter 26 . In this case, although the output voltage of the inverter 26 does not change, the Pch gate of the second transmission gate 22 so that the second phase difference detection signal P _d is transmitted through the fourth transmission gate 24 of the second Transmission gate 22 becomes conductive and output terminal O
The potential of the UT will drop.

The effect of the charge pump circuit according to the present embodiment shown in FIG. 4 will be specifically described using simulation results. Figure 5 is a graph showing simulation results of the embodiment and the output voltage of the conventional charge pump circuit when the pulse width of the second phase difference detection signal P _d is very small. In the figure, (a) shows a pulse width of 100p.
It s about the second phase difference detection signal P _d (i.e. when the phase of the reference clock signal F _p is delayed by about 100ps from the phase of the reference clock signal F _r), the shown in (b) is (a) Figure 2. when a phase difference detection signal P _d is input 4
The output voltage of the charge pump circuit according to the present embodiment shown in, (c) the output of a conventional charge pump circuit shown in FIG. 8 when entered the second phase difference detection signal P _d shown in (a) Shows voltage. The simulation conditions are
It is as follows. P-type MOS transistor ... drain current I _d = 150μA (including Pch gate) gate width W = 8 [mu] m gate length L = 0.5 [mu] m N-type MOS transistor ... drain current I _d = 300μA (including Nch gate) gate width W = 4 μm Gate length L = 0.5 μm Transistor threshold voltage... 0.7 V

As can be seen from FIG. 5, according to the present embodiment, it is possible to detect a small phase difference of about 100 ps, which has not been detected conventionally. The performance of the phase comparator is reflected in the phase error of the PLL circuit. If the dead zone of the phase comparator is a (ps) and the jitter of the voltage controlled oscillator is b (ps), the phase error of the PLL circuit is (a + b). The setup margin between the inside of the chip and the external device is set according to the phase error of the PLL circuit. When the clock frequency is several tens to several hundreds MHz or more, the clock cycle takes a value of about several ns. Like 100
When a phase difference of about ps can be detected, the operation margins of the internal chip and the external chip can be relatively significantly reduced.

Further, by the third transmission gate 23,
The first phase difference detection signal P _u is first one of the control time required for the input to the terminal a first transmission gate 21 of the phase difference detection signal P _u is inverted the first transmission gate 21
And the fourth transmission gate 24 outputs the second phase difference detection signal _Pd to the first transmission gate 22.
The time required for input to one control terminal is equal to the time required for the second phase difference detection signal _{Pd to} be inverted and input to another control terminal of the second transmission gate 22. Like that. Thereby, the output terminal OU
Ripple of the potential of T can be prevented.

FIG. 4 shows the first phase difference detection signal P _u.
And the charge pump circuit when the second phase difference detection signal _Pd is normally "H" and becomes "L" when the phase difference is detected, but the first phase difference detection signal Pd _u
And the second phase difference detection signal P _d are both or be made of the "H" when either one normally detects a is the phase difference "L", the is present invention is of course feasible . FIG. 6 shows the first phase difference detection signal _Pu and the second phase difference detection signal _Pu .
3 is a circuit diagram showing a configuration of a charge pump circuit according to the present invention when both of the phase difference detection signals _Pd are normally “L” and become “H” when a phase difference is detected. As shown in FIG. 6, in this case, the first phase difference detection signal _Pu becomes the third phase difference detection signal _Pu .
Nch of the first transmission gate 21 through the transmission gate 23
While that is input to the gate, the inverted signal of the first phase difference detection signal P _u is input to the Pch gate of the first transmission gate 21, a second phase difference detection signal P _d is the fourth transmission gate while that is input to the Nch gate of the second transmission gate 22 through 24, as an inverted signal of the second phase difference detection signal P _d is input to the Pch gate of the second transmission gate 22, a charge pump What is necessary is just to comprise a circuit.

As described above, according to the phase comparator according to the present embodiment, the reset circuit of the digital phase comparator is constituted by the two-input NOR circuit and the three-input NAND circuit. As a result, the dead zone of the phase difference becomes smaller than before, and the input / output characteristics are improved. Further, since the entire digital phase comparator is constituted by a logic circuit having three inputs or less, it is possible to operate stably at a power supply voltage lower than the conventional one.

Further, since the charge pump circuit is constituted by a transmission gate using a phase difference detection signal and its inverted signal as a control signal, it is possible to detect a minute phase difference and to have the same detection accuracy for leading and lagging phases. Can be obtained. By using such a phase comparator, a PLL circuit with small jitter can be realized.

The digital phase comparator according to the present embodiment shown in FIG. 1 can be used alone as a phase comparator.

[0068]

As described above, according to the present invention, the delay time of the reset circuit for determining the input / output characteristics of the phase comparator is optimized, so that the dead zone of the phase difference is reduced and the linearity of the input / output characteristics is improved. Is done. Further, since the reset circuit is constituted by a logic circuit having three inputs or less, it is possible to operate stably even with a power supply voltage lower than the conventional one.

Further, since the output voltage of the charge pump circuit changes even if the first and second phase difference detection signals change little, even a minute phase difference can be detected. And the lead and lag of the phase of the second pulse signal can be detected equally.

Furthermore, it is possible to prevent the output voltage from being rippled when the charge pump circuit is driven.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a digital phase comparator according to one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the digital phase comparator according to one embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an example of a configuration of a reset circuit.

FIG. 4 is a circuit diagram of a charge pump circuit according to one embodiment of the present invention.

Figure 5 is a graph showing the effect of the charge pump circuit shown in FIG. 4, (a) is a graph showing the change of the second phase difference detection signal P _d, (b) a second as shown in (a) graph showing changes in the output voltage of the charge pump circuit shown in Figure 4 when the phase difference detection signal P _d is inputted, (c) has been entered a second phase difference detection signal P _d shown in (a) 6 is a graph showing a change in output voltage of the conventional charge pump circuit at the time.

FIG. 6 is a circuit diagram showing another configuration example of the charge pump circuit according to one embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a general PLL circuit.

FIG. 8 is a circuit diagram of a conventional phase comparator.

FIG. 9 is a graph showing input / output characteristics of the phase comparator.

FIG. 10 is a timing chart for explaining a problem of the conventional phase comparator.

[Description of Signs] 11 Reset circuit 11a 2-input NOR circuit 11b 3-input NAND circuit 12 First flip-flop (first state holding circuit) 13 Second flip-flop (second state holding circuit) 14th 1 three-input NAND circuit (first phase difference detection circuit) 15 second three-input NAND circuit (second phase difference detection circuit) _Fp reference clock signal (first pulse signal) _Fr reference clock signal ( Second pulse signal) _Pu First phase difference detection signal _Pd Second phase difference detection signal _Sr Reset signal S1 _First state signal S2 _Second state signal 21 First transmission gate 22 First 2 transmission gate 23 third transmission gate (first delay time adjusting means) 24 fourth transmission gate (second delay time adjusting means) 25, 26 inverter

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-177027 (JP, A) JP-A-7-143002 (JP, A) JP-A-7-30417 (JP, A) JP-A-6-176 132817 (JP, A) JP-A-6-216767 (JP, A) JP-A-64-69122 (JP, A) JP-A-3-297217 (JP, A) (58) Fields investigated (Int. ⁶ , DB name) H03L 7/06-7/199 G01R 25/00 H03K 5/26

Claims (6)

(57) [Claims] A first state holding circuit for receiving a first pulse signal input from the outside and outputting a first state signal; and a second pulse signal for receiving a second pulse signal input from the outside; 2
A second state holding circuit that outputs the first and second pulse signals, and the first and second pulse signals, and the first and second state signals.
A reset circuit that generates a reset signal based on the state signal of (1), and outputs the generated reset signal to the first and second state holding circuits; and the first pulse signal, the first state signal, and the reset signal. And the phase of the first pulse signal is
A first phase difference detection circuit that outputs a first phase difference detection signal indicating that the phase signal is advanced from the phase of the pulse signal, and the second pulse signal, the second state signal, and the reset signal. , The phase of the first pulse signal is the second
And a second phase difference detection circuit that outputs a second phase difference detection signal indicating that the phase of the pulse signal is delayed from the phase of the pulse signal. It is composed of a plurality of logic gates , and receives output signals of the first and second state holding circuits as inputs.
A first logic gate, an output signal of the first logic gate, and the first and second logic gates.
2 is input and the reset signal is output.
And a second logic gate . 2. The phase comparator according to claim 1, wherein the reset circuit includes a two-input NOR circuit that receives an inverted signal of the first state signal and an inverted signal of the second state signal. A phase comparator, comprising: a three-input NAND circuit which receives an output signal of the two-input NOR circuit and the first and second pulse signals and outputs the reset signal. 3. The phase comparator according to claim 1, wherein the first and second phase difference detection signals are input, and a voltage indicating a lead / lag of a phase of the first and second pulse signals is output. A phase comparator, comprising: 4. The phase comparator according to claim 3 , wherein the charge pump circuit has one terminal connected to a power supply, and one control terminal receiving the first phase difference detection signal. A complementary first transmission gate to which an inverted signal of the first phase difference detection signal is input to another control terminal; and one terminal is connected to another terminal of the first transmission gate. The other terminal is grounded, and one control terminal receives the second phase difference detection signal and the other control terminal receives an inverted signal of the second phase difference detection signal. 2. A phase comparator comprising: a second transmission gate; and a voltage output at a connection point between another terminal of the first transmission gate and one terminal of the second transmission gate. 5. The phase comparator according to claim 4 , wherein the charge pump circuit comprises a first transmission gate after the first phase difference detection signal is output from the first phase difference detection circuit. The time required for input to one of the control terminals is inverted after the first phase difference detection signal is output from the first phase difference detection circuit, and the other control of the first transmission gate is performed. So that the time required for input to the terminal is equal to the first time.
A first delay time adjusting means provided between the phase difference detection circuit and one control terminal of the first transmission gate, and wherein the second phase difference detection signal is provided by the second phase difference detection circuit. The time required from the output of the second transmission gate to the input to one control terminal of the second transmission gate is inverted after the second phase difference detection signal is output from the second phase difference detection circuit. The second transmission gate is controlled so as to be equal to the time required for input to another control terminal of the second transmission gate.
And a second delay time adjusting means provided between the phase difference detecting circuit and one control terminal of the second transmission gate. 6. The phase of a first pulse signal and the phase of a second pulse signal input from the outside are compared, and the phase of the first pulse signal is advanced from the phase of the second pulse signal. A first phase difference detection signal indicating that the
A digital phase comparator that outputs a second phase difference detection signal indicating that the phase of the pulse signal is behind the phase of the second pulse signal; A charge pump circuit that outputs, as an input, a voltage indicating the lead and lag of the phase of the first and second pulse signals, wherein the charge pump circuit has one terminal connected to a power supply, and one control terminal A first transmission gate of a complementary type in which the first phase difference detection signal is input to the other control terminal and an inverted signal of the first phase difference detection signal is input to another control terminal; One of the transmission gates is connected to the other terminal, the other terminal is grounded, the one control terminal receives the second phase difference detection signal, and the other control terminal receives the second signal. An inverted signal of the phase difference detection signal is input And a complementary second transmission gate, which outputs a voltage at a connection point between another terminal of the first transmission gate and one terminal of the second transmission gate.
And the first phase difference detection signal is the digital phase comparator
And a control terminal of the first transmission gate.
The time required for input to the input terminal is the first phase difference.
Whether the detection signal is output from the digital phase comparator
And inverted to the other control terminal of the first transmission gate.
To ensure that the time it takes
Digital phase comparator and one control terminal of the first transmission gate
First delay time adjusting means provided between the digital phase comparator and the digital phase comparator.
From one of the control terminals of the second transmission gate
The time required for input to the input terminal is the second phase difference
Whether the detection signal is output from the digital phase comparator
And then input to the other control terminal of the second transmission gate.
To be equal to the time required until the force, the di
A digital phase comparator and one control end of the second transmission gate
And second delay time adjusting means provided between the
A phase comparator, characterized in that is.