JP2917348B2 - Method of manufacturing MIS type semiconductor device - Google Patents
Method of manufacturing MIS type semiconductor deviceInfo
- Publication number
- JP2917348B2 JP2917348B2 JP479590A JP479590A JP2917348B2 JP 2917348 B2 JP2917348 B2 JP 2917348B2 JP 479590 A JP479590 A JP 479590A JP 479590 A JP479590 A JP 479590A JP 2917348 B2 JP2917348 B2 JP 2917348B2
- Authority
- JP
- Japan
- Prior art keywords
- refractory metal
- polycrystalline silicon
- film
- gate electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 239000003870 refractory metal Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 17
- 229910052719 titanium Inorganic materials 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 5
- -1 argon ions Chemical class 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 15
- 229910052698 phosphorus Inorganic materials 0.000 description 15
- 239000011574 phosphorus Substances 0.000 description 15
- 229910021341 titanium silicide Inorganic materials 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 150000003609 titanium compounds Chemical class 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、シリコン表面に高融点金属シリサイドを選
択的に形成した半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device in which a refractory metal silicide is selectively formed on a silicon surface.
[従来の技術] 従来のシリコンの表面にチタンシリサイドを選択的に
形成した構造を有する半導体装置の製造方法において、
特にゲート電極として多結晶シリコンを用い該ゲート電
極の多結晶シリコンの表面にチタンシリサイドを形成す
る半導体装置の製造方法においては、多結晶シリコンに
導電性をもたすために多結晶シリコン中に不純物として
燐を拡散していたがこの燐濃度が多くなって多結晶シリ
コン中に過飽和になってくるとチタンとシリコンの反応
が抑制されシリサイドになり難くなるため、従来技術の
半導体装置の製造方法では多結晶シリコン中に拡散する
燐の濃度を低くしていた。[Prior Art] In a conventional method of manufacturing a semiconductor device having a structure in which titanium silicide is selectively formed on the surface of silicon,
In particular, in a method of manufacturing a semiconductor device in which polycrystalline silicon is used as a gate electrode and titanium silicide is formed on the surface of the polycrystalline silicon of the gate electrode, impurities are contained in the polycrystalline silicon in order to impart conductivity to the polycrystalline silicon. However, when the phosphorus concentration is increased and becomes supersaturated in the polycrystalline silicon, the reaction between titanium and silicon is suppressed and it becomes difficult to form silicide. The concentration of phosphorus diffused into the polycrystalline silicon was reduced.
[発明が解決しようとする課題及び目的] しかしながら前述の従来技術の製造方法を用いて相補
型のMIS型トランジスタを形成すると、ゲート電極とし
ての多結晶シリコン中の燐濃度が低いタメ、Pチャンネ
ル側にソース・ドレインにする不純物拡散層を形成する
ときに注入されるP型の不純物であるホウ素がゲート電
極中にも注入されるためN型の不純物の燐が発生するキ
ャリアとしての電子数が減少しゲート電極の抵抗が高く
なったり、トランジスタのスイッチング特性であるしき
い値電圧が変化する問題を有していた。またゲート電極
中のキャリアの濃度が低いため多結晶シリコン表面に形
成したチタンシリサイドと多結晶シリコンの接触抵抗も
高くなり半導体装置の動作不良の原因になることや半導
体装置の高速動作をできなくする問題点を有していた。[Problem and Object to be Solved by the Invention] However, when a complementary MIS transistor is formed by using the above-described conventional manufacturing method, the phosphorus concentration in the polycrystalline silicon as the gate electrode is low and the P channel side is low. The boron, which is a P-type impurity implanted when an impurity diffusion layer serving as a source / drain is formed, is also implanted into a gate electrode, thereby reducing the number of electrons as carriers for generating N-type impurity phosphorus. However, there has been a problem that the resistance of the gate electrode is increased and a threshold voltage which is a switching characteristic of the transistor is changed. In addition, since the carrier concentration in the gate electrode is low, the contact resistance between titanium silicide formed on the polycrystalline silicon surface and the polycrystalline silicon increases, which may cause a malfunction of the semiconductor device and prevent the semiconductor device from operating at high speed. Had problems.
そこで、本発明はこのような課題を解決しようとする
もので、その目的とするところは、ゲート電極としての
多結晶シリコン表面に高融点金属シリサイドを自己整合
的に形成し同時にゲート電極の配線抵抗の増加やトラン
ジスタのしきい値電圧の変化、高融点金属シリサイドと
多結晶シリコンの接触抵抗の増加を抑えた半導体装置の
製造方法を提供するところにある。Therefore, the present invention is intended to solve such a problem, and an object of the present invention is to form a refractory metal silicide in a self-aligned manner on the surface of polycrystalline silicon as a gate electrode, and at the same time, to reduce the wiring resistance of the gate electrode. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the increase in the threshold voltage of the transistor, the change in the threshold voltage of the transistor, and the increase in the contact resistance between the refractory metal silicide and the polycrystalline silicon are suppressed.
[課題を解決するための手段] 本発明のMIS型半導体装置の製造方法は、 露出したシリコン表面に高融点金属のシリサイドを自
己整合的に形成するMIS型半導体装置の製造方法におい
て、 半導体基板上にゲート絶縁膜を介して多結晶シリコン
膜を形成する工程と、 前記多結晶シリコン膜中に第1導電型の不純物濃度を
後にイオン注入される第2導電型の不純物濃度より1桁
以上高く拡散される工程と、 前記第1導電型の不純物を拡散させた前記多結晶シリ
コン膜にアルゴンイオンをイオン注入することにより前
記多結晶シリコン膜の表面近傍をアモルファス化する工
程と、 前記多結晶シリコン膜をフォトリソグラフィ技術とエ
ッチング技術によりゲート電極および配線に加工する工
程と、 前記半導体基板全面に絶縁膜を堆積し、前記絶縁膜を
エッチングする事により前記ゲート電極側面に前記絶縁
膜のサイドウォールを形成する工程と、 前記半導体基板全面に高融点金属膜を形成する工程
と、 前記高融点金属膜を形成した半導体基板を加熱処理す
ることにより露出したシリコン基板表面およびゲート電
極上の高融点金属を高融点金属のシリサイドに変化させ
る工程と、 前記高融点金属のシリサイド以外の前記高融点金属の
化合物、及び、未反応の前記高融点金属を選択的に除去
する工程と、 からなることを特徴とするMIS型半導体装置の製造方
法。[MEANS FOR SOLVING THE PROBLEMS] A method for manufacturing an MIS type semiconductor device according to the present invention is a method for manufacturing a MIS type semiconductor device in which silicide of a high melting point metal is formed on an exposed silicon surface in a self-aligned manner. Forming a polycrystalline silicon film via a gate insulating film, and diffusing the impurity concentration of the first conductivity type into the polycrystalline silicon film by at least one order of magnitude higher than the impurity concentration of the second conductivity type which is later ion-implanted. A step of implanting argon ions into the polycrystalline silicon film in which the impurities of the first conductivity type are diffused to make the vicinity of the surface of the polycrystalline silicon film amorphous, Processing into a gate electrode and a wiring by photolithography and etching, and depositing an insulating film on the entire surface of the semiconductor substrate; Forming a side wall of the insulating film on the side surface of the gate electrode by etching; forming a refractory metal film on the entire surface of the semiconductor substrate; heating the semiconductor substrate on which the refractory metal film is formed; Changing the refractory metal on the silicon substrate surface and the gate electrode exposed by the process to a silicide of the refractory metal, a compound of the refractory metal other than the refractory metal silicide, and the unreacted refractory metal A method for selectively removing a metal, comprising: a step of selectively removing a metal.
また本発明のMIS型半導体装置の製造方法は、 前記高融点金属としてチタンを用いることを特徴とす
る。Further, in the method for manufacturing an MIS type semiconductor device according to the present invention, titanium is used as the high melting point metal.
[実施例] 第1図(a)〜(g)は本発明の実施例であり、本発
明の半導体装置の製造方法を工程を追って示した半導体
装置の断面図である。以下この図にしたがって本発明の
半導体装置の製造方法を実施例として説明する。Embodiments FIGS. 1A to 1G show an embodiment of the present invention, and are cross-sectional views of a semiconductor device illustrating a method of manufacturing a semiconductor device of the present invention step by step. Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described as an embodiment with reference to FIG.
第1図(a)に示すように半導体装置のシリコン基板
1上にゲート絶縁膜2を介して多結晶シリコン膜3を形
成する。本実施例ではこの第1の多結晶シリコン膜の膜
厚は4000Åとする。多結晶シリコン膜は不純物を含まな
い状態ではほとんど導電性はない。そこで本実施例とし
ては第1図(b)で示すように半導体基板をオキシ塩化
燐雰囲気中において900℃で加熱処理することにより多
結晶シリコン膜中に不純物として燐を熱拡散させること
によりN型の半導体として導電性をもたせた。熱拡散に
より注入される燐の濃度はPチャンネルのソース・ドレ
インの不純物拡散層形成のために注入されるホウ素の濃
度より1桁以上高く拡散しておく。このように高い濃度
に燐を含んでいる多結晶シリコンに対してチタンはシリ
サイドを作りにくい。次に第1図(c)で示すように燐
を拡散した多結晶シリコン膜1中に不純物イオンをイオ
ン注入する。本実施例では一例としてアルゴンイオンを
イオン注入することにする。注入されたアルゴンイオン
は多結晶シリコンの結晶生を破壊し非晶質化するため結
果として多結晶シリコンの表面近傍なアモルファス化し
たシリコン層4となる。アモルファス化したシリコンは
チタンと反応してチタンシリサイドになり易い。この多
結晶シリコン膜とアモルファスシリコン層をフォトリソ
技術及びエッチング技術によりゲート電極および配線以
外の部分を除去することにより第1図(d)の様に半導
体基板上にゲート電極および配線を形成する。次にこの
半導体基板上の全面に絶縁膜を形成する。一実施例とし
てこの絶縁膜は400℃程度の温度での化学的気層成長法
によるSiO2を主成分とする絶縁膜で膜厚は5000Åで形成
した。この絶縁膜を全面に渡ってフロン系ガスのプラズ
マ中での異方性エッチングによりゲート電極および配線
の側面のみ残しそのほかの部分は除去することにより、
第1図(e)に示すようにゲート電極および配線の側面
に絶縁膜からなるサイドウォール5を形成する。この後
第1図(f)に示すように半導体基板全面にチタン金属
膜6を形成する。本実施例としてこのチタン金属膜の膜
厚は500Åである。この半導体基板に加熱処理を行なう
ことによりシリコンとチタンを反応させシリコンと接触
している部分のチタンを選択的にチタンシリサイドに変
化させる。本発明の実施例としては、窒素ガス中でのハ
ロゲンランプによる光照射による短時間アニールにより
30秒間750℃に半導体基板表面を加熱する。この加熱に
よりアモルファス化した多結晶シリコン表面のシリコン
層および半導体基板のシリコンでシリコン表面がチタン
と接触している部分が反応してチタンシリサイドとな
る。またサイドウォールの絶縁膜上および素子分離の絶
縁膜上のチタンのほとんどは窒素と反応して窒化チタン
となる。また多少はチタンのまま残っているがチタンシ
リサイド以外のチタン化合物はアンモニア水と過酸化水
素水の混合液で溶かすことができる。本実施例ではこの
方法を用いてチタンシリサイドのみを残しサイドウォー
ル上や素子分離絶縁膜上のチタン金属およびチタン化合
物を除去することにより第1図(g)に示すように露出
したシリコン基板上、およびゲート電極と配線である多
結晶シリコン上に選択的にチタンシリサイド7を形成す
ることができた。As shown in FIG. 1A, a polycrystalline silicon film 3 is formed on a silicon substrate 1 of a semiconductor device with a gate insulating film 2 interposed therebetween. In this embodiment, the thickness of the first polycrystalline silicon film is 4000 °. The polycrystalline silicon film has almost no conductivity when no impurities are contained. Therefore, in this embodiment, as shown in FIG. 1 (b), the semiconductor substrate is heated at 900 ° C. in an atmosphere of phosphorus oxychloride to thermally diffuse phosphorus as an impurity in the polycrystalline silicon film, thereby obtaining an N-type semiconductor substrate. Was made conductive as a semiconductor. The concentration of phosphorus implanted by thermal diffusion is higher than the concentration of boron implanted for forming the impurity diffusion layer of the source / drain of the P channel by one digit or more. Titanium hardly forms silicide for polycrystalline silicon containing phosphorus at such a high concentration. Next, as shown in FIG. 1C, impurity ions are implanted into the polycrystalline silicon film 1 in which phosphorus is diffused. In this embodiment, argon ions are implanted as an example. The implanted argon ions destroy the crystal growth of the polycrystalline silicon and become amorphous, resulting in an amorphous silicon layer 4 near the surface of the polycrystalline silicon. Amorphous silicon tends to react with titanium to become titanium silicide. By removing portions of the polycrystalline silicon film and the amorphous silicon layer other than the gate electrode and the wiring by the photolithography technique and the etching technique, the gate electrode and the wiring are formed on the semiconductor substrate as shown in FIG. Next, an insulating film is formed on the entire surface of the semiconductor substrate. As an example, this insulating film was formed by a chemical vapor deposition method at a temperature of about 400 ° C. and was made of an insulating film containing SiO 2 as a main component and having a thickness of 5000 °. This insulating film is entirely anisotropically etched in a plasma of a chlorofluorocarbon gas, leaving only the side surfaces of the gate electrode and the wiring, and removing the other portions,
As shown in FIG. 1E, a side wall 5 made of an insulating film is formed on the side surfaces of the gate electrode and the wiring. Thereafter, as shown in FIG. 1 (f), a titanium metal film 6 is formed on the entire surface of the semiconductor substrate. In this embodiment, the thickness of the titanium metal film is 500 °. By subjecting the semiconductor substrate to heat treatment, silicon and titanium react with each other to selectively change titanium in a portion in contact with silicon to titanium silicide. As an embodiment of the present invention, a short-time annealing by light irradiation with a halogen lamp in nitrogen gas is performed.
Heat the semiconductor substrate surface to 750 ° C. for 30 seconds. The portion of the silicon layer on the surface of the polycrystalline silicon which has been made amorphous by this heating and the silicon of the semiconductor substrate where the silicon surface is in contact with titanium react to become titanium silicide. Most of titanium on the sidewall insulating film and the element isolation insulating film reacts with nitrogen to form titanium nitride. Although some titanium remains, titanium compounds other than titanium silicide can be dissolved in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. In this embodiment, the titanium metal and the titanium compound on the sidewalls and on the element isolation insulating film are removed by using this method, leaving only the titanium silicide, thereby removing the titanium metal and the titanium compound on the exposed silicon substrate as shown in FIG. In addition, titanium silicide 7 was selectively formed on the gate electrode and the polycrystalline silicon serving as the wiring.
以上実施例として述べてきた本発明の半導体装置の製
造方法によれば、不純物イオンのイオン注入によりアモ
ルファス化したシリコン層4はチタンと反応しやすくチ
タンシリサイドになりやすいのに対し多結晶シリコン膜
3は不純物として燐を多量に含んでいるためチタンとの
反応が抑制される。すなわちアモルファス化したシリコ
ン層4をすべてチタンシリサイド7にでき、かつ多結晶
シリコン膜3はそのまま残るためゲート電極上および配
線上にチタンシリサイドを制御性よく形成することがで
きる。さらにゲート電極および配線上に形成されたチタ
ンシリサイドは高濃度に燐を含んだ多結晶シリコンと接
触しているため従来技術の課題であったチタンシリサイ
ドと多結晶シリコンの接触抵抗は低減している。According to the method of manufacturing a semiconductor device of the present invention described above as an embodiment, the silicon layer 4 made amorphous by ion implantation of impurity ions easily reacts with titanium and easily becomes titanium silicide. Since phosphorus contains a large amount of phosphorus as an impurity, the reaction with titanium is suppressed. That is, since the amorphous silicon layer 4 can be entirely made of titanium silicide 7 and the polycrystalline silicon film 3 remains as it is, titanium silicide can be formed on the gate electrode and the wiring with good controllability. Furthermore, since the titanium silicide formed on the gate electrode and the wiring is in contact with polycrystalline silicon containing high concentration of phosphorus, the contact resistance between titanium silicide and polycrystalline silicon, which was a problem of the prior art, has been reduced. .
さらに以上の実施例で述べてきたように多結晶シリコ
ンは高濃度に燐を含んでいるためPチャンネルのソース
・ドレインを形成するための不純物であるホウ素の注入
拡散によっても燐の濃度はほとんど変化しないためPチ
ャンネル側のゲート電極の抵抗が高くなったり、トラン
ジスタのしきい値電圧が変化することはなくなった。Further, as described in the above embodiment, since the polycrystalline silicon contains phosphorus at a high concentration, the phosphorus concentration hardly changes even by the implantation and diffusion of boron which is an impurity for forming the source / drain of the P-channel. Therefore, the resistance of the gate electrode on the P-channel side does not increase and the threshold voltage of the transistor does not change.
また以上の実施例においては多結晶シリコンの表面近
傍の結晶性を破壊してアモルファス化する第2の不純物
としてアルゴンイオンを例に説明してきたがアルゴンイ
オンの他に燐や砒素、ホウ素などのイオンを用いても特
に以上の実施例で述べてきた作用と異なるものではな
く、本発明の半導体装置の製造方法と異なるものではな
い。また、本実施例においては高融点金属としてチタ
ン、第1の不純物として燐を用いているが、本発明はこ
れに限られない。In the above embodiments, argon ions are described as an example of the second impurity which breaks the crystallinity in the vicinity of the surface of polycrystalline silicon and becomes amorphous, but other ions such as phosphorus, arsenic, boron, etc. Is not different from the operation described in the above embodiment, and is not different from the method of manufacturing a semiconductor device of the present invention. In this embodiment, titanium is used as the high melting point metal and phosphorus is used as the first impurity, but the present invention is not limited to this.
[発明の効果] 以上述べたように、本発明によれば以下に列挙するよ
うな効果を有する。[Effects of the Invention] As described above, the present invention has the following effects.
(1)ゲート電極として高濃度に不純物を含んだ多結晶
シリコン上に高融点金属シリサイドを制御性よく形成す
ることができる。(1) Refractory metal silicide can be formed with good controllability on polycrystalline silicon containing a high concentration of impurities as a gate electrode.
(2)またゲート電極および配線である多結晶シリコン
と高融点金属シリサイドとの接触抵抗を低減させること
ができた。このことは半導体装置の高速動作において非
常に有利である。(2) The contact resistance between polycrystalline silicon, which is a gate electrode and a wiring, and high-melting-point metal silicide could be reduced. This is very advantageous in high-speed operation of the semiconductor device.
(3)従来技術におけるシリコン表面に自己整合的に高
融点金属シリサイドを形成する技術で問題であったPチ
ャンネル側のゲート電極の抵抗が高くなる問題やPチャ
ンネルトランジスタのしきい値電圧が変化する問題を解
決できた。(3) The conventional technique of forming a refractory metal silicide on the silicon surface in a self-aligned manner, which is a problem in that the resistance of the gate electrode on the P-channel side is increased, and the threshold voltage of the P-channel transistor is changed. Problem solved.
第1図(a)〜(g)は、本発明の半導体装置の製造方
法を工程を追って示した半導体装置の断面図。 1…シリコン半導体基板 2…ゲート絶縁膜 3…多結晶シリコン膜 4…アモルファス化したシリコン層 5…サイドウォール 6…高融点金属 7…高融点金属シリサイド1 (a) to 1 (g) are cross-sectional views of a semiconductor device illustrating a method of manufacturing a semiconductor device according to the present invention step by step. DESCRIPTION OF SYMBOLS 1 ... Silicon semiconductor substrate 2 ... Gate insulating film 3 ... Polycrystalline silicon film 4 ... Amorphized silicon layer 5 ... Side wall 6 ... Refractory metal 7 ... Refractory metal silicide
Claims (2)
サイドを自己整合的に形成するMIS型半導体装置の製造
方法において、 半導体基板上にゲート絶縁膜を介して多結晶シリコン膜
を形成する工程と、 前記多結晶シリコン膜中に第1導電型の不純物濃度を後
にイオン注入される第2導電型の不純物濃度より1桁以
上高く拡散される工程と、 前記第1導電型の不純物を拡散させた前記多結晶シリコ
ン膜にアルゴンイオンをイオン注入することにより前記
多結晶シリコン膜の表面近傍をアモルファス化する工程
と、 前記多結晶シリコン膜をフォトリソグラフィ技術とエッ
チング技術によりゲート電極および配線に加工する工程
と、 前記半導体基板全面に絶縁膜を堆積し、前記絶縁膜をエ
ッチングする事により前記ゲート電極側面に前記絶縁膜
のサイドウォールを形成する工程と、 前記半導体基板全面に高融点金属膜を形成する工程と、 前記高融点金属膜を形成した半導体基板を加熱処理する
ことにより露出したシリコン基板表面および前記ゲート
電極上の高融点金属を高融点金属のシリサイドに変化さ
せる工程と、 前記高融点金属のシリサイド以外の前記高融点金属の化
合物、及び、未反応の前記高融点金属を選択的に除去す
る工程と、 からなることを特徴とするMIS型半導体装置の製造方
法。1. A method of manufacturing a MIS type semiconductor device in which a refractory metal silicide is formed in a self-aligned manner on an exposed silicon surface, comprising: forming a polycrystalline silicon film on a semiconductor substrate via a gate insulating film; Diffusing the impurity concentration of the first conductivity type into the polycrystalline silicon film by one digit or more than the impurity concentration of the second conductivity type which is later ion-implanted; and diffusing the first conductivity type impurity. A step of amorphizing the vicinity of the surface of the polycrystalline silicon film by implanting argon ions into the polycrystalline silicon film; and a step of processing the polycrystalline silicon film into a gate electrode and a wiring by photolithography and etching. Depositing an insulating film on the entire surface of the semiconductor substrate, and etching the insulating film to form the insulating film on the side surface of the gate electrode. A step of forming a sidewall; a step of forming a refractory metal film over the entire surface of the semiconductor substrate; and a step of heat-treating the semiconductor substrate on which the refractory metal film is formed, on the silicon substrate surface and on the gate electrode which are exposed. Converting the refractory metal to a refractory metal silicide; and selectively removing the refractory metal compound other than the refractory metal silicide, and the unreacted refractory metal. A method for manufacturing a MIS type semiconductor device, comprising:
を特徴とする請求項1記載のMIS型半導体装置の製造方
法。2. The method according to claim 1, wherein titanium is used as said refractory metal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP479590A JP2917348B2 (en) | 1990-01-12 | 1990-01-12 | Method of manufacturing MIS type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP479590A JP2917348B2 (en) | 1990-01-12 | 1990-01-12 | Method of manufacturing MIS type semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03209834A JPH03209834A (en) | 1991-09-12 |
JP2917348B2 true JP2917348B2 (en) | 1999-07-12 |
Family
ID=11593711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP479590A Expired - Lifetime JP2917348B2 (en) | 1990-01-12 | 1990-01-12 | Method of manufacturing MIS type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2917348B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2720827B2 (en) * | 1994-07-05 | 1998-03-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5554566A (en) * | 1994-09-06 | 1996-09-10 | United Microelectronics Corporation | Method to eliminate polycide peeling |
US6100170A (en) * | 1997-07-07 | 2000-08-08 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device |
JP3389075B2 (en) | 1997-10-01 | 2003-03-24 | 株式会社東芝 | Method for manufacturing semiconductor device |
JPH11176833A (en) * | 1997-12-10 | 1999-07-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
-
1990
- 1990-01-12 JP JP479590A patent/JP2917348B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH03209834A (en) | 1991-09-12 |
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