JP2915040B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, in particular, to a bipolar device and a CM.
Bipolar CMOS (hereafter, referred to as “OS device”) is formed on the same substrate.
The present invention relates to a method of manufacturing a semiconductor device which enables a semiconductor integrated circuit (abbreviated as BiCMOS) to be manufactured by a simple manufacturing process.

(Prior art) In recent years, in order to increase the speed of analog / digital hybrid and CMOS, the use of BiCMOS hybrid technology has been increasing.
It has become the mainstream in the field of multi-technology.

Bi LSI has the characteristics of bipolar and CMOS, so it can achieve excellent performance such as high speed, high integration, high withstand voltage, high load driving capability, low power consumption, etc., but structurally incorporates bipolar element Therefore, an epitaxial layer and an isolation diffusion layer are required.

In addition, the steps are complicated in order to simultaneously form the bipolar element and the CMOS element without deteriorating the performance thereof, and the number of masks is increased, which is disadvantageous in terms of economy.

Here, a conventional BiCMOS type semiconductor integrated circuit will be described with reference to FIG.

In this figure, an N ⁺ buried layer 2 is formed on a P-type semiconductor substrate 1, and the N ⁺ buried layer 2 is usually made of an A ^{+ type} to reduce the collector series resistance of the NPN bipolar transistor 100.
It is diffused to 20-100Ω / □ using s and Sb. The method of manufacturing the portion of the NPN bipolar transistor 100 is disclosed in
No. 259.

The N ⁺ buried layer 2 is also diffused into the PMOS 300 formation region at the same time so that the CMOS does not cause a parasitic bipolar operation.

4 is a P ⁺ buried layer, which is an NPN bipolar transistor 100
Are formed in advance in the element isolation region by an ion implantation method or the like, and are used to shorten the separation / diffusion time by utilizing upward diffusion from the semiconductor substrate 1 during the next epitaxial step or separation / diffusion, Usually, it is set to 50 to 300Ω / □ using B (boron).

The NMOS 200 is also formed in the NMOS 200 formation region at the same time so that the parasitic bipolar operation does not occur.

The concentration and thickness of the N ⁻ epitaxial layer 5 are determined so that the device characteristics of the NPN bipolar transistor 100 and the gate threshold voltage of the PMOS can be controlled.

The P ^- diffusion region 6 is diffused from the surface of the epitaxial layer 5 in order to control the element isolation of the NPN bipolar transistor 100 and the threshold voltage of the NMOS 200.

7 is a P diffusion layer, the active base of the NPN bipolar transistor 100, 8 is a P ⁺ diffusion layer,
The drain and the inactive base layer of the NPN bipolar transistor 100 are formed. The inactive base layer is necessary to make ohmic contact with the base layer.

9 is an N ⁺ diffusion layer, which is the source / drain of the NMOS 200 and the NPN
The contact extraction of the emitter and collector layers of the bipolar transistor 100 is formed.

7, 8, and 9 are selectively diffused using oxide film 11 as a mask to form P, P ⁺ , and N ⁺ regions, respectively. Reference numeral 10 denotes a gate of a PMOS or NMOS.

Thus, a BiCMOS type semiconductor integrated circuit is configured.

However, in the conventional method, when the N ⁺ buried layer 2 and the P ⁺ buried layer 4 are formed, the N ⁺ buried layer 2 and the P ⁺ buried layer 4 are formed through separate photolithography steps. In addition to the space required for obtaining a withstand voltage, a margin for alignment of about 1 to 2 μm is required between the buried layers 2 and 4, which hinders miniaturization of the device.

Further, as a more improved process, first, the P ⁺ buried layer 4
Is covered with a Si ₃ N ₄ film, and then this S
Using the i ₃ N ₄ film as a mask, Sb for the N ⁺ buried layer is implanted by ion implantation.

Next, while performing drive-in in an oxidizing atmosphere, Sb
There is a method of forming a thick oxide film in the region where the is implanted, stripping off the Si ₃ N ₄ film, implanting B ⁺ for a P ⁺ buried layer, and driving in. According to this method, the N ⁺ buried layer and the P ⁺ buried layer are formed in a self-aligned manner, so that no alignment margin is required.

(Problems to be Solved by the Invention) However, in the former method, when applied to a device having a high isolation withstand voltage, the distance between the N ⁺ -type buried layer and the P ⁺ -type buried layer depends on the isolation withstand voltage. In addition to the spacing required to obtain the alignment, a margin for alignment of about 1 to 2 μm is required, and there is a problem that the reduction in the size of the element is greatly hindered.

In the latter method, for the N ⁺ type buried layer and the P ⁺ -type buried layer can be formed by self-alignment, combined but allowance is not required, the N ⁺ type buried layer and the P ⁺ -type buried layer Since they are close to each other, there is a problem that they can be applied only to devices having a low isolation breakdown voltage.

The present invention has been made in view of the above points, and eliminates the need for an alignment margin between an N ⁺ type buried layer and a P ⁺ type buried layer.
An object of the present invention is to provide a method of manufacturing a semiconductor device in which both buried layers can be separated to increase the isolation withstand voltage.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device having a buried layer, which is an isolation diffusion layer, in a semiconductor substrate. Forming an oxidation-resistant film on the first oxide film and the first oxide film; and selecting the oxidation-resistant film on regions where a first conductivity type diffusion layer and a second conductivity type diffusion layer are to be formed. Leaving an insulating film on the main surface of the semiconductor substrate so as to cover the oxidation-resistant film left selectively; and forming an insulating film on the first conductive type diffusion layer forming region. Removing the oxidation-resistant film and the insulating film; implanting a first-conductivity-type impurity into a region where the first-conductivity-type diffusion layer is to be formed in the semiconductor substrate; and removing the remaining insulating film And a thermal oxidation process to expand the first conductivity type into the semiconductor substrate. Forming a diffused layer, forming a second oxide film on the main surface of the semiconductor substrate, and removing the oxidation-resistant film on a region where the second conductivity type diffusion layer is to be formed; Implanting a second conductivity type impurity into the second conductivity type diffusion layer forming region in the semiconductor substrate, and forming a second conductivity type diffusion layer in the semiconductor substrate by heat treatment; Wherein the diffusion layer of the second conductivity type and the diffusion layer of the first conductivity type are buried layers.

(Operation) According to the present invention, as described above, in the method of manufacturing a semiconductor device, an oxide film is formed on a semiconductor substrate, and an N ⁺ -type buried layer and a P ⁺ -type buried layer are formed on the oxide film. A nitride film to be a region is selectively formed. Then, to remove the nitride film serving as the N ⁺ -type buried layer forming region, by the nitride film in a region to remove selectively N-type impurity ions are implanted to oxidize the entire surface, N ⁺ -type buried layer To form Then by removing the nitride film serving as the P ⁺ -type buried layer forming region, by selectively ion-implanting P-type impurity in the region to remove the nitride film to form a P ⁺ -type buried layer.

Therefore, there is no need for a margin for alignment between the buried layers, and the device can be reduced in size. Further, since the distance between both buried layers can be increased in accordance with the isolation withstand voltage of the element, elements requiring high isolation withstand voltage and low isolation withstand voltage can be formed simultaneously.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

An embodiment of the present invention will be described with reference to the cross-sectional views of FIGS.

(A) First, an oxide film 102 having a thickness of 100 ° is formed on a P-type semiconductor substrate 101 by performing oxidation at 950 ° C. for about 20 minutes. Next, a 3000-nm-thick nitride film 103 is formed on the entire surface by using a known LPCVD method.

(B) The nitride film other than the nitride film 104 (a part of the nitride film 103) to be the N ⁺ type buried layer and the P ⁺ type buried layer forming region is etched by using a known photolithography etching technique.

(C) An oxide film 105 having a thickness of 1 μm is formed on the entire surface by using a known CVD method.

(D) Using a known photolitho etching technique, the portion of the oxide film 105 to be the N ⁺ type buried layer formation region 106 is changed to the nitride film 10
Etch until the 4 is exposed.

(E) Using the oxide film 105 as a mask, the nitride film 104 in the N ⁺ type buried layer formation region 106 is etched using a known etching technique. Next, using the oxide film 105 as a mask, a known ion implantation technique is used to deposit Sb at a dose of 2 × 10 ¹⁵ cm ⁻² ,
It is implanted into the P-type semiconductor substrate 101 at an acceleration voltage of 60 KeV. The nitride film below the oxide film 105 remaining after the etching of the nitride film 104 is referred to as 107.

(F) The oxide film 105 and the oxide film 102 are etched using a known etching technique. Even if this etching is performed, the oxide film 102 under the nitride film 107 remains using the nitride film 107 as a mask.

(G) By performing drive-in at 1200 ° C. for about 120 minutes, Sb in the P-type semiconductor substrate 101 is activated, and the N ⁺ -type buried layer 108 is formed. At this time, the P-type semiconductor substrate 1
Oxide film 109 having a thickness of 3000 ° is formed on the surface of 01.

(H) After etching the nitride film 107 with hot phosphoric acid, the P-type semiconductor substrate 101 is doped with B (boron) at a dose of 1 × 10 ¹⁴ cm ⁻² and an acceleration voltage of 60 KeV using a known ion implantation technique.
Inject into.

(I) By annealing at 1000 ° C. for about 60 minutes,
B (boron) in the P-type semiconductor substrate 101 is activated, and P ⁺
A mold buried layer 110 is formed.

Subsequent steps can be formed in exactly the same manner as the conventional step if the oxide film 109 is removed, so that the description is omitted.

With this configuration, as shown in FIG. 1 (i), the region 111 becomes an element forming region requiring a high isolation withstand voltage, and the N ⁺ -type buried layer 108 and the P ⁺ -type buried layer 110
The region 112 is formed at a large distance, and the region 112 becomes an element formation region requiring a low isolation withstand voltage, and N ⁺
The buried layer 108 and the P ⁺ -type buried layer 110 can be simultaneously formed without any distance.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the gist of the present invention.
They are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, the N ⁺ -type buried layer and the P ⁺ -type buried layer forming region are formed simultaneously with the nitride film pattern. The alignment margin between the embedded layers becomes unnecessary, and the element can be reduced in size. Further, since the distance between both buried layers can be increased in accordance with the isolation withstand voltage of the element, elements requiring high isolation withstand voltage and low isolation withstand voltage can be formed simultaneously.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional BiCMOS type semiconductor integrated circuit. 101: P-type semiconductor substrate, 102, 105, 109 ... oxide film, 103, 104,
107 ... nitride film, 106 ... N ⁺ type buried layer formation region, 108 ... N ⁺ type buried layer, 110 ... P ⁺ type buried layer.

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a buried layer serving as an isolation diffusion layer in a semiconductor substrate, comprising: (a) a first oxide film on a main surface of the semiconductor substrate;
Forming an oxidation-resistant film on the oxide film of (b); and (b) selectively leaving the oxidation-resistant film on regions where diffusion layers of the first and second conductivity types are to be formed. (C) a step of forming an insulating film on the main surface of the semiconductor substrate so as to cover the selectively left oxidation resistant film; and (d) on a region where the first conductivity type diffusion layer is to be formed. Removing the oxidation-resistant film and the insulating film; (e) implanting a first-conductivity-type impurity into a region where the first-conductivity-type diffusion layer is to be formed in the semiconductor substrate; and (f). Removing the remaining insulating film; and (g) forming a first conductivity type diffusion layer in the semiconductor substrate by thermal oxidation, and forming a second oxide film on a main surface of the semiconductor substrate. And (h) removing the oxidation-resistant film on the region where the diffusion layer of the second conductivity type is to be formed. (I) implanting a second conductivity type impurity into the second conductivity type diffusion layer formation region in the semiconductor substrate; and (j) heat treating the second conductivity type impurity into the semiconductor substrate. Forming a diffusion layer of a second conductivity type, wherein the diffusion layer of the second conductivity type and the diffusion layer of the first conductivity type are buried layers.