JP2909910B2 - Image recording device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image recording apparatus that records a still image on an external recording medium.

2. Description of the Related Art A digital still camera is an example of an image recording apparatus. Such a still camera generally uses a memory element having a relatively low writing speed as an external recording medium. In order to increase the continuous shooting speed, a plurality of frame memories are provided in the camera body to provide one frame memory. There has been proposed a configuration in which a captured image is written in another frame memory while a stored image in the frame memory is written to an external recording medium (for example, Japanese Patent Application Publication No.
64485).

[Problems to be Solved by the Invention] However, in the above conventional example, in order to increase the continuous shooting speed, the number of frame memories in the camera body must be increased, which leads to an increase in circuit size and cost information. Furthermore, power consumption increases with an increase in the amount of memory.

Therefore, an object of the present invention is to provide an image recording apparatus which has solved such a disadvantage.

[Means for Solving the Problems] An image recording apparatus according to the present invention records an image input means, an image compression means for compressing an image input from the image input means, and an image processed by the image compression means. In accordance with the continuous input speed when a plurality of images are continuously input by the image input unit, the compression ratio of the image compression unit is increased when the continuous input speed is high. When the continuous input speed is low, the image compression means comprises a compression rate control means for lowering the compression rate of the image compression means.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
In FIG. 1, reference numeral 10 denotes a camera main body, and 12 denotes an external memory pack detachable from the camera main body 10. External memory
Pack 12 can be, for example, a battery-backed SRA
M, large capacity D with slow writing speed to reduce power consumption
It consists of solid-state memory elements such as EEPROM, which does not require RAM or battery backup but has a slow writing speed. The writing speed of each memory pack is based on battery-backed SRAM
200nsec / byte, low power consumption DRAM with battery backup
And 2 μsec / byte for EEPROM and 31 μsec / byte for EEPROM. Also,
Assuming that one screen consists of 512 × 480 pixels, the time required to write all the signals of one screen to the external memory pack 12 is 49 msec for battery backup SRAM, 490 msec for battery backup low power consumption DRAM, 7.61 sec with EEPROM
It is.

In the camera body 10, 14 is a taking lens, 15 is an aperture,
Reference numeral 16 denotes a shutter, which constitutes a photographing optical system.
Reference numeral 17 denotes a solid-state imaging device that converts an optical image obtained by a photographing optical system into an electric signal, 18 denotes an amplifier, 20 denotes an A / D converter that digitizes an analog signal, 22 denotes a timing control circuit, and 24 denotes a reference of the timing control circuit 22. An oscillation circuit that generates a signal. 26 is a frame memory for temporarily storing a captured image signal, 28 is a memory control circuit for controlling the frame memory 26, 30 is a write address generation circuit for generating a write address signal for the frame memory 26, and 32 is for writing and reading. This is a buffer for switching.

34 is a system control circuit for controlling the whole of the illustrated device, 36
Is a shutter switch interlocked with the operation of the shutter button, 38 and 40 are switches for selecting a continuous shooting mode, 42 is a switch interface circuit, 43 is a write address signal of the write address generation circuit 30 and a signal from the external memory pack 12. Switch for switching the read address signal. 44 is a power supply circuit of the camera body 10.

In the external memory pack 12, 46 is an address bus and read signal switch, and 48 is a DC-DC converter for forming a voltage required in the external memory pack 12 from a power supply voltage supplied from the camera body 10. , 50 is a BCD-binary decoder for converting BCD data into binary data, 5
2 is a data buffer for switching the direction of the data bus between shooting and playback, and 54 is a compression ratio a1
(1/2 in this embodiment), 55 is a compressor with a compression ratio a2 (1/4 in this embodiment), 56 is a compression ratio a3 (1/3 in this embodiment).
The compressor of 6), 57 is a non-compressor that does not compress (that is, a compressor with a compression ratio of zero). Reference numeral 58 denotes a switch for switching addresses, data, and write signals from the compressors 54, 55, and 56 and the non-compressor 57, and reference numeral 60 denotes a storage element such as an SRAM, a DRAM, or an EEPROM.

Next, the operation of FIG. 1 will be described. When the shutter switch 36 is closed by pressing the shutter button,
The system control circuit 34 controls the aperture 15 so that the optimum amount of light is incident on the image sensor 17, and opens the shutter 16 for a shutter time set by a shutter speed setting device (not shown). The image sensor 17 converts an optical image obtained by the photographing optical system into an electric signal. This electric signal is sequentially read out in synchronization with the timing signal from the timing control circuit 22,
The signal is amplified by the amplifier 18 and converted into an 8-bit digital signal by the A / D converter 20. Timing control circuit
The 22 appropriately divides the frequency of the clock from the oscillator 24 and generates timing signals for the respective operations of the image sensor 17, the A / D converter 20, and the memory control circuit 28.

At the same time as closing the shutter 16, the system control circuit 40 sets the signal ▼ to low (L), activates the buffer 32, and outputs the output of the A / D converter 20 to the frame memory 26.
Lead to. By the signal ▲ ▼, the switch 43 is connected to the output side of the write address generation circuit 30, and the frame memory 26 synchronizes with the write signal of the memory control circuit 28,
The data from the buffer 32 is written to the address according to the write address signal of the write address generation circuit 30. When a series of readings from the image sensor 17 is completed, the memory control circuit 28 sends a capture end signal to the system control circuit 34 to notify the frame memory 26 that the image has been captured.
When the capture of one screen into the frame memory 26 is completed, the write address generation circuit 30 stops its operation and suppresses power consumption.

Next, the system control circuit 34 reads the state of the continuous shooting mode selection switches 38 and 40 via the switch interface circuit 42 and generates control signals SEL1 and SEL2. According to the control signals SEL1 and SEL2, the switching devices 46 and
Control 58. The continuous shooting speed can be selected from three types as shown in Table 1.

The frame capture mode will be described. At this time, switch 38,4
0 is both on. In frame capture mode, the shutter
Each time the button is pressed, the shutter 16 opens and closes, and the image sensor
The image signal by 17 is temporarily stored in the frame memory 26 according to the above procedure. After completion of loading into the frame memory 26,
The system control circuit 34 sets the signal ▼ to high, activates the switches 46 and 58, and sets the control signal SEL1 (=
1), SEL (= 1) is output, and the non-compressor 57 is selected as shown in Table 1. That is, the address signal and the read signal output from the non-compressor 57 are sent from the switch 46 to the camera body 10 side, whereby the address
The bus and data bus are connected to the non-compressor 57
The address, data and write signals on the data output side of 57 are connected to the storage element 60 via the switch 58. As a result, the stored image information in the frame memory 26 is transferred to the storage element 60 without compression. For example, a large-capacity DRAM is used for the storage element 60.
Is used, a memory pack having a capacity of about 2 Mbytes has been prototyped with the current technology. In the case of no compression, eight images of 520 × 480 pixels can be stored in this memory pack.

The case of continuous shooting will be described. When both switches 38 and 40 are off, 4 frames / sec. When switch 38 is on and switch 40 is off, 8 frames / sec. When switch 38 is off and switch 40 is off.
When is ON, it is 12 frames / second. 250 msec allowed to store one image in external memory pack
And the writing speed of the external memory pack 12 made of DRAM is 49.
About twice the speed of 0 msec is required. Therefore, in this case, the amount of recorded information is reduced by half by
The writing time to the external memory pack 12 for each pixel is reduced. Similarly, in the case of 8 frames / sec, 1 /
The write information amount is compressed to 4, and in the case of 12 frames / second, it is compressed to 1/6 by the compressor 56.

At the time of continuous shooting, one of the compressors 54, 55, 56 may be activated, so that power to the unused compressors 54, 55, 56 and the non-compressor 57 is cut off from the viewpoint of saving power consumption. It is preferable to keep it.

Such compressors 54, 55, 56 are, for example, as follows. That is, the compressor 54 performs 1/2 compression with a 4-bit DPCM quantization table, and the compressor 55 performs sub-sampling and DPC.
The M quantization table performs 1/4 compression with 4 bits.
The representative value for each pixel is compressed by 1/6 using a 4-bit DPCM quantization table.

When reading image information recorded in the external memory pack 12, the external memory pack 12 is detached from the camera body 10 and connected to a dedicated reading device. When connected to the reader, the capture signal goes high, the BCD-binary decoder 50 and switch 58 are turned off, and the data bus, address bus and read signals of the storage element 60 are connected to the external connector of the external memory pack 12. Unit, and according to the addressing and read timing of the dedicated reading device,
The data in the storage element 60 is read. In the read image information, information such as a compression method, a shutter speed, and a continuous shooting speed is always stored in a predetermined position at the head of the image information.

In this embodiment, the configuration of the external recording device is also a significant feature.

In the above embodiment, different compression processes are performed by selectively using a non-compressor and a plurality of compressors.However, a high-speed digital signal processing circuit capable of externally controlling the compression ratio is used, and an external control signal is used. The image compression ratio (including no compression) may be switched. As the storage element 60 of the external memory pack, other recording media such as a magnetic bubble memory, a magnetic disk, and an optical disk can be used in addition to the above. Furthermore, although the case of DPCM has been described as a compression method, other methods such as vector quantization, block coding, and discrete cosine transform may be used.

Although an electronic still camera has been described as an example, the present invention is not limited to this, but can be applied to other image recording apparatuses.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, a continuous image can be recorded on a relatively low-speed external image recording medium without increasing the memory capacity. Became.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of one embodiment of the present invention. 10: Camera body, 12: External memory pack, 14: Shooting lens, 15: Aperture, 16: Shutter, 17: Solid-state image sensor, 18: Amplifier, 22: Timing control circuit, 26: Frame memory, 2
8: Memory control circuit, 30: Write address generation circuit, 32: Buffer, 34: System control circuit, 36: Shutter switch, 38, 40: Continuous shooting mode selection switch, 46: Address bus / read signal switch, 49 : BCD-binary decoder,
54, 55, 56: compressor, 57: no compressor, 58: storage element write address switch, 60: storage element

Claims (1)

(57) [Claims] An image input means, an image compression means for compressing an image input from the image input means, a recording means for recording an image processed by the image compression means, According to the continuous input speed when a plurality of images are input, if the continuous input speed is high, the compression ratio of the image compression unit is increased, and if the continuous input speed is low, the image compression unit is An image recording apparatus, comprising: compression ratio control means for lowering the compression ratio.