JP2907630B2 - Frame memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory control device for transferring image data written to a frame memory by a bit map method to a raster scan type CRT display device for display.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional device of this type divides (a) a frame memory 3 into a plurality of memory banks A, B and C, each of which is logically independent, and (b) ) The display screen 51 of the CRT display device is virtually divided into display sections # 0, # 1, and # 2 according to the number of horizontal scanning lines, and (c) bank A stores image data displayed in the display section # 0. The image data displayed in the display section # 1 is written in the bank B, and the image data displayed in the display section # 2 is written in the bank C.

The frame memory 3 is constructed using a dual-port DRAM (memory that can be written at any time) having two types of ports, parallel and serial. In the frame memory 3, image data written one word at a time in parallel by the bit map method from the parallel port side,
The data is read out serially from the serial port side by one line every one horizontal scanning line period and transferred to the display device side (for example, Japanese Patent Laid-Open No. 63-240).
620).

[0004]

However, according to such a configuration, there is a problem that the contents of processing performed by the device that writes data to the frame memory are greatly restricted.

The above problem occurs for the following reasons. That is, when the processing device that writes the image data in the frame memory 3 handles a large amount of image data that covers the entire display screen 51, or when the enlargement, reduction, rotation, movement, synthesis, and the like are arbitrarily performed, Short time (horizontal scan return
Have to process a large amount of data within the section of the line)
Therefore, writing of image data to the frame memory needs to proceed simultaneously to all memory banks, and all the memory banks are used for writing.
Write and read in parallel.
Can no longer do so.

Therefore, conventionally, as shown in FIG. 4, parallel writing and serial reading to the frame memory are separated in synchronization with a horizontal synchronization signal (HSYNC #), and a horizontal scanning return section (BLAN) of the display apparatus is separated.
K #), one line of image data is serially transferred to the display device side, and while the serially transferred one line of image data is being displayed on the display device, the data is transferred to an arbitrary bank of the frame memory. Writing was performed.

However, in this case, on the writing side, the time during which continuous access to the frame memory is possible is restricted by the horizontal synchronization period, and on the reading side, the timing is restricted only to the horizontal scanning retrace interval. Operation under very severe timing conditions is forced.

In other words, the writing-side device can only perform processing such that one access is always completed within one horizontal scanning period, so that the contents of the processing are restricted. It becomes difficult to perform such processing as to handle the image data smoothly. In addition, since the reading side is given only a limited timing of only the horizontal scanning retrace interval, the access on the writing side may be prolonged even a little, so that the transfer of image data to the display device side is performed. Cannot be performed, and display noise appears on the display screen.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the contents of processing performed by a device that writes data to a frame memory without hindering transfer of image data from the frame memory to the display device. It is an object of the present invention to provide a frame memory control device capable of providing a margin.

[0010]

According to the present invention, a frame memory is divided into a plurality of memory banks.
Interleave control means for logically dividing one memory bank into a plurality of blocks and switching between the blocks; and the interleave control means switching blocks in the memory bank for each horizontal line as an arbitrary row of image data. La from the frame memory and transfer means for transferring the image data to the display side, to the frame memory data transfer units of lines by the transfer means by the writing side
Horizontal scanning retrace period before in synchronization with the write-in units
And timing control means for performing the control during a period extending over both of the display sections of the transferred lines .

[0011]

According to the present invention, a transfer time for transferring image data from the frame memory to the display side by the above configuration is provided.
In this case , the line image data can be surely transferred from the frame memory to the display side, and the transfer from the frame memory to the display side can be performed by the device that writes the frame memory.
The next one horizontal line data is written in synchronization with
By doing so, the write time will also have a margin.
Because, without disturbing the display on the display device is a read side of the frame memory, making it possible to perform advanced image processing apparatus to be the writing side.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts. FIG. 1 shows a schematic configuration of a frame memory control device according to an embodiment of the present invention, wherein 1 is an image memory for storing unprocessed input images, 2
Is a display control device for processing image data, 3
Is a frame memory for storing image data in a bitmap system, and 4 is 1 from the serial port side of the frame memory 3.
A video signal conversion / transfer section that converts image data serially transferred line by line into a video signal and outputs the video signal, and a bit map type CRT display 5 that displays the video signal transmitted from the video signal conversion / transfer section 4 Equipment, 6
Is a frame memory control device for controlling the operation of the frame memory 3 and its peripherals.

The frame memory 3 is configured using a dual-port DRAM (memory that can be written at any time) having two types of ports, parallel and serial.

The frame memory controller 6 logically divides the frame memory 3 into a plurality of memory banks so that the transfer of the image data from the frame memory 3 to the display side is performed by switching the memory banks for each horizontal line. Interleave control means, and timing control means for transferring the line image data from the frame memory 3 during a period spanning both the horizontal scanning retrace interval and the subsequent line display interval.

FIG. 2 shows the correspondence between the frame memory and the display screen. The correspondence shown in the figure is logically configured under the control of the frame memory control device 6.

In FIG. 1, (a) frame memory 3
Is logically divided into three memory banks A, B, and C, and each memory bank A, B, and C is logically divided into two blocks L and H, respectively.

(B) The display screen 51 of the CRT display device 5 is virtually divided into three display sections # 0, # 1, and # 2 according to the number of horizontal scanning lines.

(C) Image data displayed in the display section # 0 of the display screen 51 is alternately sorted and stored in the banks AL and BH of the frame memory 3 line by line. Similarly, display image data of section # 1 is in banks CL and AH, and display image data of section # 2 is in banks BL and CH.
Are stored alternately for each line.

FIG. 3 shows the correspondence described above for each horizontal scanning line of the display device. As shown in the figure, the transfer of image data from the frame memory 3 to the display side is performed by switching memory banks for each horizontal line by interleave control.

The operation of the frame memory control device configured as described above will be described below.

In the above-described apparatus, as shown in FIG. 6 , first, parallel writing and serial reading to the frame memory 3 are performed in synchronization with a horizontal synchronization signal (HSYNC #). Under this synchronization, the transfer of the line image data (n, n + 1,...) From the frame memory 3 to the display side is performed by performing interleave control for switching the memory bank of the transfer source for each horizontal line. Device 5
In the horizontal scanning retrace interval and the subsequent line display interval. The transferred line image data is displayed on the display with a delay of one horizontal scanning period (n-1, n, n + 1,...).
・ ・).

As a result, timing restrictions when transferring image data from the frame memory 3 to the display side are greatly relaxed, and line image data can be reliably transferred from the frame memory 3 to the display side. Will be able to At the same time, on the display control device 2 side that writes data to the frame memory 3, the time restriction when accessing the frame memory 3 is greatly relaxed. Image processing such as accessing the frame memory 3 by shifting is also possible. This allows the display control device 2 on the writing side to perform advanced processing without hindering the display on the display device 5 on the reading side of the frame memory 3.

[0024]

As is apparent from the above description, the present invention provides an interleave control means for logically dividing a frame memory into a plurality of memory banks, one memory bank into a plurality of blocks, and switching between the blocks. Transfer means for transferring image data from the frame memory to the display side while switching blocks in the memory bank for each horizontal line, which is an arbitrary row of image data, by the interleave control means; Transfer by writing to the frame memory line by line
Horizontal scanning retrace interval and previous transfer in synchronization with writing
And timing control means for performing the control during a period extending over both display sections of the display line, so that the transfer time when transferring the image data from the frame memory to the display side is provided with a margin. Transfer of line image data from the frame memory to the display side can be reliably performed, and the apparatus that performs writing to the frame memory also has a margin for writing time.
To become bets, without disturbing the display on the display device is a read side of the frame memory, it is possible to perform advanced image processing apparatus to be the writing side, which has the effect that It is.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a system using a frame memory control device according to an embodiment of the present invention;

FIG. 2 is a diagram showing a correspondence relationship between a frame memory and a display screen.

FIG. 3 is a diagram showing the correspondence between a frame memory and a display screen for each line.

FIG. 4 is a diagram showing write / read timing conditions of a conventional frame memory.

FIG. 5 is a diagram showing a correspondence relationship between a frame memory and a display screen according to the related art.

FIG. 6 is a diagram showing write / read timing conditions of a frame memory according to the present invention;

[Explanation of symbols]

 Reference Signs List 1 input image memory 2 display control device (writing side) 3 frame memory 4 video signal conversion / transfer section 5 CRT display device 6 frame memory control device

Claims (1)

(57) [Claims] 1. An interleave control means for logically dividing a frame memory into a plurality of memory banks and one memory bank into a plurality of blocks to switch between the blocks, and the interleave control means controls an arbitrary row of image data. Transfer means for transferring image data from the frame memory to the display side while switching blocks in the memory bank for each horizontal line, and transferring data in line units by the transfer means to the frame memory by the writing side
A frame memory control device comprising: a timing control unit for performing the control in a period extending over both the horizontal scanning retrace period and the display period of the previously transferred line in synchronization with the line-by-line writing to the line .