JP2906756B2 - Substrate for mounting electronic components - Google Patents
Substrate for mounting electronic componentsInfo
- Publication number
- JP2906756B2 JP2906756B2 JP22113091A JP22113091A JP2906756B2 JP 2906756 B2 JP2906756 B2 JP 2906756B2 JP 22113091 A JP22113091 A JP 22113091A JP 22113091 A JP22113091 A JP 22113091A JP 2906756 B2 JP2906756 B2 JP 2906756B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- sealing lid
- solder resist
- electronic component
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は，封止蓋の取付位置精度
に優れた，電子部品搭載用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting electronic parts, which is excellent in mounting position accuracy of a sealing lid.
【０００２】[0002]
【従来技術】図８に示すごとく，従来電子部品搭載用基
板においては，その基板９は，配線回路９０と，該配線
回路９０を上下方向に電気的に接続するスルーホール９
１と，略中央部に設けた電子部品８の搭載用の凹部９２
と，その周縁に設けた枠状ダム部９３とを有する。そし
て，上記凹部９２内には，半導体チップ等の電子部品８
を搭載すると共に，ワイヤボンディング８１により配線
回路９０と電気的に接続し，その上方に封止蓋７が接合
されている。これにより，上記凹部９２内に，外部より
水分が侵入することが防止されている。2. Description of the Related Art As shown in FIG. 8, in a conventional electronic component mounting substrate, a substrate 9 includes a wiring circuit 90 and a through hole 9 for electrically connecting the wiring circuit 90 in a vertical direction.
1 and a recess 92 for mounting the electronic component 8 provided substantially at the center.
And a frame-shaped dam portion 93 provided on the periphery thereof. In the recess 92, the electronic component 8 such as a semiconductor chip is placed.
Is mounted, and is electrically connected to the wiring circuit 90 by wire bonding 81, and the sealing lid 7 is joined above the wiring circuit 90. This prevents moisture from entering the recess 92 from outside.
【０００３】また，図９に示すごとく，他の態様の電子
部品搭載用基板がある。このものは，凹部９２の周縁に
切込み凹部９０１を設けている。そして，該切込み凹部
９０１の上に，接着剤６を介して上記封止蓋７が接合さ
れている。As shown in FIG. 9, there is another type of electronic component mounting substrate. In this embodiment, a notch 901 is provided on the periphery of the recess 92. The sealing lid 7 is joined to the cut recess 901 via an adhesive 6.
【０００４】[0004]
【解決しようとする課題】しかしながら，上記従来技術
には，次の問題点がある。即ち，前者（図８）において
は，枠状ダム部９３と封止蓋７との間には，両者の寸法
変化を考慮して若干の隙間９３１を設けておく必要があ
る。そのため，上記封止蓋７の位置ずれを生じ，封止蓋
の取付位置精度に優れない。また，封止蓋７の取付け不
良を生ずることがある。一方，後者においては，上記切
込み凹部９０１を形成するに当たって，その深さや大き
さにバラツキを生ずることがある。そのため，上記と同
様に，封止蓋７の位置ずれを生じ，封止蓋の取付位置精
度に優れない。また，封止蓋７の取付け不良を生ずるこ
とがある。However, the above prior art has the following problems. That is, in the former case (FIG. 8), it is necessary to provide a slight gap 931 between the frame-shaped dam portion 93 and the sealing lid 7 in consideration of the dimensional change between them. Therefore, the sealing lid 7 is displaced, and the mounting position accuracy of the sealing lid is not excellent. Further, there is a case where the mounting of the sealing lid 7 is defective. On the other hand, in the latter case, the depth and size of the cut recess 901 may vary in forming the cut recess 901. Therefore, similarly to the above, the sealing lid 7 is displaced, and the mounting position accuracy of the sealing lid is not excellent. Further, there is a case where the mounting of the sealing lid 7 is defective.
【０００５】また，上記切込み凹部９０１を形成するに
当たり，基板９の内部には配線回路９０が形成してある
ため，該切込み凹部９０１はその切り込み深さや大きさ
に制限を受けることになる。そのため，該切込み凹部９
０１を設ける作業が困難となり，作業能率が悪くなる。
本発明は，かかる従来の問題点に鑑みてなされたもの
で，封止蓋の取付位置精度に優れ，作業能率が良い，電
子部品搭載用の基板を提供しようとするものである。In forming the notch 901, since the wiring circuit 90 is formed inside the substrate 9, the notch 901 is limited in its cut depth and size. Therefore, the cut recess 9
01 becomes difficult, and the work efficiency deteriorates.
SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and has as its object to provide a substrate for mounting an electronic component, which has excellent mounting position accuracy of a sealing lid and good work efficiency.
【０００６】[0006]
【課題の解決手段】本発明は，基板における凹部内に電
子部品を搭載し，その上方に封止蓋を接合してなる電子
部品搭載用基板において，上記基板には凹部の開口部周
縁を除いてソルダーレジスト被膜が施されており，また
上記開口部周縁の表面には封止蓋の周縁部を接合してな
り，かつ該封止蓋の内側面はソルダーレジスト被膜の表
面よりも内部に位置していることを特徴とする電子部品
搭載用基板にある。本発明において最も注目すべきこと
は，上記基板には凹部の開口部周縁を除いてソルダーレ
ジスト被膜が施され，また上記開口部周縁の表面に封止
蓋の周縁を接合してなり，かつ該封止蓋の内側面はソル
ダーレジスト被膜の表面よりも内部に位置していること
である。According to the present invention, there is provided an electronic component mounting board in which an electronic component is mounted in a concave portion of a substrate and a sealing lid is bonded above the electronic component. A solder resist film is applied to the surface of the opening, and a peripheral edge of a sealing lid is joined to the surface of the peripheral edge of the opening, and the inner surface of the sealing lid is located inside the surface of the solder resist coating. The electronic component mounting substrate is characterized in that: It is most remarkable in the present invention that the substrate is coated with a solder resist film except for the periphery of the opening of the recess, and the periphery of the sealing lid is joined to the surface of the periphery of the opening. The inner surface of the sealing lid is located inside the surface of the solder resist coating.
【０００７】上記ソルダーレジスト被膜は，例えばエポ
キシ樹脂，トリアジン樹脂を用いて，約４０〜５０μｍ
の厚みを有する塗膜で形成してある。また，上記ソルダ
ーレジスト被膜を形成するに当たっては，上記開口部周
縁に対して例えばマスクを施しておくことが好ましい。
これにより，該開口部周縁にソルダーレジスト被膜を有
しない部分を，精度良く容易に形成することができる。The above-mentioned solder resist film is made of, for example, an epoxy resin or a triazine resin to a thickness of about 40 to 50 μm.
It is formed with a coating film having a thickness of In forming the solder resist film, it is preferable that, for example, a mask is applied to the periphery of the opening.
This makes it possible to easily and accurately form a portion having no solder resist coating on the periphery of the opening.
【０００８】また，上記封止蓋としては，例えば，アル
ミニウム板や銅板等の金属材料，上記基板と同質のガラ
スエポキシ基板材料，セラミックス基板材料を用いる。
そして，該封止蓋の周縁部は，上記開口部周縁の表面に
対して，例えば接着剤を介して接合する。また，上記封
止蓋の周縁部を開口部周縁の表面に接合するに当たって
は，該封止蓋の内側面をソルダーレジスト被膜の表面よ
りも内部に位置させる。Further, as the sealing lid, for example, a metal material such as an aluminum plate or a copper plate, a glass epoxy substrate material of the same quality as the substrate, and a ceramic substrate material are used.
The peripheral edge of the sealing lid is joined to the surface of the peripheral edge of the opening via, for example, an adhesive. In joining the peripheral edge of the sealing lid to the surface of the opening peripheral edge, the inner surface of the sealing lid is located inside the surface of the solder resist coating.
【０００９】[0009]
【作用及び効果】本発明においては，基板の表面上に，
凹部の開口部周縁を除いて，ソルダーレジスト被膜が施
されている。そのため，ソルダーレジスト被膜の表面と
基板の表面との間には，該ソルダーレジスト被膜の厚み
分だけ，段差を生じることになる。 そこで，上記開口
部周縁の表面に対して，上記封止蓋の周縁部を直接接合
する。そのため，封止蓋は上記段差の間に嵌め込まれた
状態となる。それ故，本発明によれば，従来の基板のご
とく，切込み凹部，枠状ダム部を設ける必要がなく，作
業能率に優れることになる。[Operation and Effect] In the present invention, on the surface of the substrate,
Except for the periphery of the opening of the recess, a solder resist coating is applied. Therefore, a step is generated between the surface of the solder resist film and the surface of the substrate by the thickness of the solder resist film. Therefore, the peripheral portion of the sealing lid is directly joined to the surface of the peripheral portion of the opening. Therefore, the sealing lid is in a state of being fitted between the steps. Therefore, according to the present invention, there is no need to provide a cut recess and a frame-shaped dam as in the case of a conventional substrate, and the work efficiency is excellent.
【００１０】またそのため，封止蓋の取付位置精度に優
れ，また該封止蓋の位置ずれ等による取付不良を生ずる
ことがない。それ故，本発明によれば，封止蓋の取付位
置精度に優れ，作業能率が良い，電子部品搭載用基板を
提供することができる。[0010] For this reason, the mounting position accuracy of the sealing lid is excellent, and the mounting defect due to the displacement of the sealing lid does not occur. Therefore, according to the present invention, it is possible to provide an electronic component mounting substrate that is excellent in the accuracy of the mounting position of the sealing lid and has good work efficiency.
【００１１】[0011]
【実施例】本発明の実施例にかかる電子部品搭載用基板
につき，図１〜図７を用いて説明する。即ち，図１に示
すごとく，本例にかかる電子部品搭載用基板において
は，その基板９における凹部９２内に電子部品８を搭載
し，封止蓋７を接合してなる。上記基板９には，図１，
図２，図６に示すごとく，段差状の凹部９２の開口部周
縁１を除いてソルダーレジスト被膜５が施されている。
また，図１に示すごとく，上記開口部周縁１の表面に対
して，封止蓋７の周縁部７１を接合してある。また，該
封止蓋７の内側面７２は，図１に示すごとく，ソルダー
レジスト被膜５の表面５１よりも内部に位置している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic component mounting board according to an embodiment of the present invention will be described with reference to FIGS. That is, as shown in FIG. 1, in the electronic component mounting board according to the present embodiment, the electronic component 8 is mounted in the concave portion 92 of the substrate 9 and the sealing lid 7 is joined. As shown in FIG.
As shown in FIGS. 2 and 6, the solder resist coating 5 is applied except for the peripheral edge 1 of the opening of the stepped concave portion 92.
Further, as shown in FIG. 1, a peripheral portion 71 of the sealing lid 7 is joined to the surface of the peripheral portion 1 of the opening. The inner side surface 72 of the sealing lid 7 is located inside the surface 51 of the solder resist coating 5 as shown in FIG.
【００１２】上記ソルダーレジスト被膜５は，トリアジ
ン樹脂を用いて，図２，図６に示すごとく，約４５μｍ
の厚みＳを有する塗膜で形成してある。また，上記封止
蓋７としては，上記基板９と同質のガラスエポキシ基板
材料を用いる。また，該基板９には，図３に示すごと
く，電子部品搭載用の溝状凹部９２１及び配線回路９０
が形成してある。また，該封止蓋７は，図１，図５に示
すごとく，上記開口部周縁１の全体を覆えるよう，略正
方形を有する。そして，該封止蓋７の周縁部７１は，上
記開口部周縁１の表面に対して，接着剤６を介して接合
してある。As shown in FIGS. 2 and 6, the solder resist film 5 is made of triazine resin to have a thickness of about 45 μm.
Formed with a coating film having a thickness S. Further, as the sealing lid 7, a glass epoxy substrate material of the same quality as the substrate 9 is used. As shown in FIG. 3, the substrate 9 has a groove-shaped recess 921 for mounting electronic components and a wiring circuit 90.
Is formed. Further, as shown in FIGS. 1 and 5, the sealing lid 7 has a substantially square shape so as to cover the entire periphery 1 of the opening. The peripheral edge 71 of the sealing lid 7 is joined to the surface of the opening peripheral edge 1 via an adhesive 6.
【００１３】ここで注目すべきことは，上記封止蓋７の
周縁部７１を開口部周縁１の表面上に接合するに当たっ
ては，図１に示すごとく，該封止蓋７の内側面７２がソ
ルダーレジスト被膜５の表面５１より内部に位置させる
ことである。即ち，図２に示すごとく，上記ソルダーレ
ジスト被膜５の表面５１と，基板９の表面９５との間に
は，段差ｔが生じている。そこで，上記開口部周縁１と
しての基板９の表面９５に対して，図１，図６に示すご
とく，上記封止蓋７を接着剤６により接合する。これに
より，図１に示すごとく，上記封止蓋７の内側面７１
は，ソルダーレジスト被膜５の表面５１よりも内部に位
置した状態で，接合される。同図において，符号９６は
マザーボード，９７は導体ピン，９８はランド，９９は
半田を示す。It should be noted that, when the peripheral edge 71 of the sealing lid 7 is joined to the surface of the opening peripheral edge 1, as shown in FIG. That is, the solder resist film 5 is located inside the surface 51 of the solder resist film 5. That is, as shown in FIG. 2, a step t occurs between the surface 51 of the solder resist film 5 and the surface 95 of the substrate 9. Therefore, as shown in FIGS. 1 and 6, the sealing lid 7 is bonded to the surface 95 of the substrate 9 as the opening peripheral edge 1 with an adhesive 6. As a result, as shown in FIG.
Are joined in a state where they are located inside the surface 51 of the solder resist film 5. In the figure, reference numeral 96 denotes a motherboard, 97 denotes a conductor pin, 98 denotes a land, and 99 denotes solder.
【００１４】ここで，上記電子部品搭載用基板の製造方
法について図３〜図７により説明する。まず，図３に示
すごとく，基板９に電子部品搭載用の溝状凹部９２１を
設ける。次に，該基板９上に，内部に配線回路９０及び
開口部９０１を有する基板９を接合する。これにより，
略中央部に，電子部品８を搭載する段付状の凹部９２を
形成する。Here, a method of manufacturing the electronic component mounting board will be described with reference to FIGS. First, as shown in FIG. 3, a groove-shaped recess 921 for mounting an electronic component is provided on the substrate 9. Next, the substrate 9 having the wiring circuit 90 and the opening 901 therein is bonded onto the substrate 9. This gives
At a substantially central portion, a stepped concave portion 92 for mounting the electronic component 8 is formed.
【００１５】次いで，図４，図５に示すごとく，上記開
口部９０１及びその周縁部１の表面に，逆凸板状のマス
ク３を施す。該マスク３は，図５に示すごとく，上記周
縁部１と略同形の正方形を有する。そして，基板９の表
面において該マスク３以外の部分に，ソルダーレジスト
膜５を形成する。その後，上記マスク３を除去し，図６
に示すごとく，上記周縁部１に，ソルダーレジスト被膜
を有しない基板９を得る。次いで，図７に示すごとく，
電子部品を搭載した後，上記周縁部１に，接着剤６を介
して封止蓋７を接合する。次に，作用効果につき説明す
る。Next, as shown in FIGS. 4 and 5, a mask 3 in the shape of an inverted convex plate is applied to the surface of the opening 901 and the periphery 1 thereof. As shown in FIG. 5, the mask 3 has a square having substantially the same shape as the peripheral portion 1. Then, a solder resist film 5 is formed on a portion other than the mask 3 on the surface of the substrate 9. Thereafter, the mask 3 is removed, and FIG.
As shown in (1), a substrate 9 having no solder resist film on the peripheral portion 1 is obtained. Next, as shown in FIG.
After mounting the electronic components, a sealing lid 7 is joined to the peripheral portion 1 via an adhesive 6. Next, the function and effect will be described.
【００１６】即ち，本例においては，図２，図６に示す
ごとく，基板９の表面９５上に，段付状の凹部９２の開
口部周縁１を除いて，ソルダーレジスト被膜５が施され
ている。そのため，図２に示すごとく，ソルダーレジス
ト被膜５の表面５１と基板９の表面９５との間には，該
ソルダーレジスト被膜５の厚み分だけ，段差ｔを生じて
いる。そこで，上記開口部周縁１の表面に対して，上記
段差の部分に上記封止蓋７を接着剤６を用いて接合すれ
ば良い。そのため，従来の基板のごとく，切込み凹部，
枠状ダム部を設ける必要がなく，作業能率に優れること
になる。That is, in the present embodiment, as shown in FIGS. 2 and 6, the solder resist coating 5 is applied to the surface 95 of the substrate 9 except for the opening edge 1 of the stepped concave portion 92. I have. Therefore, as shown in FIG. 2, a step t is generated between the surface 51 of the solder resist film 5 and the surface 95 of the substrate 9 by the thickness of the solder resist film 5. Therefore, the sealing lid 7 may be joined to the surface of the opening peripheral edge 1 at the step by using an adhesive 6. Therefore, like a conventional board,
There is no need to provide a frame-shaped dam, which results in excellent work efficiency.
【００１７】また，図４に示すごとく，ソルダーレジス
ト被膜５を施すに当たって，上記開口部周縁１に，マス
ク３を施している。そのため，ソルダーレジスト被膜５
が施されない部分を精度良く形成することができる。ま
た，そのため，封止蓋７の取付位置精度に優れ，また該
封止蓋７の位置ずれ等による取付不良を生ずることがな
い。それ故，本例によれば，封止蓋７の取付位置精度に
優れ，作業能率が良い，電子部品搭載用基板を得ること
ができる。As shown in FIG. 4, a mask 3 is applied to the periphery 1 of the opening when the solder resist film 5 is applied. Therefore, solder resist film 5
Can be formed with high precision. Therefore, the mounting position accuracy of the sealing lid 7 is excellent, and the mounting defect due to the displacement of the sealing lid 7 does not occur. Therefore, according to the present embodiment, it is possible to obtain an electronic component mounting board that is excellent in the mounting position accuracy of the sealing lid 7 and has good work efficiency.
【図１】実施例にかかる電子部品搭載用基板の断面図。FIG. 1 is a cross-sectional view of an electronic component mounting board according to an embodiment.
【図２】実施例にかかる電子部品搭載用基板の要部側面
図。FIG. 2 is a side view of a main part of the electronic component mounting board according to the embodiment.
【図３】実施例における，基板の凹部及び配線回路の形
成状態を示す断面図。FIG. 3 is a cross-sectional view showing a concave portion of a substrate and a formation state of a wiring circuit in the example.
【図４】実施例における，凹部の上方にマスクを施した
状態を示す，図５のＡ−Ａ矢視断面図。FIG. 4 is a cross-sectional view taken along the line AA of FIG. 5, showing a state in which a mask is applied above the concave portion in the embodiment.
【図５】図４における，要部平面図。FIG. 5 is a plan view of a main part in FIG. 4;
【図６】実施例における，基板の表面にソルダーレジス
ト被膜を施した状態を示す断面図。FIG. 6 is a cross-sectional view showing a state in which a solder resist film is applied to the surface of the substrate in the example.
【図７】実施例における，封止蓋の取り付け状態を示す
断面図。FIG. 7 is a cross-sectional view showing an attached state of a sealing lid in the embodiment.
【図８】従来例を示す電子部品搭載用の基板断面図。FIG. 8 is a sectional view of a substrate for mounting electronic components, showing a conventional example.
【図９】他の従来例を示す電子部品搭載用基板の断面
図。FIG. 9 is a cross-sectional view of an electronic component mounting board showing another conventional example.
１．．．開口部周縁， ３．．．マスク， ５．．．ソルダーレジスト被膜， ７．．．封止蓋， ７１．．．周縁部， ７２．．．内側面， ８．．．電子部品， ９．．．基板， ９２．．．凹部， 1. . . 2. the periphery of the opening; . . Mask, 5. . . 6. Solder resist coating, . . Sealing lid, 71. . . Peripheral part, 72. . . 7. inner surface, . . Electronic components, 9. . . Substrate, 92. . . Recess,
Claims (1)
し，その上方に封止蓋を接合してなる電子部品搭載用基
板において， 上記基板には凹部の開口部周縁を除いてソルダーレジス
ト被膜が施されており，また上記開口部周縁の表面には
封止蓋の周縁部を接合してなり，かつ該封止蓋の内側面
はソルダーレジスト被膜の表面よりも内部に位置してい
ることを特徴とする電子部品搭載用基板。1. An electronic component mounting substrate comprising an electronic component mounted in a recess in a substrate and a sealing lid bonded thereto, wherein the substrate is coated with a solder resist coating except for the periphery of the opening of the recess. In addition, the periphery of the opening is joined to the periphery of the sealing lid, and the inner surface of the sealing lid is located inside the surface of the solder resist coating. Characteristic electronic component mounting board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22113091A JP2906756B2 (en) | 1991-08-06 | 1991-08-06 | Substrate for mounting electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22113091A JP2906756B2 (en) | 1991-08-06 | 1991-08-06 | Substrate for mounting electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0541460A JPH0541460A (en) | 1993-02-19 |
| JP2906756B2 true JP2906756B2 (en) | 1999-06-21 |
Family
ID=16761928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22113091A Expired - Lifetime JP2906756B2 (en) | 1991-08-06 | 1991-08-06 | Substrate for mounting electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2906756B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4703424B2 (en) * | 2006-02-10 | 2011-06-15 | 大日本印刷株式会社 | Compound sensor package |
| JP5231382B2 (en) * | 2009-11-27 | 2013-07-10 | 新光電気工業株式会社 | Semiconductor device |
| KR20130041645A (en) * | 2011-10-17 | 2013-04-25 | 삼성전기주식회사 | Printed circuit board |
-
1991
- 1991-08-06 JP JP22113091A patent/JP2906756B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0541460A (en) | 1993-02-19 |
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