JP2900847B2 - Integrated circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit test apparatus, and more particularly to an integrated circuit test apparatus for evaluating the operation of an integrated circuit in a state of a chip or a wafer.

[0002]

2. Description of the Related Art In order to evaluate an integrated circuit on a semiconductor chip or wafer, a conventional integrated circuit test apparatus receives power supplies, clock signals, address signals and input data for the required number of chips and the number of inputs and outputs. 2. Description of the Related Art There is known an LSI tester which supplies a chip or a wafer and determines the output of the chip or the wafer by a determination circuit.

[0003] Known techniques relating to this LSI tester are disclosed, for example, in JP-A-62-243335 and JP-A-2-5.
No. 6947 and JP-A-2-239641. Further, for such a measurement, a device in which a test circuit is provided on a chip or a wafer to be measured is also known.

Hereinafter, a memory tester for measuring a storage element will be described as an example of the LSI tester.

FIG. 8 shows an example of measurement of a wafer to be measured by a conventional memory tester. Conventional memory tester is 100
A memory tester main body 51 operating at MHz and a memory tester measurement station 52 are provided. The memory tester measurement station 52 is provided with a driver comparator 62 and a signal cable 57. The wafer to be measured 55 is placed on a vacuum chuck table 56 on a wafer prober 53 and measured via a probe card 54.

The wafer to be measured 5 by the memory tester 5
In the measurement of 5, the wafer prober 53
The relative positioning of the wafer 55 to be measured placed on the upper vacuum chuck table and the probe card 54 attached to the upper surface of the wafer prober 53 is performed to make contact.

Referring to FIG. 7, which schematically shows this relative alignment method, first, a wafer to be measured 102 is placed on a movable support jig 101, and an alignment mark 106 of an arbitrary chip on the wafer is set with, for example, a laser. Using the alignment device 105 capable of emitting light, the detected position coordinates (X1, Y1)
Is detected. Next, the reference coordinates (X0, Y0) of the alignment mark 106 'on the reference wafer position detection pattern 104 are detected by using the alignment device 105 described above.

A difference ΔX = X1−X0 in the X direction and a difference ΔY = Y1−Y0 in the X direction between the detected position coordinates (X1, Y1) and the reference coordinates (X0, Y0) are detected.
The movable support jig is moved so as to eliminate substantially, and the relative position between the wafer to be measured 106 and the wafer position detection pattern 104 is adjusted.

A blow card (not shown) also performs relative positioning of the wafer position detection pattern 104 and the relative position of the probe card 54 attached to the prober 53 shown in FIG. After that, a power supply and a signal are applied, a continuity test is performed, and electrical measurement of the wafer to be measured is performed.

FIG. 9 shows a block configuration of a measurement system of the memory tester. The memory tester main body 51 includes a central processing unit 61 therein, and a memory tester measuring station 52.
A driver / comparator 62 is provided therein. The memory under test 63 is connected to the driver / comparator 62 via signal lines 64, 65 and 66. The driver comparator 62 supplies a high-precision and high-speed clock as the RAS signal and the CAS signal to the memory 63 via the signal lines 64 and 65, and supplies test data via the signal line 66. The driver comparator 62 also determines the data output from the memory under measurement 63 to the signal line 66 with high accuracy.

[0011]

However, the conventional LSI
The tester needs to supply and measure clock signals, address signals, data, etc. with high accuracy and high speed according to the number of chips and the number of inputs and outputs of the integrated circuit under test.
There is a problem that the device becomes complicated and its control becomes difficult. For example, 16M-DRAM with input / output of 8 bits
There is a problem that the control of a memory tester capable of measuring 16 pieces of data at 100 MHz in parallel becomes technically sophisticated.

In addition, in order to perform relative positioning between the wafer to be measured and the probe card, it is necessary to detect respective alignment marks, and further perform the positioning operation using a laser light emitting device. The work efficiency at the time of replacing the measurement wafer is poor, and the maintenance work for keeping the optical axis of the laser beam stable is also poor .

An object of the present invention is to provide an integrated circuit test apparatus capable of solving such a problem and measuring an integrated circuit on a chip or a wafer with high accuracy with a small hardware configuration.

[0014]

SUMMARY OF THE INVENTION An integrated circuit test apparatus according to the present invention inputs a power supply and a signal necessary for the operation of an integrated circuit under test formed on a substrate and measures the output. in integrated circuit testing apparatus having a test unit, comprising a semiconductor chip or wafer in which at least part of which is formed of electrically contactable at the testing means via the contact member to the measured integrated circuit, the semiconductor chip or
On the wafer, comprises four positioning pad for contacting the said contact material semiconductor chip or wafer, the four alignment pads are arranged in a square shape, the four
Semiconductor chips or wafers with alignment pads
4 input to receive the input level corresponding to the relative position coordinate value above
And the output of the four-input NAND circuit.
Inverter and its gate connected to the inverter
Connect its drain to the first power supply and output its source
A first N-channel MOSFET connected to OUT;
Connect its gate to the inverter and its drain
Connected to the output OUT and its source connected to the second power supply.
Alignment with a second N-channel MOSFET
This is a configuration having a bias detection circuit .

In the integrated circuit testing apparatus of the present invention, the integrated circuit to be measured may be connected to the integrated circuit under test in a state in which the contact material pad does not contact any of the four alignment pads or in a state in which all of the four alignment pads contact each other. The determination of the relative alignment with the semiconductor chip or the wafer can also be made.

In the following description, a technology using silicon as a semiconductor is assumed, and a semiconductor chip or a wafer on which at least a part of the test means is formed is referred to as a “silicon tester”.

This silicon tester uses n bits (n) for each of m chips (m is a positive integer) from one bit of data for one chip of the integrated circuit under test.
Means for generating data of a positive integer) The integrated circuit under test formed on one wafer is divided into a blocks (a is a positive integer), and one of the blocks is selected for measurement. Means, means for selecting and measuring one chip of the integrated circuit to be measured, and the like.

[0018]

A part or all of the function of the LSI tester is provided on a semiconductor chip or a wafer to form a silicon tester.
This is electrically contacted with the integrated circuit to be measured via the contact material. As a result, all signals necessary for the test are set to L.
There is no need to pull out from the SI tester via a signal line. In particular, the hardware of the LSI tester can be simplified by incorporating the functions of a high-precision and high-speed driver and comparator for multiple inputs and outputs in parallel with multiple chips in a silicon tester. In addition, since the silicon tester has an alignment pad for determining whether or not it is electrically connected to a contact material or a predetermined reference pad of the integrated circuit to be measured, this allows the silicon tester and the integrated circuit to be measured to have an alignment pad. Adjust the relative position electrically.

[0019]

FIG. 1 is a view showing a configuration of a silicon tester of an integrated circuit test apparatus according to a first embodiment of the present invention, and shows an embodiment at a wafer level.

Referring to each of FIGS. 1 and 3,
The silicon tester 11 of this embodiment includes a multi-chip / bit control circuit 31, a block select decoder 32, a chip select decoder 33, a p-speed control circuit 34, a P-speed algorithm circuit 35, a self-overcurrent protection circuit 36, a chip Internal test circuit 38, fail memory circuit 39, current control circuit 40, comparator circuit 41 and on-chip capacitor 42, measuring circuit 12 and pad 43, positioning circuit 13 and positioning pads 22, 23, 24 and 25. Is provided.

Further, the alignment circuit 13 has alignment detection circuits 2, 3, 4, and 5. Referring to FIG. 2, the alignment detection circuits (2 to 5) receive the NAND 14 which receives as input coordinate values (X0, X1, Y0, Y1) corresponding to the relative positions of the alignment pads (22 to 25).
And MOS transistor 1 receiving the output of NAND 14
7 and a MOS transistor 16 which receives the inverted output of the NAND 14.

Referring again to FIG. 3, the multi-chip / bit control circuit 31 converts the data of one bit (or one input / output) of one chip supplied from the memory tester into a decoder circuit, an input / output and an address. Chips (m is a positive integer) and n bits (n
Is a positive integer). When the silicon tester measures at the wafer level, the block selection decoder 32 divides the measured wafer into a blocks (a is a positive integer) and selects one of the blocks as a measurement target. The chip selection decoder 33
When measuring at the level, an arbitrary chip on the wafer to be measured is selected. The p-times speed control circuit 34 uses the phase locked loop to adjust the clock frequency supplied from the memory tester.
(P is an integer of 2 or more). When the p-times control circuit 34 operates, the p-times speed algorithm circuit 35 uses the up / down counter and the latch circuit to generate a test pattern after the second cycle of the p-times speed operation that is not supplied from the memory tester. . Self overcurrent protection circuit 3
6 stops current supply to a chip in which an overcurrent exceeding the rating flows, using a flip-flop having a reset function. The positioning circuit 37 has b (where b is a positive number) arranged for an arbitrary pad of the chip to be measured so that the pad of the silicon tester and the pad of the chip to be measured can be aligned. DC signal from the memory tester is supplied to the (integer) pad via the signal switching circuit. The in-chip test circuit 38 has a built-in dummy chip circuit corresponding to a part of the function of the chip under test, and performs self-diagnosis of the operation of the memory tester by measuring the dummy chip circuit. The fail memory circuit 39
When the measurement result of the chip to be measured is defective, the content of the defect is held by the flip-flop circuit. The current control circuit 40 divides the clock frequency from the memory tester to 1 / c (c is an integer of 2 or more) by a frequency dividing circuit when performing multi-chip parallel measurement of the wafer to be measured at the wafer level. The current is controlled by reducing the speed or by dividing the wafer to be measured into arbitrary blocks and sequentially selecting the blocks. The comparator circuit 41 determines the measurement result of the chip to be measured. On-chip capacitor 4
2 operates as a bypass capacitor with the chip to be measured.

All of the above circuits need not be provided on a silicon tester. For example, when measurement is performed on a chip basis, some of the circuits can be omitted.

FIG. 4 is a timing chart for explaining the operation of the silicon tester shown in FIG. Time t in the measurement cycle of 40 ns (time t1 to t5) from the memory tester
When each signal is set for 10 ns from 1 to t2, p
Double speed control circuit 34 and p double speed algorithm circuit 35
Copies the waveforms at times t1 to t2 by a phase locked loop, an up / down counter and a latch circuit, and copies the waveforms at times t2 to t3, times t3 to t4, and times t4 to t5.
Generates and outputs a copy waveform. The times t1 to t2 are the read “H” portion of the marking increment, the write “L” at the times t2 to t3, the read “H” at the address [A + 1] at the times t3 to t4, and the time t.
The change between the "L" level and the "H" level of each signal of the write "L" from 4 to t5 and the address change are performed by the p-times speed algorithm circuit 35, and the "H" level of each signal is changed.
Level to "L" level or "L" level to "H"
The setting of the time of the transition point to the level is performed by the p-times speed control circuit 34.

FIG. 5 is a view showing an integrated circuit test apparatus to which the silicon tester of one embodiment of the present invention is applied, and shows an embodiment at a wafer level. In this case, a memory tester 51 operating at 25 MHz and a driver 62 having only one I / O are provided for inputting a power supply and a signal necessary for operating the circuit to the measured wafer 74 and measuring the output. , Signal cable 57, silicon tester
And a wafer 72. Further, the silicon tester wafer 72 and the wafer to be measured 74 are mounted on separate measuring jigs 71, respectively, and are electrically connected to each other via a piezoelectric conductive rubber 73 as a contact material. silicon·
The tester wafer 72 is provided with some or all functions for testing.

Next, the operation of this embodiment will be described. In this case, the number of chips to be measured is not one,
A part of all the chips of the wafer 74 to be measured, for example, 96
This is 16 chips out of the chips.

In this case, a signal for one input of one chip is supplied from the memory tester 51 to the silicon tester wafer 72. In the silicon tester wafer 72,
Eight input data for 16 chips is generated by an exclusive OR circuit of a latch circuit of a multi-chip / bit conversion control circuit,
A block selection decoder divides 96 chips into 6 blocks, selects 16 chips in one block, and supplies each signal.

First, the wafer to be measured 74 is a non-defective 16M-D
The case of a RAM chip will be described as an example. In this case, a signal for the test is supplied from the silicon tester chip 72 to the wafer 74 to be measured via the piezoelectric conductive rubber 73.
The output of the chip under test is transmitted to the silicon tester chip 72 via the piezoelectric conductive rubber 73, the comparator circuit judges the non-defective product, and is transmitted to the memory tester 51 via the signal line cable 57.

The measured wafer 74 has a marking defect 16
Similarly, in the case of an M-DRAM chip,
A test signal is supplied from the tester chip 72 to the wafer under test 74 via the piezoelectric conductive rubber 73, and the output of the chip under test is supplied to the silicon wafer via the piezoelectric conductive rubber 73.
It is transmitted to the tester chip 72. At this time, in the comparator circuit in the silicon tester chip 72, for example, since the output of the "L" level arrives at the place where the expected value is the "H" level, it is determined that the chip to be measured is defective. , The defective signal is transmitted to the memory tester 51 via the signal line 57. Also, the failure result is
It is also held in the memory circuit.

If there is a fault in the measured wafer 74 in which an overcurrent flows during standby, the self-overcurrent protection circuit operates when the chip is set and power is applied. As a result, the current supply to the chip to be measured is stopped, and a defective standby current is transmitted to the memory tester.

Next, the relative alignment between the silicon tester chip 11 and the wafer to be measured will be described with reference to FIG. In this case, the silicon tester chip 11
The projection 78 of the piezoelectric conductive rubber 73 shown in FIG. 5 is fitted to the relative positions of the positioning pads (22 to 25) to perform relative positioning between the silicon tester chip 11 and the wafer to be measured. The signals of the alignment pads (22 to 25) are supplied to the alignment detection circuits (2 to 5) by wirings (26 to 29).
Is transmitted to

First, when the projection 78 of the piezoelectric conductive rubber 73 and the positioning pad 22 come into contact with each other, the alignment detection circuit 2 applies a potential (for example, 2 volts) applied to the projection 78 of the piezoelectric conductive rubber 73 to a MOS transistor. 16 to output OUT. Also, the piezoelectric conductive rubber 7
When the third projection 78 and the positioning pad 22 are not in contact with each other, the MOS transistor 16 is turned off, and the potential applied to the projection 78 of the piezoelectric conductive rubber 73 (for example, 2 volts)
Output OU via MOS transistor 17
Output 0 volt potential to T.

Similarly, the alignment detection circuit 3 outputs a potential (for example, 2 volts) applied to the projection 78 of the piezoelectric conductive rubber 73 when the projection 78 of the piezoelectric conductive rubber 73 contacts the alignment pad 23. I do. When the projection 78 of the piezoelectric conductive rubber 73 is not in contact with the positioning pad 23, a 0 volt potential is output instead of the potential (for example, 2 volts) applied to the projection 78 of the piezoelectric conductive rubber 73. . The alignment detection circuit 4 outputs a potential (for example, 2 volts) applied to the projection 78 of the piezoelectric conductive rubber 73 when the projection 78 of the piezoelectric conductive rubber 73 comes into contact with the alignment pad 24. Also, the projection 78 of the piezoelectric conductive rubber 73
When the positioning pad 24 is not in contact with the positioning pad 24, a potential of 0 volt is output instead of the potential (for example, 2 volt) applied to the projection 78 of the piezoelectric conductive rubber 73. The alignment detection circuit 5 aligns with the protrusion 78 of the piezoelectric conductive rubber 73.
When the pad 25 comes into contact with the pad 25, the protrusion 7
8 is output (for example, 2 volts).
In addition, the positioning pad is aligned with the protrusion 78 of the piezoelectric conductive rubber 73.
When the contact 25 is not in contact, the potential (for example, 2 volts) applied to the protrusion 78 of the piezoelectric conductive rubber 73 is set to 0 instead of 0.
Outputs volt potential.

Further, these alignment detecting circuits (2
The selection of the outputs of (5) to (5) is based on the silicon tester chip 11
The input levels corresponding to the coordinates (X0, Y0) and (X1, Y1) corresponding to the relative positions of the positioning pads (22 to 25) are input to the NAND circuit 14 and decoded.

The determination of the relative alignment between the silicon tester chip 11 and the wafer to be measured is made in the state 6 in which the projection 78 of the piezoelectric conductive rubber 73 does not contact any of the alignment pads (22 to 25), that is, Alignment detection circuit (2
In all of the cases (1) to (5), when 0 volt is detected in the output, it is determined that the relative alignment between the silicon tester chip 11 and the wafer to be measured is perfect (FIG. 6A).

As shown in FIG. 6B, the projections 78 of the piezoelectric conductive rubber 73 are aligned with the positioning pads (22 to 2).
5) The state 7 in which all the contacts are made, that is, when all of the alignment detection circuits (2 to 5) detect 2 volts at their outputs, the relative alignment between the silicon tester chip 11 and the wafer to be measured is performed. It is needless to say that a criterion for judging that is complete can be set.

The silicon tester shown in FIGS. 3 and 4 is intended for measurement at the wafer level.
Modifications for chip-by-chip measurements are also possible.

In the above description, the integrated circuit under test is a DRAM
Although the description has been given of the case of a wafer on which a chip or a DRAM chip is formed, the present invention can be similarly applied to measurement of other integrated circuits.

[0039]

As described above, the integrated circuit test apparatus of the present invention has at least a part of the functions of the LSI tester.
It is provided on a silicon tester made of a semiconductor chip or a wafer capable of electrically contacting the integrated circuit to be measured via a contact material. In addition, since the silicon tester has an alignment pad for determining whether or not it is electrically connected to a contact material or a predetermined reference pad of the integrated circuit to be measured, this allows the silicon tester and the integrated circuit to be measured to have an alignment pad. Since the relative position can be electrically adjusted and the check of the silicon tester measurement system or the measurement accuracy is performed prior to the LSI test, high-precision and high-speed measurement for multi-chip parallel and multi-input / output of the LSI tester is performed. Becomes possible.

In the present invention, the functions of the driver and the comparator are performed by a silicon tester, so that the LSI tester main body only needs to have one 1-input / output hardware.
In addition, the same measurement as that of the related art can be performed using a memory tester whose function is simplified with high accuracy at 25 MHz operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an integrated circuit test apparatus according to one embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a positioning circuit of the integrated circuit test apparatus according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a silicon tester.

FIG. 4 is a timing chart illustrating the operation of the silicon tester.

FIG. 5 is a diagram showing a configuration of an application of the integrated circuit test apparatus according to one embodiment of the present invention.

FIG. 6 is a view showing an alignment reference pad of the integrated circuit test apparatus according to one embodiment of the present invention.

FIG. 7 is a diagram showing a measurement example using a conventional memory tester.

FIG. 8 is a diagram showing another measurement example using a conventional memory tester.

FIG. 9 is a diagram showing a block configuration of a measurement system of the memory tester.

[Explanation of symbols]

1,51 Memory tester 2,3,4,5 Alignment detection circuit 6 Alignment mark does not contact piezoelectric conductive rubber
State 7: Contact between the piezoelectric conductive rubber and the alignment mark
State 11 Silicon tester wafer 12 Measurement circuit 13 Alignment circuit 21 Alignment pad group 22, 23, 24, 25 Alignment pad 26, 27, 28, 29 Signal line 31 Multi-chip / bit control circuit 32 Blockon Selection decoder 33 chip selection decoder 34 p-times speed control circuit 35 p-times speed algorithm circuit 36 self-overcurrent protection circuit 37 positioning circuit 38 in-chip test circuit 39 fail memory circuit 40 current control circuit 41 comparator circuit 42 on-chip capacitor 43 pad 52 memory tester measuring station 53 a wafer prober 54 probe card 55 to be measured wafer 56 vacuum Fuchaku base 56 57 signal line cable 61 central processing unit 62 the driver comparator 63 to be measured memory 64, 65 Line 71 fixture 72 silicon tester wafer 73, 78 piezoelectric conductive rubber 74 to be measured wafer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/66 H01L 21/822 H01L 27/04 G01R 31/28

Claims (2)

(57) [Claims] 1. An integrated circuit test apparatus comprising: test means for inputting a power supply and a signal necessary for the operation of an integrated circuit to be formed formed on a substrate and measuring an output of the integrated circuit. A semiconductor chip or a wafer having at least a part of the test means formed thereon and capable of electrically contacting the measurement integrated circuit via a contact material;
Or four alignment pads for contacting the contact material with the semiconductor chip or the wafer on the wafer, wherein the four alignment pads are arranged in a square shape, and the four alignment pads are Up to the semiconductor chip
Or the input level corresponding to the relative position coordinate value on the wafer.
Receiving 4-input NAND circuit and 4-input NAND circuit
And the gate of the inverter receiving the output of
Connected to a first power supply and its source
N-channel MOS having a source connected to output OUT
FET and its gate connected to the inverter
Connected to the output OUT and its source connected to the second
A second N-channel MOSFET connected to the source.
An integrated circuit test device, comprising: an alignment detection circuit . 2. The relative positioning between the integrated circuit to be measured and the semiconductor chip or wafer depending on a state in which the contact material pad does not contact any of the four positioning pads or a state in which all of the four positioning pads contact all of the four positioning pads. 2. The integrated circuit test apparatus according to claim 1, wherein the judgment is made.