JP2997884B2 - Television signal processing system - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital television (TV) signal processing system for simultaneously displaying multiple images on a single screen.

BACKGROUND OF THE INVENTION Recently, the interest in digital television has increased due to the increasing availability of inexpensive digital hardware and memory. Digital television allows a user to convert the format of an incoming video signal. For example, in a digital television having a picture-in-picture (pix-in-pix) function, a secondary or secondary video signal SVS (eg, a signal from a video tape recorder and an intermediate frequency circuit) is a primary or secondary video signal. A small image is defined on the display screen as an insert within the entire image determined by the primary video signal PVS (eg, signals from a television tuner and intermediate frequency circuitry).

When either the primary or secondary video signal is a non-standard signal, timing or skew errors may occur in the displayed inset image, appearing as jagged vertical edges. As used herein, a non-standard signal is a video signal that has a non-standard number of chrominance subcarrier cycles during a horizontal period, and typically has a non-constant, ie, varying, horizontal period. A typical example of a non-standard signal is a video cassette recorder (VC
R) or a video signal generated by a video disc player (VDP). Periodic variations (also known as time axis errors) in the horizontal line period are typically caused by tape or disk speed variations.

Skew error occurs not only when one (or both) of the incoming video signals is non-standard, but also when two standard video signals are received from two sources that are not synchronized with each other. This means that synchronization signals that are within the tolerance limits of the individual signal standard (eg, NTSC standard) have different frequencies, and the synchronization signals process in phase with respect to each other, causing skew errors.

In order to understand how such timing or skew errors affect the inserted image, the primary and secondary video signals PVS and SVS must be a typical picture-in-picture television receiver. It is useful to know how is processed in
The secondary video signal SVS is sampled and digitized at a point determined by the sampling clock signal. The digital samples representing this secondary video signal are then sub-sampled in both the horizontal and vertical directions to produce a series of samples representing the reduced image. For example, when reducing the size of the image to 3: 1, it is stored every two samples and every two lines, and intermediate samples and lines are removed.

Digital samples extracted during one field of the secondary video signal SVS are stored in a field memory. These samples are the display deflection signals (eg,
The horizontal synchronous component of the primary video signal PVS) is read from the memory using a clock signal having a desired relationship. The samples read from the memory are converted to an analog signal SVS 'representing a reduced secondary image. A video switch having an input terminal coupled to receive the primary video signal PVS and the reduced magnitude secondary video signal SVS 'indicates at each time an appropriate one of the two input signals. Supply to the device to generate small images within large images. Christopher
r) U.S. Pat. No. 4,638,360 entitled "Timing Correction for Picture-in-Picture Television Systems" issued to Mr. et al. discloses an example of a picture-in-picture television receiver and a skew error correction system used therein. Is described.

The above-mentioned patent issued to Christopher et al. Shows two embodiments of a picture-in-picture television receiver. In the first embodiment shown in FIG. 2, the sampling clock signal is fixed to the color burst component of the secondary video signal SVS. In the second embodiment shown in FIG. 3, the sampling clock signal is fixed to the color burst component of the primary video signal PVS. In both embodiments, the digital samples are subject to skew error correction. That is, (1) before the samples are stored in memory (to compensate for skew errors caused by variations in the horizontal line period of the secondary video signal SVS), and (2) after the samples are read from memory (primary (To correct a skew error caused by a change in the horizontal line period of the target video signal PVS), a skew error is corrected.

SUMMARY OF THE INVENTION An object of the present invention is to reliably correct a skew error generated when trying to synchronize two video signals with a simple and inexpensive circuit configuration.

SUMMARY OF THE INVENTION A television signal processing system for use with a display responsive to a periodic raster synchronization component (HSS _D ), comprising a video signal containing a periodic image synchronization component (HSS _S ). A clock generator (102) for generating a first clock signal (FCS); receiving the first clock signal and the periodic raster synchronization component; Line fixing means (104, 106, 108) for fixing the line to the periodic raster synchronization component, and receiving the first clock signal and responding to the periodic image synchronization component, A phase shifter (110) that has a phase that is adjusted once every cycle of the periodic image synchronization component so as to match the phase of the periodic image synchronization component, and 1 black A phase shifter (110) for generating a second clock signal having the same period as the clock signal; and a sampling circuit (120) for receiving the video signal and supplying video signal samples in synchronization with the second clock signal. , 122) responsive to the first and second clock signals, receiving video signal samples synchronized with the second clock signal and supplied from the sampling circuit at a constant sample rate; A clock conversion circuit (124) synchronized with the first clock signal and providing video signal samples at the constant sample rate; and coupled to the clock conversion circuit and synchronized with the first clock signal, Said television signal processing system comprising: memory means (150) for storing and outputting signal samples.

Effects of the Invention A skew error that occurs when trying to synchronize two video signals can be corrected with high reliability with a simple and inexpensive circuit configuration.

EXAMPLES In each figure, the lines interconnecting the various blocks are:
Either a single conductor connection for transmitting analog signals or a bus for transmitting binary digital signals. The value near the diagonal crossing that crosses an individual interconnect line indicates the number of parallel connections for that line or bus, and the value in parentheses indicates the sample repetition frequency.

Those skilled in the art of television signal processing will readily appreciate that the present invention may be implemented in either digital or analog form of the composite video signal. However, for convenience of detailed description, it is assumed that the composite video signal in this specification is a binary digital signal.

Further assume that the incoming video signal nominally matches the NTSC standard format. An example of a signal that nominally matches the NTSC standard format is a video signal generated by a video cassette recorder or video disc player (hereinafter referred to as a non-standard video signal).

FIG. 1 shows a memory-dependent television receiver 10 that processes video signals from two unrelated sources 12 and 14 simultaneously. Source 12 (eg, a TV antenna, tuner, and intermediate frequency circuit) provides a baseband first composite video signal CV1. Source 14 (eg, a video cassette recorder (VCR)) generates a baseband second composite video signal CV2.

The first and second composite video signals CV1 and CV2 are provided to a pair of electronic switches 16 and 18, respectively.
The switch 16 responding to the selection signal SS has two input signals CV
1 and CV2 (hereinafter referred to as a primary or main video signal PVS), and a third electronic switch 2
0 is supplied to the first input terminal. Inverted selection signal ▲
The second 18 in response to ▼ is the other of the two input signals CV1 and CV2 (hereinafter, the secondary or auxiliary video signal SVS).
That. ) Select the analog signal processing circuit (ASP) 50
To supply.

As mentioned earlier, the primary video signal PVS produces an overall large image on the TV screen, on which the reduced small image generated by the secondary video signal is superimposed. Is done. The user decides which of the two incoming video signals CV1 and CV2 is used to generate a large image. The remaining video signal is used to automatically generate a small image.
The control microprocessor (not shown) of the television receiver 10 responds to a user command by selecting the selection signal SS and
Generates ▼.

The analog signal processing circuit 50 includes a low-pass filter 52 and a band-pass filter 54. A low pass filter 52 having an upper cut-off frequency of about 1.5 MHz removes the chroma signal and passes the luma signal (called the secondary luma signal).
As will become apparent, low pass filter 52 also acts as an anti-aliasing filter in the horizontal direction. About 3.58
Bandpass filter 54 having a pass band of MHz ± 0.5 MHz to play chroma component C _S from the secondary video signal SVS. Chroma demodulator 56 combined to receive chroma signal C _S
Are a pair of baseband color difference signals U _S and V _S (eg,
RY and BY). The circuits in block 50 (eg, low pass filter 52, etc.) are conventional and will not be described in detail.

The secondary luma signal Y _S is supplied to a sync separation circuit 58 to extract horizontal and vertical sync pulses. The output of the sync separation circuit 58 is provided to a sync phase locked loop (PLL) 60, which generates a secondary horizontal sync signal HSS _S at its output. Synchronous phase locked loop 60 provides secondary video signal SVS
To enhance the insensitivity of horizontal timing information reproduced from the to the noise.

The horizontal and vertical sync pulses at the output of sync separator 58 are also supplied to low pass filter 62 to remove the horizontal sync pulses and generate only vertical sync pulses at its output. Vertical sync pulses from the low pass filter 62 is coupled to a threshold detector 64 to generate a secondary vertical sync signal VSS _S.

The output signal from the analog signal processing block 50 _{(e.g., Y S, U S, V} S, HSS S and VSS _S) is supplied to the video component processing circuit (VFP) 100 of the present invention. The analog output SVS 'of the video component processing circuit 100 representing the reduced size secondary image is coupled to a second input terminal of the video switch 20. As mentioned earlier, the fast switching signal FST
Switch 20 responsive to the two input signals PVS and SV
An appropriate one of S 'is supplied to a signal processing circuit 22 of the television receiver.

Signal processing circuit 22 generates red, green, and blue drive signals from the composite video signal provided by video switch 20. These signals are supplied to the red, green and blue electron guns of the picture tube or display 24. Signal processing circuit
The 22 reproduces a pair of horizontal and vertical deflection signals HDS _D and VDS _D from the primary video signal PVS and supplies them to the horizontal and vertical deflection windings 26 of the display device 24. The red, green, and blue electron beams responsive to each of the drive and deflection signals raster scan the screen 28 to produce the desired small image within the large image.

Next, the configuration and operation of a video component processing circuit embodying the present invention will be described with reference to FIG. Voltage controlled oscillator (VCO) 102 responsive to low-pass filtered phase error signal PES _L
Generates a first clock signal FCS which phase and frequency are fixed to the horizontal synchronizing component HSS _D of the secondary video signal PVS.

The nominal frequency of the first clock signal FCS is set to 1374 times the horizontal sync frequency F _H. For NTSC system, the horizontal sync frequency F _H is set to 2/455 times the color subcarrier frequency 3.58 MHz. As a result, the horizontal synchronization frequency F _H is set to about 15.734 kHz, and the frequency F _FCS of the first clock signal is about 21.6 MHz.
Is set to

The counter 104 divides the first clock signal FCS by 1374,
Has a phase that is aligned with the first clock signal FCS, it generates a signal having a frequency substantially equal to the frequency F _H of the horizontal synchronizing component HSS _D of the secondary video signal PVS. Phase detector 10
6 compares the phase of the signal at the output of the counter 104 with the phase of the horizontal synchronizing signal for display HSS _D (which is in the form of a flyback signal from the horizontal deflection circuit of the television receiver) and outputs a phase error signal PES. Occurs. Phase error signal PES
Is low pass filtered by a low pass filter 108 to enhance the insensitivity to noise and to remove the input frequency to the phase detector 106. The low-pass filtered phase error signal PES _L is
It is supplied to the voltage controlled oscillator 102 to generate a first clock signal FCS of 21.6MHz which phase and frequency are fixed to the horizontal synchronizing component HSS _D of the secondary video signal PVS.

As mentioned earlier, the video component processing circuit 100, two clock signals, i.e., (1) a first clock signal by the phase and frequency are fixed to the horizontal synchronizing signal HSS _D display (main, or system, or A phase-shifted clock signal for each horizontal line to match the phase of the horizontal synchronization component HSS _S of the secondary video signal SVS. The second clock signal (also referred to as a skew-shifted clock signal) having a period equal to the period of the clock signal is used.

To generate a skew-shifted second clock signal SCS, video component processing circuit 100 includes a skew shifter or phase shifter 110. Skew shifter 110 has a different phase, but delays first clock signal FCS by a different amount to generate a plurality of clock signals, all having the same period as the first clock signal. A detection circuit (not shown) coupled to receive the multi-phase clock signal and responsive to the horizontal period component HSS _S of the secondary video signal SVS includes a clock signal having a phase closest to the horizontal synchronization component HSS _S Select Tarsi (Ta
rcy)-Hornoch U.S. Patent No. 3,911,368.
No. 1 discloses a circuit configuration suitable for use as a skew shifter or phase shifter 110. On August 7, 1987,
A phase shifter in a US patent filed by McNeely entitled "Signal Phase Matching Circuit"
Another circuit configuration of 110 is shown.

Line-fixed clock signal FCS and skew
The shifted clock signal SCS is supplied to N divide circuits 112 and 114, respectively, to generate a pair of reduced frequency clock signals FCS / N and SCS / N. In the picture-in-picture mode, the reduction rate N represents a reduction in the size of a small inserted image in both the horizontal and vertical directions. For example, the reduction ratio N takes any one of the integer values 1, 2, 3,... In the zoom mode, the reduction ratio N is 1
, Where the video signal stored in memory is not subsampled.

The luma and chroma signals Y _S , U from the analog processing circuit 50
_S and V _S are supplied to each input terminal of the analog multiplexer 120. Second clock signal of reduced frequency
The SCS / N is supplied to a 0 to 3 counter 116 which sends a control signal to an analog multiplexer 120. The analog multiplexer 120 generates at its output a series of values Y, U, Y, V, Y, U... At a reduced SCS / N frequency. An analog-to-digital (A / D) converter 122 responsive to the reduced frequency second clock signal SCS / N provides an incoming Y, U, Y,
Convert the V, Y... Sequence into a series of 6-bit digital samples with corresponding values.

First and second clock signals FC of reduced frequency
A clock conversion circuit 124 responsive to the S / N and SCS / N provides a series of digital samples (Y, U, Y, V, Y, ...) into a series of digital samples (at a frequency of FCS / N) that occur synchronously with the line-fixed clock signal. The clock conversion circuit 124 will be described later in detail with reference to FIGS.

Line fixed clock signal FC with reduced frequency
Demultiplexer 126 responsive to S / N classifies a series of digital samples occurring at the frequency of FCS / N into three streams:

* 5-bit luma samples generated at FCS / 2N frequency
Y _S (least significant bit (LSB) of the luma sample is discarded) * 6-bit chroma sample U _S * occurring at the frequency of FCS / 4N and representing one of the two color difference signals * frequency of FCS / 4N in occurs, chroma sample luma samples Y _S of 6 bits representing the other of the two color difference signals vertical aliasing prevention filters
Supplied to 128. Vertical anti-aliasing filter 128
Limits the maximum frequency of the luma signal in the vertical direction to reduce aliasing effects in reduced-size inserted images. As described above, the low-pass filter 52 of the analog processing block 50 reduces aliasing noise in the horizontal direction. The 5-bit luma sample Y _S from the vertical anti-aliasing filter 128 is provided to a first input of a multiplexer 130.

The 6-bit chroma samples U _S and V _S are supplied to sampling circuits 132 and 134, respectively. Sampling circuit
132 and 134 discard every other sample and generate chroma samples at the frequency of FCS / 8N. FC removed
The chroma samples U _S and V _{S at} the frequency of S / 8N are provided to the multiplexer 136. Multiplexer 136 generates the next series of 3-bit words at the frequency of FCS / 2N.

* The lower 3 bits, such as the top three bits * V _S of the lower 3 bits * V _S of the three most-significant bits * U _S of the U _S.

The 3-bit output of the multiplexer 136 is provided to a second input terminal of the multiplexer 130. Multiplexer 130 responsive to the FCS / N clock signal generates the next 4-bit sequence at the frequency of FCS / N.

* Y _S upper 4 bits * Y least significant bit and U _S upper 3 bits * Y _S upper 4 bits * Y _S least significant bit and U the lower 3 bits * Y _S upper four bits of the _S in the _S-a * lower 3 bits, etc. of the least significant bit and V _S of the upper 4 bits * Y _S of the upper 3 bits * Y _S of the least significant bit and V _S of Y _S.

The above 4-bit sample (4Y, 1Y + 3U, 4Y, 1Y + 3U, 4
Y, 1Y + 3V, 4Y, 1Y + 3V ...) is video field memory
150 and the timing and control signal generation circuit 140
Are stored in consecutive memory locations under the control of Field memory 150 has separate input and output ports, and consists of a 4-bit storage cell or location network composed of rows and columns. Perfect one field of the television signal (i.e., about 2 ¹⁸ 4
A sufficient number of rows to store the bits of the sample i.e. nibble (nibble)) (for example, there are 2 ⁸ or 256) and columns (e.g., 2 ¹⁰ i.e. 1024).

Timing and control signal generation circuit 140 generates a write address signal WAS and a read address signal RAW. The write address signal WAS includes a row address and a column address. The row address is the display vertical synchronization signal VS
It is reset once every field in response to S _D and advances once every N horizontal sync signal pulses HSS _D. Where N (1,
2,3 ...) are reduction rates. As indicated above, N is set equal to 1, 2, 3,... In the picture-in-picture mode, and is set equal to 1 in the zoom mode.

Column address is reset once every horizontal line in response to the display horizontal sync signal HSS _D, advanced once every N pulses of the line fixed clock signal FCS. Therefore, a digital image representing a reduced size insert image
Samples (ie, subsampled secondary video signals) are stored at sequential locations. 3 to 1
, Only one of three consecutive pixels and one of three consecutive horizontal lines are stored in memory.
Stored in 150.

4-bit digital sample (4Y, 1Y + 3U, 4Y, 1Y
+ 3U, 4Y, 1Y + 3V, 4Y, 1Y + 3V,...) Are read from the memory 150 at appropriate times at the frequency of the FCS under the control of the timing and control signal generation circuit 140. Read address signal R
AS contains both row and column addresses.
The row address is reset once for each field in response to the display vertical synchronization signal VSS _D , and the display horizontal synchronization signal HSS _D
Is advanced once for each pulse of. Column address is reset once every horizontal line in response to the display horizontal sync signal HSS _D, advanced once every pulse of the line fixed clock signal FCS.

Timing and control signal generating circuit 140, (1) display vertical sync signal VSS _D display horizontal synchronization signal for each pulse
Counts HSS _D pulses and (2) horizontal sync signal for display
Counts the pulses of the clock signal FCS, which is line secured for each pulse of the HSS _D, to determine whether to initiate what time the memory read operation in the mode of the picture-in-picture. Thereby, the small inserted image is positioned at a desired place in the large image.

An exemplary arrangement for generating the write address and the read address is described in US Pat. No. 4,249,213 entitled "Picture-in-Picture Television Receiver" and "Television Receiver with Means for Displaying Several Programs Simultaneously." No. 4,139,860, entitled "Machine".

Demultiplexer 160 provides a series of 4-bit digital samples (4Y, 1Y + 3U, 4Y, 1Y + 3U, 4Y, 1) of the frequency of the FSC.
Y + 3V, 4Y, 1Y + 3V ...) at a frequency of FCS / 2
Bit luma sample and a series of three bit chroma samples (3U, 3U, 3V, 3U) also occurring at the frequency of FCS / 2
V…). It can be seen that demultiplexer 160 and multiplexer 130 perform complementary functions. In other words, the format of the output streams Y _S and C _S of the demultiplexer 160 is the same as the format of each input stream Y _S and C _S to the multiplexer 130 (however, it is delayed by N: 1 and the speed is increased). The 5-bit output Y _S of the demultiplexer 160 is supplied to a first input terminal of the multiplexer 162. 3-bit output C _S of the demultiplexer 160 is supplied to the demultiplexer 164 is complementary to the multiplexer 136. The demultiplexer 164 recombines the upper 3 bits and the lower 3 bits of the U _S and V _S signals generated at the frequency of FCS / 2, and respectively generates the 6-bit U _S signal and V 6 generated at the frequency of FCS / 8.
Reconstruct the _S signal. The 6-bit signals U _S and V _S are supplied to the second and third terminals of the multiplexer 162, respectively.

Multiplexer 162, the desired boundary signal and blanking signal luma signal Y _S and chroma signals at the appropriate time
Operates to insert into each of U _S and V _S. digital·
The analog (D / A) converter 164 is a digital luma signal Y _S
And the chroma signals U _S and V _S are respectively converted into equivalent analog signals. The encoder 170 has an analog luma signal Y _S
And the chroma signals U _S and V _S are converted to an NTSC composite video signal (representing a reduced size insert image) for supply to the video switch 20. As mentioned earlier,
Video switch 20 responding to fast switching signal FST
Are two video signals, the primary video signal PVS
And the sub-sampled secondary video signal SVS '
Is supplied to the display 28 to generate a large image with an inset image. A suitable device that can be used as the encoder 170 is an integrated circuit HA11720 manufactured by Hitachi, Ltd.

Next, the clock conversion circuit 124 will be described with reference to FIGS. FIG. 3 shows the clock conversion circuit 124.
Is shown in block diagram form. FIG. 4 shows a reference signal generation circuit. FIG. 5 shows a circuit configuration for generating a plurality of clocks used in the clock conversion circuit 124 of FIG. Fig. 6-
FIG. 8 is a timing diagram useful for understanding the clock conversion circuit 124.

An important feature of the clock conversion circuit 124 of FIG. 3 is that this configuration allows the data to be read before the data is read, regardless of the relative phase of the skew-shifted clock signal SCS with respect to the phase of the line-fixed clock signal FCS. That is enough time to change.

In FIG. 3, continuous samples generated at the frequency of SCS / N in synchronization with the skew-shifted clock signal SCS are clocked by each rising edge of the SCS / N clock signal and input to the input latch 200. . Input latch 2
The output clock signals CL ₁ of 00, CL _2, CL ₃ and a plurality of intermediate four latches 202, 204 which are clocked by CL _4,
Supplied to 206 and 208. As shown in FIG. 6, clock signals CL ₁ , CL ₂ , CL ₃ and CL ₄ are skewed.
Synchronized with the shifted clock signal SCS, has a frequency of 1/4 of the frequency of the SCS / N clock signal, and has a phase sequentially shifted by an amount equal to one clock cycle of the SCS / N clock signal. .

Four coupled to receive the output of the intermediate latch 202-208, 4 inputs of multiplexer 210 responsive to 2-bit control signal C ₁ is supplied to the output latch 212 the output of one of the four intermediate latch . Latch 212 responsive to the FCS / N clock signal generates a series of digital samples occurring at the frequency of FCS / N in synchronization with line-fixed clock signal FCS.

The four clock signals CL ₁ -CL ₄ and the control signal C ₁ provide at least one horizontal synchronization component HSS _S of the secondary video signal SVS.
Generated in response to a reference signal REF obtained by delaying by a clock period. As mentioned earlier, the phase of the skew-shifted clock signal SCS is changed once per horizontal line in response to the HSS _S signal. The one clock cycle delay ensures that the rising edge 252 of the reference signal REF occurs after the phase transition of the deskewed clock signal SCS is completed.

To this end, the HSS _S signal, as shown in FIG.
The data is supplied to the data input of the D-type flip-flop 280.
The output Q of the first flip-flop 280 is provided to the data input of the second D-type flip-flop 282. Flip-flops 280 and 282 may be clocked by one of two clock signals FCS / N and SCS / N of reduced frequency, but in the embodiment shown in FIG.
Clocked by S / N signal. The reference signal REF is obtained at the Q output of the second flip-flop 282. Upstream edge 252 of the reference signal REF, as shown in Figure 6, is delayed at least one clock period from the rising edge 250 of the horizontal synchronizing component HSS _S of the secondary video signal SVS.

The four clock signals CL ₁ -CL ₄ are applied to the circuit 230 shown in FIG.
Generated by Circuit 230 responds to reference signal REF.
It includes a 0-3 synchronization counter 232 that is reset to 00 and is clocked by the SCS / N clock signal. Sixth
As shown, the reference signal R is lower during one period of the clock signal SCS / N in response to the rising edge 250 of the horizontal sync signal HSS _S. To this end, the circuit 230 includes a pair of flip-flops 234 and 236 and a NAND gate 238. The output Q ₁ of the first flip-flop 234 is provided to a first input of a NAND gate 238 and a data (D) input of a second flip-flop 236. Second flip-flop 236
_Two outputs is coupled to a second input of the NAND gate 238. The output R of the NAND gate 238 is supplied to the reset terminal of the synchronous counter 232.

The counter 232 responding to the SCS / N clock signal outputs the first clock signal CL which is the upper bit of the 2-bit count value.
Generate ₁ A plurality of cascaded flip-flops 240, 242 and 244 coupled to counter 232 provide second, third and fourth clock signals CL ₂ , CL ₃ and CL ₄ phase shifted at the timing shown in FIG. Occurs.

Second control signal C ₁ bit, starting count in response to the rising edge 250 of the horizontal sync signal HSS _S (e.g., 01) is input, clocked by the clock signal FCS / N 0-3
Generated by the second synchronization counter 214. Counter 2
Circuit 22 used to generate signal L which is supplied to 14
0 is the same as that of the reset signal generation circuit 246 in FIG.

The circuit 220 includes a pair of flip-flops 224, 226 and a NAND gate 228. Flip-flop 224 and
226 is clocked by the FCS / N clock signal.
The waveform of the load signal generation circuit 220 is similar to the waveform of the reset signal generation circuit 246 shown in FIG.

Once the start address is input to the synchronization counter 214 in response to the horizontal synchronization signal HSS _S , the counter 214 changes the address bits supplied to the multiplexer 210 until the maximum count value (ie, 11) is reached by using the FCS / N clock. Advance once for each pulse of the signal. The address bits are then reset (ie, 00) and counting continues (ie,
01,10,11,00,01…). The address bits (that is, the control signal C ₁ ) supplied to the multiplexer 210 are 00,01,10,1.
Latches 202, 20
The outputs of 4,206,208 are sequentially supplied to the output latch 212.

 The advantage of the clock conversion circuit 124 of FIG. 3 is two-fold.

* The intermediate latch 202 ... 208 are clocked by the clock signal CL ₁ ... CL ₄ having a period equal to 4 times the clock period, the data is input once is clocked in the middle of the latch, four Data is stable during the clock cycle.

* This system ensures that data is clocked into intermediate latches 202-208 and provides sufficient time (i.e., at least one clock period) between fetches. The reason will be described below with reference to FIGS. 7 and 8.

In the example of FIG. 7, the rising edge 254 of the SCS / N clock signal occurs immediately before the rising edge 252 of the reference signal REF that precedes the rising edge 256 of the FCS / N clock signal. Reset the clock signal generation circuit 230 (also control data writing to intermediate latches 202-208)
The reset pulse R extends between the rising edges 258 and 260 of the SCS / N clock signal. The load pulse L for inputting the start address (01) to the counter 214 (and for controlling the reading of data from the intermediate latches 202 to 208) is FCS /
Expand between the rising edges 256 and 262 of the N clock signal.

The time axis points at which data is written to and read from each of the intermediate latches 202-208 are indicated by x in FIG.
Indicated by a cross associated with the latch number in parentheses near the mark. Approximately one time between when data is clocked in and when data is clocked out.
It can be seen that there is a time lapse (δ) of the clock period, which gives a considerable data set time.

FIG. 8 shows that the rising edge 274 of the SCS / N clock signal
Another extreme case occurs immediately after the rising edge 272 of the reference signal REF, which occurs immediately after the rising edge 276 of the FCS / N clock signal. The reset signal R and the load signal L are generated as shown. It takes about 2 seconds between the time data is latched and the time data is fetched from the latch.
It can be seen that there is a time interval (δ) of the clock cycle.

As mentioned earlier, the signal processing circuitry used to produce special effects (eg, picture-in-picture, TV guide, fly-eye mode, zoom, etc.) uses two clocks. That is, (1) a system clock fixed to display and (2) a skew-shifted clock fixed to the horizontal synchronization component of the auxiliary video signal and having the same period as the system clock signal. The circuits used to implement the two clock systems, the skew shifter or phase shifter and the clock converter, are simple in construction, reliable and relatively inexpensive.

The embodiment described herein uses the primary video signal PV
The horizontal synchronization component HSS of the system clock FCS and the horizontal synchronization component HS of the secondary video signal SVS which are line-fixed to the horizontal synchronization component HSS _D (that is, the phase and frequency are fixed).
But is intended to use a second clock SCS that is phase locked to S _S, it is possible to set the relationship between these two clocks reversed. For example, the second clock SCS is line-fixed to the horizontal synchronization component HSS _S of the secondary video signal SVS, and the system clock FCS is
The phase may be fixed to the horizontal synchronization component HSS _D of VS.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a digital television receiver including a portion of a video component processing circuit according to the principles of the present invention. FIG. 2 shows a detailed block diagram of the video component processing circuit. FIG. 3 shows a clock conversion circuit suitable for use in the video component processing circuit of FIG. FIG. 4 shows a circuit for generating a reference signal REF suitable for use in the clock conversion circuit of FIG. FIG. 5 is a circuit for generating a plurality of clocks suitable for use in the clock conversion circuit of FIG. 6 to 8 are waveform diagrams useful for understanding the operation of the clock conversion circuit of FIG. 100: video component processing circuit, 106: phase detector, 110
…… Skew shifter (phase shifter), 120 …… Analog multiplexer, 122 …… Analog digital (A /
D) Converter, 124 clock conversion circuit, 140 timing and control signal generation circuit, 150 memory.

Continuation of the front page (56) References JP-A-62-102671 (JP, A) US Patent 4,423,915 (US, A) US Patent 4,139,860 (US, A) US Patent 4,638,360 (US, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/262-5/28 H04N 5/45

Claims (1)

(57) [Claims] 1. A television signal processing system for use with a display responsive to a periodic raster synchronization component, comprising: a source of a video signal including a periodic image synchronization component; Clock generation means for generating a clock signal; line fixing means for receiving the first clock signal and the periodic raster synchronization component and line fixing the first clock signal to the periodic raster synchronization component; A phase shifter that receives the first clock signal and is responsive to the periodic image synchronization component and generates a second clock signal, the phase shifter being in phase with the periodic image synchronization component. Generating a second clock signal having a phase adjusted once every period of the periodic image synchronization component and having the same period as the first clock signal; A phase shifter; a sampling circuit that receives the video signal and supplies a video signal sample in synchronization with the second clock signal; and a second clock in response to the first and second clock signals. A clock conversion circuit synchronized with a signal and receiving a video signal sample supplied from the sampling circuit at a constant sample rate, and synchronizing with the first clock signal and supplying a video signal sample at the constant sample rate And a memory means coupled to the clock conversion circuit for storing and outputting the video signal samples in synchronization with the first clock signal.