JP2993784B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an N-channel MOS transistor having an LDD structure in a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, miniaturization of the device has been promoted in order to increase the degree of device integration. In the MOS transistor of the device, a high electric field is generated at a drain portion, hot carriers are generated, and a gate is formed. Since the element is injected into the oxide film, the life of the element is shortened. In order to suppress the reduction in the device life, a lightly doped drain (LDD) having a low-concentration diffusion layer (n ⁻ layer) provided in a drain portion for an N-channel transistor.
Transistors having a structure have been used. FIG. 2 shows a schematic sectional view thereof. Conventionally, when this LDD transistor is used, the drain structure of all the transistors in the circuit element is the same, as is well known. That is, the transistors of the NN type output buffer circuit shown in FIG. 3 also have the same drain structure (LDD structure).

[0003]

However, in the transistor having the above-described structure, generation of hot carriers is suppressed and the life of the element is prolonged.
When a transistor is used, there is a problem that the electrostatic breakdown voltage against the injection of static electricity from the output pin (terminal) is reduced. In particular, the device life of an LDD transistor depends on the concentration of a low concentration portion (n ⁻ layer), and there is a drawback that the electrostatic breakdown voltage becomes lowest when the concentration is optimized with respect to the device life.

An object of the present invention is to provide a semiconductor device which suppresses the above-described decrease in electrostatic withstand voltage and maintains resistance to hot carriers as an integrated circuit element, and a method of manufacturing the same.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides a semiconductor device in which arsenic is ion-implanted only into the n ^- layer portion of an N-channel transistor of an output buffer section, thereby achieving a BVsd of an output buffer section transistor. In order to improve the electrostatic withstand voltage.

[0006]

DETAILED DESCRIPTION OF THE INVENTION The present invention as described above, n in the LDD structure of the N-channel transistors of only the output buffer unit ^- since the introduction of arsenic in the layer portion to improve the electrostatic withstand voltage can be obtained.

[0007]

FIG. 1 is a sectional view for explaining a manufacturing method according to an embodiment of the present invention. Here, the diagram on the left side of FIG. 1 corresponds to an N-channel transistor other than the output buffer unit, and the diagram on the right side of FIG. 1 corresponds to the N-channel transistor of the output buffer unit.

As shown in FIG. 1A, a silicon oxide film 1 is formed on a silicon semiconductor substrate 1 by a normal element isolation method, for example, a LOCOS method. Then, the silicon substrate 1 is dried at 800 ° C. to 900 ° C. or a gate oxide film 3 is formed at 150 to 250 ° by steam oxidation. Thereafter, a conductive film serving as a gate electrode, for example, phosphorus is 4 to 6 × 1
A 2000-4000 ° polysilicon film doped with 0 ²⁰ cm ⁻³ is formed, and a gate electrode 4 is obtained by using a usual photolithography technique and etching using a resist as a mask. Next, in order to form an n ⁻ layer of the LDD transistor, phosphorus ( ³¹ p ⁺ ) is ion-implanted into 1 to 3 × 10 3 using the field oxide film 2 and the gate electrode 4 as a mask.
^The n ⁻ layer 5 is obtained by implanting with a dose of ¹³ cm ⁻² and an energy of 40 to 60 keV. The dose and energy at this time are conditions under which the amount of generated hot carriers when the transistor is operated is minimized. The next output buffer N-channel transistor portion the n ^- introducing arsenic only to the layer. Here, a method using photolithography is shown.

The left side and the right side of FIG. 1B show a transistor portion other than the output buffer and a transistor portion having only the output buffer portion, respectively, as described above.

First, a positive resist, for example, is applied to the entire surface of the wafer (substrate), and thereafter, only the N-channel transistor portion of the output buffer portion is exposed using a mask. A structure other than the transistor portion is covered with a resist 6. Then arsenic the resist film 6 and the field oxide film 2 and the gate electrode 4 as a mask ⁽⁷⁵ As ⁺⁾ to 1 to 5 × 1
Ions are implanted at a dose of 0 ¹⁴ cm ^-2 and an energy of 40 to 100 keV. The reason why arsenic is used here is that, since arsenic diffuses slowly in silicon, the subsequent heat treatment suppresses the n ^- part lateral diffusion from becoming longer than that of transistors other than the output buffer. Also, this dose /
As a result of the electrostatic withstand voltage test within the energy range, 2
A withstand voltage of 000 V or more has been obtained.

Next, as shown in FIG. 1C, the resist film 6 is removed, and a CVD oxide film
0 ° is formed, and a sidewall 8 is obtained by using reactive ion etching. Thereafter, field oxide film 2, gate electrode 4, and side wall 8 are formed to form n ⁺ layer 9.
4-8 × 10 ¹⁵ cm ^{- 2} , 40-8 using arsenic as a mask
Ion implantation at 0 keV, 800-90 for activation
Heat treatment is performed at 0 ° C. for 30 to 60 minutes. At this stage, the N-channel transistors other than the output buffer section have the n ^- layer 5 of phosphorus alone as an LDD structure, and the concentration thereof depends on the phosphorus ion implantation conditions so that the generation of hot carriers during the operation of the transistor is minimized. Is set. On the other hand, the N-channel transistor of the output buffer section has a double n ^- layer 7 of phosphorus and arsenic as an LDD structure, and the surface concentration of arsenic is set to have a withstand voltage of 2000 V or more by an electrostatic test. It is set according to the ion implantation conditions.

Next, although not shown in the figure, a semiconductor integrated circuit device is obtained through formation of an intermediate insulating film, opening of a planarized contact hole, formation of a metal wiring, and formation of a final protective film.

[0013]

As described in detail above, according to the present invention, the LD of the N-channel transistor in the output buffer section is used.
Since arsenic is introduced into the n ^- layer portion of the D structure, an improvement in electrostatic withstand voltage can be obtained. In general, since the gate length of the N-channel transistor of the output buffer does not use a critical dimension, the hot carrier resistance as a semiconductor integrated circuit element is determined by the N-channel transistor other than the output buffer. Hot carrier resistance as an element is not impaired.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an LDD transistor.

FIG. 3 is an output buffer circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Si substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 n ⁻ layer 6 resist 7 n ⁻ layer (including As) 8 sidewall 9 n ⁺ layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8234 H01L 27/088 H01L 29/78

Claims (5)

(57) [Claims] 1. A gate electrode having a sidewall film on a side wall, a first impurity diffusion layer, and a first impurity diffusion layer adjacent to the first impurity diffusion layer, the impurity being higher in concentration than the first impurity diffusion layer. -Channel type MO having two impurity diffusion layers
In the semiconductor device having a plurality of S transistors, among the N-channel MOS transistors, the first impurity diffusion layer in an N-channel MOS transistor forming a buffer unit for outputting a signal includes phosphorus and arsenic; N-channel type MO that constitutes the part
The semiconductor, wherein the first impurity diffusion layer in the S transistor has a higher arsenic concentration than the first impurity diffusion layer in an N-channel MOS transistor other than the N-channel MOS transistor forming the buffer section. apparatus. 2. The semiconductor device according to claim 2, wherein said second impurity diffusion layer in said N-channel MOS transistor forming said buffer section contains arsenic at a higher concentration than arsenic contained in said first impurity diffusion layer as an impurity. The semiconductor device according to claim 1, wherein: 3. A method of manufacturing a semiconductor device, comprising: forming an N-channel type semiconductor device on a semiconductor substrate via a gate insulating film;
Providing a plurality of gate electrodes for the OS transistor; introducing phosphorus for forming a low-concentration impurity diffusion layer of each N-channel MOS transistor using the plurality of gate electrodes as a mask; Introducing arsenic into a region where an N-channel MOS transistor for the buffer unit is to be formed, using a gate electrode used for an N-channel MOS transistor for a buffer unit for outputting a signal as a mask, After the introduction, providing a sidewall on each of the plurality of gate electrodes, and introducing arsenic for forming a high-concentration impurity diffusion layer of each N-channel MOS transistor using the plurality of gate electrodes and the sidewalls as a mask. A method for manufacturing a semiconductor device, comprising: 4. The step of introducing arsenic into a region where an N-channel MOS transistor for a buffer section is to be formed, wherein the N-channel MOS transistor for the buffer section is provided.
4. The method of manufacturing a semiconductor device according to claim 3, wherein a resist is provided on a region where the N-channel MOS transistor is to be formed other than the region where the transistor is to be formed. 5. The introduction of phosphorus for the low concentration impurity diffusion layer formed, a dose of 1 to 5 × 10 ¹⁴ cm ^-2, 40
The method according to claim 3, wherein the method is performed at an energy of 100 keV.