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JP2989319B2 - Method of forming external electrodes in multilayer ceramic capacitors - Google Patents

Method of forming external electrodes in multilayer ceramic capacitors

Info

Publication number
JP2989319B2
JP2989319B2 JP3147025A JP14702591A JP2989319B2 JP 2989319 B2 JP2989319 B2 JP 2989319B2 JP 3147025 A JP3147025 A JP 3147025A JP 14702591 A JP14702591 A JP 14702591A JP 2989319 B2 JP2989319 B2 JP 2989319B2
Authority
JP
Japan
Prior art keywords
layer
dielectric ceramic
semiconductor layer
electrode layer
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3147025A
Other languages
Japanese (ja)
Other versions
JPH04369812A (en
Inventor
弘司 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP3147025A priority Critical patent/JP2989319B2/en
Publication of JPH04369812A publication Critical patent/JPH04369812A/en
Application granted granted Critical
Publication of JP2989319B2 publication Critical patent/JP2989319B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、誘電体セラミック層と
内部電極層とを交互に積み重ねた積層セラミックコンデ
ンサにおける外部電極の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming external electrodes in a multilayer ceramic capacitor in which dielectric ceramic layers and internal electrode layers are alternately stacked.

【0002】[0002]

【従来の技術】積層セラミックコンデンサは一般に、誘
電体セラミック層の間に内部電極層を介在させて積層誘
電体セラミックを形成し、このセラミックの端面に、内
部電極層に接続したAg主体の外部電極層を設けたもの
である。かかるコンデンサを基板にはんだ付けすると、
溶融はんだ中に外部電極層の成分であるAgが溶出する
所謂銀くわれが生じて、はんだ接合の信頼性の劣化が著
しくなるため、又ははんだの濡れが悪いことがあるた
め、これの防止策として外部電極層上に、耐熱性やはん
だ濡れ性を有する各種メッキ膜を施すことが行われてい
る。しかしながら、メッキ膜を形成する過程でメッキ液
が外部電極層の微細な空隙(ポーラス細孔)に浸入し、
更に誘電体セラミック層と内部電極層との接合界面まで
拡散し、絶縁抵抗が変化する等のコンデンサの電気的特
性の劣化を招いている。
2. Description of the Related Art In a multilayer ceramic capacitor, a multilayer dielectric ceramic is generally formed by interposing an internal electrode layer between dielectric ceramic layers, and an external electrode mainly composed of Ag connected to the internal electrode layer is formed on an end face of the ceramic. It is provided with a layer. When soldering such a capacitor to the board,
The so-called silver cracking, in which Ag, which is a component of the external electrode layer, is eluted in the molten solder, which significantly deteriorates the reliability of the solder joint, or the solder may have poor wettability. Various types of plating films having heat resistance and solder wettability are applied on external electrode layers. However, in the process of forming the plating film, the plating solution penetrates into fine voids (porous pores) of the external electrode layer,
Further, it diffuses to the junction interface between the dielectric ceramic layer and the internal electrode layer, causing deterioration of electrical characteristics of the capacitor such as a change in insulation resistance.

【0003】そこで、更にこの問題点を解決するため
に、外部電極層上に施すメッキ膜の形成過程でメッキ液
が積層誘電体セラミックの内部まで浸入しないようにし
た積層セラミックコンデンサが提案されている(特開平
2−277205号公報参照)。この公報に記載のコン
デンサは、図4に示すように、誘電体セラミック層10
と内部電極層11を交互に積層した積層誘電体セラミッ
ク12の端面に、所定の内部電極層11に接続した半導
体層13を設け、この半導体層13上に外部電極層14
を形成し、更に外部電極層14上にニッケル、銅等のメ
ッキ膜15と、はんだ、錫等のメッキ膜16を順に形成
したものである。
In order to further solve this problem, a multilayer ceramic capacitor has been proposed in which a plating solution is prevented from penetrating into a multilayer dielectric ceramic in a process of forming a plating film on an external electrode layer. (See JP-A-2-277205). The capacitor described in this publication has a dielectric ceramic layer 10 as shown in FIG.
A semiconductor layer 13 connected to a predetermined internal electrode layer 11 is provided on an end face of a laminated dielectric ceramic 12 in which the internal electrode layers 11 are alternately laminated.
And a plating film 15 of nickel, copper, or the like, and a plating film 16 of solder, tin, or the like are sequentially formed on the external electrode layer 14.

【0004】このコンデンサでは、内部電極層11と外
部電極層14との間に介在する半導体層13によって、
内部及び外部電極層11、14は電気的には接続されて
いるが、構造的には分断されている。従って、メッキ膜
15、16を形成する際に、メッキ液の積層誘電体セラ
ミック12内部への浸入が半導体層13によって阻止さ
れ、電気的特性が劣化しないのである。
In this capacitor, the semiconductor layer 13 interposed between the internal electrode layer 11 and the external electrode layer 14 causes
The inner and outer electrode layers 11 and 14 are electrically connected, but are structurally separated. Therefore, when the plating films 15 and 16 are formed, the infiltration of the plating solution into the laminated dielectric ceramic 12 is prevented by the semiconductor layer 13 and the electrical characteristics are not deteriorated.

【0005】[0005]

【発明が解決しようとする課題】前記公報に開示のコン
デンサの製法によれば、内部電極層となる導電ペースト
層を有するグリーンシートとペースト層を有しないグリ
ーンシートを所定数積層した積層体の端面に、半導体層
となる半導体化剤ペーストを塗布して乾燥した後に、焼
成して積層体の磁器化と半導体層の形成を同時に行って
いる。
According to the method of manufacturing a capacitor disclosed in the above publication, an end face of a laminated body in which a predetermined number of green sheets having a conductive paste layer serving as internal electrode layers and green sheets having no paste layer are laminated. Then, a semiconductor agent paste for forming a semiconductor layer is applied and dried, and then baked to simultaneously form the laminate into a ceramic and form a semiconductor layer.

【0006】しかしながら、この製法において、グリー
ンシート上に導電ペーストをスクリーン印刷法にて印刷
したものを積み重ねて熱圧着しただけの積層体は、誘電
体セラミック層10と内部電極層11との接合界面(図
4参照)が十分な接着強度を有していない。しかるに、
この積層体の端面に半導体化剤ペーストを塗布した後に
高温(約1300℃)で焼成すると、両層10、11が
接合界面で剥離したり欠けたりすることがある。両層1
0、11が一旦剥離すると焼成しても再接合することは
なく、両層10、11を一体化した積層セラミック焼結
体を得ることができないだけでなく、焼成後の積層セラ
ミック焼結体での剥離や欠け不良を選別する有効且つ経
済的な手段がない。
However, in this manufacturing method, a laminate in which conductive paste is printed on a green sheet by a screen printing method and is laminated by thermocompression bonding is used as a bonding interface between the dielectric ceramic layer 10 and the internal electrode layer 11. (See FIG. 4) does not have sufficient adhesive strength. However,
If the semiconductive agent paste is applied to the end face of the laminate and then baked at a high temperature (about 1300 ° C.), the two layers 10 and 11 may be separated or chipped at the joint interface. Both layers 1
Once the layers 0 and 11 are peeled off, they do not rejoin even if they are fired, so that not only can a multilayer ceramic sintered body integrating the two layers 10 and 11 be obtained, but also the fired multilayer ceramic sintered body can be used. There is no effective and economical means for selecting peeling or chipping defects.

【0007】従って、本発明の目的は、誘電体セラミッ
ク層と内部電極層との接合界面での剥離や欠けを誘発し
ない積層セラミックコンデンサにおける外部電極の形成
方法を提供することにある。
Accordingly, it is an object of the present invention to provide a method of forming external electrodes in a multilayer ceramic capacitor which does not induce peeling or chipping at a bonding interface between a dielectric ceramic layer and an internal electrode layer.

【0008】[0008]

【課題を解決するための手段】前記目的を達成するため
に、本発明の積層セラミックコンデンサにおける外部電
極の形成方法は、複数の誘電体セラミック層と複数の内
部電極層を交互に積み重ねた積層体を焼成した後、得ら
れた積層誘電体セラミックの端面に半導体層を形成・焼
成し、更に半導体層上に外部電極層を形成して焼付ける
ことを特徴とするものである。
In order to achieve the above object, a method of forming an external electrode in a multilayer ceramic capacitor according to the present invention is directed to a laminated body in which a plurality of dielectric ceramic layers and a plurality of internal electrode layers are alternately stacked. After firing, a semiconductor layer is formed and fired on the end face of the obtained laminated dielectric ceramic, and an external electrode layer is formed on the semiconductor layer and fired.

【0009】本発明の形成方法は、前記公報に開示の如
く積層体の端面に半導体化剤ペーストを塗布した後に焼
成して、積層体の磁器化と半導体層の形成を同時に行う
のではなく、まず積層体を焼成して積層誘電体セラミッ
クとした後に、このセラミックの端面に半導体化剤ペー
ストを塗布して焼成し、得られた半導体層上に外部電極
層となる導電ペーストを塗布して焼付ける。このため、
誘電体セラミック層と内部電極層を加圧・接着するだけ
でなく、半導体層を形成する前に積層体を焼成するの
で、両層の接合界面の接着強度が十分で、両層が一体化
した積層誘電体セラミックが得られる。この後に半導体
層を形成しても、その過程で両層が接合界面で剥離した
り欠けたりする致命的欠陥は生じない。
According to the formation method of the present invention, instead of applying a semiconducting agent paste to the end face of the laminate and firing it as disclosed in the above-mentioned publication, the porcelainization of the laminate and the formation of the semiconductor layer are performed simultaneously. First, the laminated body is fired to obtain a laminated dielectric ceramic, and then a semiconducting agent paste is applied to the end face of the ceramic and fired. wear. For this reason,
In addition to pressing and bonding the dielectric ceramic layer and the internal electrode layer, the laminate is fired before forming the semiconductor layer, so the bonding strength at the bonding interface between both layers is sufficient, and the two layers are integrated. A laminated dielectric ceramic is obtained. Even if a semiconductor layer is formed thereafter, a critical defect that both layers are separated or chipped at a bonding interface in the process does not occur.

【0010】[0010]

【実施例】以下、本発明の外部電極の形成方法を実施例
に基づいて説明する。図1はその形成方法に従って作製
した外部電極を有する積層セラミックコンデンサの断面
図である。このコンデンサは、複数の誘電体セラミック
層1と、セラミック層1と交互に積層した複数の内部電
極層2とからなる積層誘電体セラミック3の一対の端面
に、半導体層4を形成し、更に半導体層4上に外部電極
層5を形成したものである。半導体層4と外部電極層5
の構造は、その拡大図を図2に示すように、所定の内部
電極層2と接続した半導体層4が積層誘電体セラミック
3の端面に設けられ、半導体層4上に導電層51、下地
メッキ膜52、及びメッキ膜53からなる外部電極層5
が設けられている。図1及び図2から分かるように、コ
ンデンサの構造自体は図4に示す従来のものとほぼ同じ
である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The method for forming an external electrode according to the present invention will be described below with reference to embodiments. FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor having external electrodes manufactured according to the forming method. In this capacitor, a semiconductor layer 4 is formed on a pair of end faces of a laminated dielectric ceramic 3 composed of a plurality of dielectric ceramic layers 1 and a plurality of internal electrode layers 2 alternately laminated with the ceramic layers 1. The external electrode layer 5 is formed on the layer 4. Semiconductor layer 4 and external electrode layer 5
As shown in an enlarged view of FIG. 2, a semiconductor layer 4 connected to a predetermined internal electrode layer 2 is provided on an end face of a laminated dielectric ceramic 3, and a conductive layer 51 and a base plating are provided on the semiconductor layer 4. External electrode layer 5 composed of film 52 and plating film 53
Is provided. As can be seen from FIGS. 1 and 2, the structure of the capacitor itself is almost the same as the conventional one shown in FIG.

【0011】次に、上記構造のコンデンサの具体的な製
造について述べる。まず誘電体セラミックとしてのBa
TiO3 に、CeO2 、ZrO2 、MnCO2 の添加剤
を配合したものに、エチルセルロースと溶媒からなる結
合剤を加え、15時間分散・混練してスラリーを調製す
る。このスラリーをドクターブレード法によって成形し
て、厚さ20〜40μmのグリーンシートを得る。続い
て、Pd(パラジウム)を主成分とする内部電極剤とし
てのインクを、スクリーン印刷法を用いてグリーンシー
ト上に印刷する。そして、図3に示すように、インク
2’を印刷した複数枚のグリーンシート1’を積み重ね
ると共に、これの上下に未印刷の複数枚のグリーンシー
ト1’を重ねて積層体とし、この積層体を加圧・加熱し
た後に所定サイズに切断する。
Next, a specific production of the capacitor having the above structure will be described. First, Ba as a dielectric ceramic
A binder made of ethyl cellulose and a solvent is added to a mixture of TiO 3 and additives of CeO 2 , ZrO 2 and MnCO 2 , and the mixture is dispersed and kneaded for 15 hours to prepare a slurry. This slurry is formed by a doctor blade method to obtain a green sheet having a thickness of 20 to 40 μm. Subsequently, ink as an internal electrode agent containing Pd (palladium) as a main component is printed on the green sheet by using a screen printing method. Then, as shown in FIG. 3, a plurality of green sheets 1 'on which the ink 2' is printed are stacked, and a plurality of unprinted green sheets 1 'are stacked on and under the green sheets 1' to form a laminate. Is pressed and heated, and then cut into a predetermined size.

【0012】以後の工程からが本発明に係る外部電極の
形成方法に相当する。即ち、まずN2雰囲気中において約
500℃で積層体に対して脱バインダー処理を行った
後、約1300℃で十分に焼成する。これにより、誘電
体セラミック層と内部電極層との接着強度が十分な積層
誘電体セラミックが得られる。この誘電体セラミックを
面取りした後、正温度特性抵抗体(PTC)等の半導体
セラミックペーストをディッピング等によって誘電体セ
ラミックの一対の端面に塗着し、乾燥後に約1300℃
で焼結する。この際、半導体セラミックペースト中にP
d又はAg等の金属を配合してもよい。これにより、半
導体層が形成される。
The following steps correspond to the method of forming an external electrode according to the present invention. That is, the laminate is first subjected to a binder removal treatment at about 500 ° C. in an N 2 atmosphere, and then sufficiently fired at about 1300 ° C. Thereby, a laminated dielectric ceramic having a sufficient adhesive strength between the dielectric ceramic layer and the internal electrode layer can be obtained. After chamfering the dielectric ceramic, a semiconductor ceramic paste such as a positive temperature characteristic resistor (PTC) is applied to a pair of end faces of the dielectric ceramic by dipping or the like.
And sinter. At this time, P
A metal such as d or Ag may be blended. Thereby, a semiconductor layer is formed.

【0013】次いで、導電層剤としてAg/Pd又はA
gとフリットからなる導電ペーストを半導体層上に厚膜
に塗布し、約800℃で焼付けて、導電層を形成する。
更に、基板実装時のはんだ濡れ性や耐熱性を良好にする
ために、Ni、Cu等の下地メッキ膜と、はんだ、錫等
のメッキ膜を導電層上に順に施す。以上により、積層誘
電体セラミックの一対の端面に、半導体層と、導電層、
下地メッキ膜及びメッキ膜で構成される外部電極層とを
形成した、図1に示すような積層セラミックコンデンサ
が完成する。
Next, Ag / Pd or A is used as a conductive layer agent.
A conductive paste composed of g and frit is applied on the semiconductor layer in a thick film and baked at about 800 ° C. to form a conductive layer.
Further, in order to improve the solder wettability and heat resistance during mounting on the substrate, a base plating film of Ni, Cu or the like and a plating film of solder, tin or the like are sequentially applied on the conductive layer. As described above, the semiconductor layer, the conductive layer,
A multilayer ceramic capacitor as shown in FIG. 1 in which an underlying plating film and an external electrode layer composed of a plating film are formed is completed.

【0014】[0014]

【発明の効果】本発明の外部電極の形成方法は、以上説
明したように構成されるので、下記の効果を有する。 (1)まず積層体を焼成するので、得られる積層誘電体
セラミックにおける誘電体セラミック層と内部電極層と
の接着強度が十分である。このため、以後に積層誘電体
セラミックの端面に半導体層を形成しても、誘電体セラ
ミック層と内部電極層との接合界面での剥離や欠けは発
生しない。 (2)外部電極層上へのメッキ膜形成時にメッキ液は半
導体層によって積層誘電体セラミックの内部まで浸入し
ないため、コンデンサの劣化が防止される。
The method of forming an external electrode according to the present invention has the following effects because it is configured as described above. (1) Since the laminate is first fired, the adhesive strength between the dielectric ceramic layer and the internal electrode layer in the obtained laminated dielectric ceramic is sufficient. For this reason, even if a semiconductor layer is formed on the end face of the laminated dielectric ceramic, peeling or chipping does not occur at the bonding interface between the dielectric ceramic layer and the internal electrode layer. (2) Since the plating solution does not penetrate into the laminated dielectric ceramic due to the semiconductor layer when the plating film is formed on the external electrode layer, deterioration of the capacitor is prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の形成方法を用いて作製した外部電極を
有する積層セラミックコンデンサの断面図である。
FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor having external electrodes manufactured by using the forming method of the present invention.

【図2】図1のコンデンサの半導体層と外部電極層の一
部省略拡大図である。
FIG. 2 is a partially omitted enlarged view of a semiconductor layer and an external electrode layer of the capacitor of FIG. 1;

【図3】図1に示すようなコンデンサの製造において積
層体を得るための一工程図である。
FIG. 3 is a process chart for obtaining a laminate in the production of the capacitor as shown in FIG. 1;

【図4】従来の積層セラミックコンデンサの断面図であ
る。
FIG. 4 is a cross-sectional view of a conventional multilayer ceramic capacitor.

【符号の説明】[Explanation of symbols]

1 誘電体セラミック層 2 内部電極層 3 積層誘電体セラミック 4 半導体層 5 外部電極層 51 導電層 52 下地メッキ膜 53 メッキ膜 Reference Signs List 1 dielectric ceramic layer 2 internal electrode layer 3 laminated dielectric ceramic 4 semiconductor layer 5 external electrode layer 51 conductive layer 52 base plating film 53 plating film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】複数の誘電体セラミック層と、このセラミ
ック層と交互に積層した複数の内部電極層とからなる積
層誘電体セラミックの端面に、内部電極層に接続した半
導体層を形成し、半導体層上に外部電極層を形成してな
る積層セラミックコンデンサの外部電極の形成方法であ
って、前記誘電体セラミック層と内部電極層とからなる
積層体を焼成した後、得られた積層誘電体セラミックの
端面に半導体層を形成・焼成し、更に半導体層上に外部
電極層を形成して焼付けることを特徴とする積層セラミ
ックコンデンサにおける外部電極の形成方法。
A semiconductor layer connected to an internal electrode layer is formed on an end face of a laminated dielectric ceramic comprising a plurality of dielectric ceramic layers and a plurality of internal electrode layers alternately laminated with the ceramic layers. A method of forming an external electrode of a multilayer ceramic capacitor, comprising forming an external electrode layer on a layer, comprising: firing a multilayer body including the dielectric ceramic layer and an internal electrode layer; Forming a semiconductor layer on the end face of the multilayer ceramic capacitor and firing the same, and further forming an external electrode layer on the semiconductor layer and firing the semiconductor layer.
JP3147025A 1991-06-19 1991-06-19 Method of forming external electrodes in multilayer ceramic capacitors Expired - Fee Related JP2989319B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3147025A JP2989319B2 (en) 1991-06-19 1991-06-19 Method of forming external electrodes in multilayer ceramic capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3147025A JP2989319B2 (en) 1991-06-19 1991-06-19 Method of forming external electrodes in multilayer ceramic capacitors

Publications (2)

Publication Number Publication Date
JPH04369812A JPH04369812A (en) 1992-12-22
JP2989319B2 true JP2989319B2 (en) 1999-12-13

Family

ID=15420846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3147025A Expired - Fee Related JP2989319B2 (en) 1991-06-19 1991-06-19 Method of forming external electrodes in multilayer ceramic capacitors

Country Status (1)

Country Link
JP (1) JP2989319B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007046607A1 (en) * 2007-09-28 2009-04-02 Epcos Ag Electrical multilayer component and method for producing an electrical multilayer component

Also Published As

Publication number Publication date
JPH04369812A (en) 1992-12-22

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