JP2984429B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a counter circuit.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional general semiconductor integrated circuit (counter circuit). In FIG. 2, 10
a is an input terminal of the circuit, 16a is its output terminal, and 1
0b is a reset terminal. Reference numeral 14 denotes a logic circuit composed of basic logic elements.
The signal values 10c, 11a, 12a, 13a of 0 to 13 are
It is assumed that an output signal 14d is output when the value of the logic circuit 14 becomes a base value set by the base number setting signals 14a to 14c.

Next, the operation will be described with reference to the timing chart of FIG. In FIG. 4, it is assumed that a ternary counter is set by signals 14a to 14c.
First, a reset pulse is applied from the reset terminal 10b so that Q of all flip-flops becomes zero. When a signal as shown in FIG. 5A is applied from the input terminal 10a after reset, the signals are counted by the flip-flops 10 and 11, and the value becomes "1", as shown in FIGS.
At the timing of “1”, a signal 14d as shown in FIG.
A signal as shown in FIG. 4 (e) is output to an output terminal 16a via NOR circuits 15 and 16 constituting a flip-flop, and a reset signal is output to each flip-flop via an OR circuit 17 to reset. Is done. That is, it is a ternary counter that can obtain one cycle of the output signal for three cycles of the input pulse.

[0004]

Since the conventional semiconductor integrated circuit (counter) is configured as described above, the circuit must be designed by a combination of complicated logic circuits, and the design of the logic circuit is difficult. Delay of each logic element
If not taken into account, a spike signal etc
The counter may flip and the counter may malfunction.
Was. Further, the output waveform does not become close to the duty of 50% and becomes a general pulse waveform. In addition, there is a problem in that time of the delay from the input to the output in accordance with the number of stages of the flip-flop is to increase is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object to obtain a semiconductor integrated circuit which does not malfunction by a simple combination of logic elements. Further, an object of the present invention is to provide a semiconductor integrated circuit capable of keeping the delay time from input to output constant and small even if the number of flip-flop stages increases.

[0006]

Means for Solving the Problems A semiconductor integrated circuit according to the present invention, a shift register used in the counting section, the shift
AND of the outputs of each flip-flop that makes up the register
And a logic circuit section for
Receiving an output of the logical circuit unit and an output of the counting unit , and inverting a data output of the multiplexer;
The data output of the signal output section inverted by the inverting circuit section is input as input data of the counting section.

[0007]

[0008]

In the present invention, since the counting section is constituted by a shift register, the delay time from input to output is a delay by the shift register, and the data output of the multiplexer is inverted to be used as input data of the counting section. used, since the data in the shift register is configured to be one step advanced in a change in the input clock, late of each logic element
Operation can be performed reliably without considering the amount of delay,
Even if the number of flip-flop stages increases, the delay time does not increase.

Further, a logic circuit unit for calculating the logical product of the outputs of the flip-flops constituting the shift register is provided, and the multiplexer receives the output of the logic circuit unit and the output of the counting unit. It can also be operated as a decimal counter.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a counter circuit which is a semiconductor integrated circuit according to one embodiment of the present invention.
d is an output terminal, and 1b is a reset terminal. 1 to 4 are flip-flops constituting a shift register;
Reference numerals 5, 6, and 7 denote two-input AND circuits which use the outputs of the flip-flops adjacent to the flip-flops 1 to 4 as two-input signals, respectively, and 8 denotes a multiplexer which outputs 1c of the flip-flops 1 to 4. , 2a, 3a,
4a and the signals of the outputs 5a, 6a, 7a of the two inputs AND5-6 are selected based on the values set by the base number setting signals 8a-8c, and the result is output to the output terminal 8d. An inverting circuit 9 inverts the output of the multiplexer 8 and inputs the inverted signal to the data terminal of the flip-flop.

Next, the operation will be described with reference to the timing chart of FIG. Now it is 3 by the base number setting signals 8a to 8c.
It is assumed that it is set as a binary counter. In this case, the signal of the output 5a of the two-input AND 5 (see FIG. 3D) is selected by the multiplexer 8 and connected to the output terminal 8d. Therefore, the signals 1c (see FIG. 3 (b)) and 2a (see FIG. 3 (c)) which are the outputs of the flip-flops 1 and 2 are logically input to the shift register composed of the flip-flops 1 to 4 by the two-input AND5. The signal shown in FIG. 3D is inverted by the inverting circuit 9 and input.

Then, at the next input signal 1a, the data of the shift register advances by one stage, and the inverted two-input AN is inputted.
At D5, a signal based on the logical product is input as the data held in the flip-flop 1 in the next cycle, and the data held in the flip-flop 1 is sent to the flip-flop 2 and held therein. If the signals of the outputs 1c and 2a of 1 and 2 both become "1", the signal of 5a becomes "1". Then, the above operation is repeated, and the output of the shift register is inverted again and input to the flip-flop 1. In this way,
The waveform of FIG. 3 is repeated and operates as a ternary counter.

As described above, according to the present embodiment, the input data is counted using the shift register composed of the flip-flops 1 to 4, and the outputs of the flip-flops 1 to 4 are selected by the multiplexer 8 and set. In addition to performing the output of the radix data and using the inverted data output by the inversion circuit 9 as the input data of the shift register, the delay from the input to the output is reduced even if the number of flip-flop stages increases. This is the same as the delay amount in the operation of the shift register, and the delay operation is smaller and more stable than in the related art. If the count is a multiple of two, the output waveform has a duty of 50%, and even if the count is not a multiple of two, an output waveform close to the duty of 50% can be obtained.

Since the output of the multiplexer 8 is inverted by the inverter 9 and used as input data of the flip-flop 1 constituting the shift register, the input signal 1a
In data in the shift register is shifted by one stage, each logic element
The counting can be reliably performed without particularly considering the delay amount of the device, and the reliability of the device is high.

Further, since the AND of the outputs of the flip-flops 1 to 4 is obtained by using the two inputs AND5 to AND7, it is possible to operate as an odd-numbered counter.

[0016]

As described above, according to the semiconductor integrated circuit of the present invention, since the counting section is constituted by the shift register, the delay time from the input to the output becomes the delay by the shift register, and the data output of the multiplexer is performed. Is used as the input data of the counting section, and the data of the shift register is advanced by one stage by the change of the input clock, so that an output waveform with a duty of nearly 50% can be obtained , and the delay of each logic element can be obtained. The operation can be reliably performed without considering the amount, and a highly reliable semiconductor integrated circuit can be obtained.

Further , there is provided a logic circuit unit for calculating a logical product of outputs of the flip-flops constituting the shift register,
It is so arranged receiving outputs and the counting unit of the upper Symbol logic circuit portion at the multiplexer, the size and simple construction
In addition to being able to count up to a small numerical value, there is an effect that it can be operated as a counter of an odd number base.

[Brief description of the drawings]

FIG. 1 shows a semiconductor integrated circuit (2) according to an embodiment of the present invention.
FIG. 2 is a configuration diagram illustrating a octal counter.

FIG. 2 is a configuration diagram showing a conventional semiconductor integrated circuit (2- to octal counter).

FIG. 3 is a diagram showing a semiconductor integrated circuit (3) according to an embodiment of the present invention;
FIG. 6 is a timing chart showing the operation of a binary counter.

FIG. 4 is a timing chart showing an operation of a conventional semiconductor integrated circuit (ternary counter).

[Explanation of symbols]

1 to 4 D flip-flops constituting a shift register 5 to 7 AND circuit 8 Multiplexer 9 Inverting circuit 10 to 13 D flip-flop 14 Logic circuit 15, 16 RS flip-flop 17 OR circuit

Claims (1)

(57) [Claims] An input clock counts input data.
A counting unit to perform, and the output of the counting unit is received, and the value is set.
A signal output part that outputs data when
A semiconductor integrated circuit capable of setting the radix of the signal output unit to an arbitrary value, wherein each of a counting unit constituted by a shift register and a flip-flop constituting the shift register is provided.
A logic circuit for calculating a logical product of forces, and an output of the logic circuit and a serial output of the counting unit.
A signal output unit comprising a multiplexer for outputting data for each arbitrarily set number, and an inversion circuit unit for inverting the data output of the multiplexer, wherein the signal output unit inverted by the inversion circuit unit Wherein the data output is input as input data of the counting section.