JP2976745B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an efficient use of a redundant circuit in a multi-bit memory LSI.

[0002]

2. Description of the Related Art In recent years, dynamic RAM (hereinafter referred to as DRA)
(Abbreviated as M) has been on the path of increasing capacity at a rate of four times in three years. Due to this increase in capacity, the area of the chip has been increased by 1.5 times between generations (for example, 1 Mbit to 4 Mbit) of the DRAM. This increase in chip area is a negative factor for improving the yield at the DRAM production site. As a means for improving the yield of the DRAM, a technique of using a redundant circuit has been generally used. However, the use of the redundant circuit leads to an increase in chip size.
Since the number of chips per wafer is reduced, a large number of redundant circuits cannot be mounted on the chips. Therefore, in recent years, a method of using a redundant circuit as efficiently as possible has been studied in recent years (references, Kikukawa et al., "Highly Flexible Redundancy Scheme for Next-Generation Large-capacity DRAM", Proc. P152).

An example of a conventional redundant circuit of a multi-bit memory will be described below with reference to the drawings.

FIG. 8 is a schematic diagram of a conventional multi-bit memory using a redundant circuit. This conventional example is 4
This is a bit configuration memory. 8, 1 is a memory cell array of I / O0, 2 is a memory cell array of I / O1, and 3 is an I / O1 memory cell array.
O2 memory cell array, 4 is an I / O3 memory cell array. 5 is a redundant cell array of I / O0, 6 is a redundant cell array of I / O1, 7 is a redundant cell array of I / O2, and 8 is a redundant cell array of I / O3. 11 is a column predecoder, 12 is a column address bus, 13 is a column predecode signal bus, 14 to 17 are column decoders, 18 to 21 are column decode signals, 22 to 29
Is a redundant fuse circuit for column address, 30 to 37 are redundant signal lines, 38 is an intermediate amplifier of I / O0, 39 is an intermediate amplifier of I / O1,
40 is an intermediate amplifier for I / O2, 41 is an intermediate amplifier for I / O3, 42 to 45
Is a data line pair from the memory cell array to the intermediate amplifier in each I / O, and 46 to 49 are data line pairs from the intermediate amplifier to the output circuit (not shown) in each I / O. 50-89
Is a column switch, and 91 to 98 are column switches of the redundant cell array. 191 to 194 are redundant column decoders, 195-1
98 is a redundant column decode signal.

FIG. 9 shows the memory cell arrays 1-4 shown in FIG.
10 is a specific circuit diagram of the redundant fuse circuits 22 to 29 in FIG. 9, 101 to 105 are word lines, 106 is a memory cell, 107 to 111
Is a sense amplifier, 112 is a data line pair from the memory cell array to the intermediate amplifier, 113 to 122 are NMOS transistors, 12
3 to 132 are bit lines, 133 to 137 are column decode signal lines,
138 to 142 are column switches. In FIG. 10, 15
0 is the redundant fuse precharge signal input terminal, 151 is the first
, 152 and 153 are PMOS transistors, 154 is an inverter, 155 is a redundancy detection signal output terminal, 156 to 161 are address input terminals, 162 to 167 are NMOS transistors, 168 to 173 are fuse elements, and 174 is an internal node. .

The operation of the conventional multi-bit memory configured as described above will be described below. In FIG. 8, first, the memory cell arrays 1 to 4 are activated, and data is read from the memory cells and amplified. The amplified data is read out to the data line pairs 42 to 45 via the column switches 50 to 89 in each I / O, further amplified by the intermediate amplifiers 38 to 41, and then passed through the data line pairs 46 to 49. It is transferred to the output circuit. Here, column switches 50 to 89 are
At O, one of them is selected by a column decode signal 18-21 driven by a column decoder 14-17. As shown in FIG. 9, bit lines are respectively connected to the column switches, and data of the bit line of the selected column address is read out to the data line pair. As shown in FIG. 8, selection by a column address is performed by predecoding a column address input via a column address bus 12 by a predecode circuit 11 and outputting an output signal via a column predecode signal bus 13 to a column decoder 14. This is done by transmitting to ~ 17.

On the other hand, if the input address is an address for which redundancy relief is being performed, one of the redundant fuses 22 to 29 determines that the address is a redundant address, and a redundant signal line 30 is provided.
The redundant address detection signal is output to any one of the signal lines of. Now, suppose that a redundant address detection signal is output to the redundant signal line 30. Since this is a redundant address detection signal for I / O0, the redundant column decoder 191 of I / O0 operates to generate the redundant column decode signal 195. Then, the data is read from the redundant cell array 5 to the data line pair 42 by opening the redundant column switch 91 or 92. When the redundant address detection signal is output to the redundant signal line 30, the operation of the column decoder 14 is stopped to stop reading data from the memory cell array 1 and prevent data from colliding on the data line pair 42 to prevent malfunction. . At this time, the other I / Os 1 to 3 are operating normally. The above operation is shown in the timing chart of FIG. The redundant fuses 22 to 29 are circuits for judging a redundant address as shown in FIG. 10, and the address input terminals 156 to 161 are configured such that odd and even numbers are paired to input complementary addresses. Has become. When the input address matches the address programmed in the fuse elements 168 to 173 (in a state where the fuse is blown and the electric charge of the node 174 is not drawn to the ground), the output of this circuit outputs “high level”, This becomes a redundant address detection signal indicating that this is a redundant address.

Usually, in a multi-bit memory, a column address is degenerated by an amount corresponding to an increase in bit width. Since the conventional example has a 4-bit configuration, lower two bits of a column address are degenerated compared to a 1-bit chip. Have been. Blocks divided by degenerated lower 2 bits are I / O
The memory cell arrays are separated for each I / O as shown in FIG. In a memory having such a configuration, a signal (for example, an address) for distinguishing each I / O is not given from outside the chip.
A redundant cell array must be provided for each I / O.
In order to increase the redundancy rescue efficiency, it is desirable to perform redundancy rescue independently for each I / O with respect to the redundant fuse. However, since the redundant fuse circuit has only the function of determining the redundancy address, As shown in FIG. 8, a redundant fuse circuit must be provided for each I / O.

Therefore, in the conventional multi-bit memory as shown in FIG. 8, it is necessary to provide a redundant circuit for each I / O. Therefore, as the number of I / Os increases, the area occupied by the redundant circuits increases, and The size increases.
Since a redundant circuit, particularly a redundant fuse circuit, requires a large area, increasing the number of redundant circuits is a very serious problem. Increasing the chip area causes a problem that the number of chips per wafer decreases, resulting in a decrease in the yield, and the effect is lost even if a redundant circuit is provided.

[0010]

In the above configuration, since the redundant fuse circuit has only a function of determining a redundant address, the number of redundant fuse circuits and redundant memory cells in a multi-bit memory is reduced. However, there is a problem that the area occupied by the redundant circuit becomes large and the chip size becomes large because a large amount of the circuit is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a semiconductor integrated circuit which increases the relieving efficiency without increasing the number of redundant circuits in a memory having a multi-bit configuration.

[0012]

The semiconductor integrated circuit of the present invention to solve the above problems SUMMARY OF THE INVENTION additionally outputs a circuit for determining a redundancy repair address, the information stored in advance at the time of determination of the redundant address And a redundant fuse circuit including an information storage circuit.

[0013]

According to the present invention, unlike the conventional multi-bit chip, the present invention eliminates the necessity of having a redundant circuit for each block whose address is degenerated, and can use the redundant circuit very efficiently. A large number of redundant fuse circuits and redundant memory cells are not required, and the chip size can be reduced without increasing the area occupied by the redundant circuit. Therefore, the yield can be improved because the redundant circuit is used efficiently and the chip size is reduced.

[0014]

【Example】

(Embodiment 1) A redundant fuse circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a redundant fuse circuit according to the first embodiment of the present invention.

In FIG. 1, reference numeral 200 denotes a first power source;
Is the address input terminal, 207-212, 229, 230, 240, 241 are
NMOS transistors, 213 to 218, 231, 232 are fuse elements, 219 to 224, 242, 243 are PMOS transistors, 225 to 22
8, 239 are inverters, 233 is a redundant fuse precharge signal input terminal, 234 is a redundant detection signal output terminal, 235 is an additional information storage unit that outputs specific information stored in response to the output of the redundant detection signal 234, 236 and 237 are additional information storage units
235 is an output terminal, and 238 is an internal node.

The redundant fuse circuit of this embodiment has a configuration in which an additional information storage unit 235 is added to the conventional fuse circuit shown in FIG. In this embodiment, the address input from the address input terminals 201 to 206 is
If the address matches the address programmed to ~ 218 (the fuse is blown and the charge at node 244 is not pulled to ground), the output 234 of this circuit outputs "high level", and the address to which this is input is redundant. This is a redundant address detection signal indicating that the address is an address. Up to this point, there is no difference from the conventional redundant fuse circuit, but since the additional information storage unit 235 has a function of receiving the output of the redundant detection signal 234 and outputting the stored specific information, the redundant fuse circuit is simply Some operation can be performed using the result of the judgment without operating only for the redundant address judgment. For example, when this is applied to a memory of a 4-bit configuration as described in the conventional example, the lower 2 bits of the column address (address for discriminating I / O 0 to 3) compressed in the additional information storage unit are used. (But not input from anywhere)), it is possible to generate a lower 2 bit column address with the input upper address,
O0-3 can be distinguished.

In this embodiment, the degenerated column address is stored in the additional information storage unit. However, various information such as an operation mode setting signal and a signal for changing the operation timing is stored. be able to.

The output of the additional information storage section is output only when the redundancy detection signal is being output, and becomes a high impedance at other times. However, the circuit type is not limited to this form. Alternatively, a circuit whose output does not become high impedance may be used. In this embodiment, the configuration of the additional information storage unit is also a fuse element.
For example, any storage element such as an SRAM may be used.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic diagram of a 4-bit memory according to a second embodiment of the present invention. In FIG. 2, 251 is an I / O
0 memory cell array, 252 I / O1 memory cell array,
253 is an I / O2 memory cell array, and 254 is an I / O3 memory cell array. Reference numeral 255 denotes a redundant cell array common to I / O0 to I / O3. 282 is a column predecoder, 281 is a column address bus, 283 is a column predecode signal bus, 256 to 259
Is a column decoder, 260 to 263 are column decode signals, 27
6 to 279 are column address redundant fuse circuits using the redundant fuse circuit having the additional information storage unit described in the first embodiment; 284 to 287 are redundant signal lines; 268 is an intermediate amplifier of I / O0;
69 is the I / O1 intermediate amplifier, 270 is the I / O2 intermediate amplifier, and 271 is
I / O3 intermediate amplifier, 264-267 are data line pairs from the memory cell array to the intermediate amplifier in each I / O, 272-275 are data line pairs from the intermediate amplifier to the output circuit (not shown) in each I / O It is. 300 to 339 are column switches, 295
Is a data line pair from the redundant cell array to the intermediate amplifiers 268 to 271, and 296 to 299 are column switches of the redundant cell array. Outputs 289 and 290 of the additional information section of the redundant fuse circuits 276 to 279 (degenerated addresses for decoding I / O0 to I / O3), and 280 decodes the outputs 289 and 290 of the additional information section to obtain I / O I / O determination circuit for determining O0 to I / O3, 291 to 294
An output signal of the / O determination circuit 280 (indicating which I / O of I / O0 to I / O3 performs redundancy relief), 340 is a redundant column decoder,
41 is a redundant column decode signal.

In the embodiment constructed as described above,
The operation of the 4-bit memory will be described below. Since the inside of the memory cell arrays 251 to 254 in FIG. 2 is the same as that in FIG. 9 in the conventional example, the description in the memory cell array is omitted. In FIG. 2, first, the memory cell array 25
1 to 254 are activated, data is read from the memory cell and amplified. The amplified data is read out to the data line pairs 264 to 267 via the column switches 300 to 339 at each I / O, further amplified by the intermediate amplifiers 268 to 271 and then passed through the data line pairs 272 to 275. It is transferred to the output circuit.
Here, column switches 300 to 339 are column decode signals driven by column decoders 256 to 259 in each I / O.
One of them is selected by 260-263. As shown in FIG. 9, bit lines are respectively connected to the column switches, and data of the bit line of the selected column address is read out to the data line pair. As shown in FIG. 2, selection by a column address is performed by predecoding a column address input via a column address bus 281 by a predecode circuit 282, and outputting an output signal of the column decoder 256 via a column predecode signal bus 283. This is done by transmitting to ~ 259.

On the other hand, if the input address is an address performing redundancy relief, the redundancy fuse circuits 276 to 279 are provided.
And outputs a redundant signal to one of the redundant signal lines 284 to 287. Now, suppose that the redundancy repair address programmed in the redundancy fuse circuit 276 is input and the redundancy signal line
A redundant address detection signal is output to 284.
Furthermore, assuming that an address for decoding I / O0 (degenerated address for this memory chip) is stored in the additional information storage unit of the redundant fuse circuit 276, the redundant address is stored in the redundant signal line 284. When the detection signal is output, I / O0 is output to outputs 289 and 290 of the additional information storage unit.
Is output. Next, the outputs 289 and 290 of the additional information storage unit determine I / O0 to I / O3.
An output signal 291 of the I / O determination circuit 280 is decoded by the I / O determination circuit 280 and indicates that I / O0 is an I / O for performing redundancy repair. The redundant address detection signal output to the redundant signal line 284 is input to the redundant column decoder 340, and outputs the redundant column decode signal 341. The redundant column decode signal 341 selects one of the redundant column switches 296 to 299, and data is read out to the redundant data line pair 295 from the redundant memory cell array activated at the same time as the normal memory cell array, and The data is transferred to the input units of the amplifiers 268 to 271. In the memory chip of the present embodiment, the data of the memory cell array is always read out to the intermediate amplifiers 268 to 271 at the time of normal and redundant repairs. The data is amplified and output by the intermediate amplifier, and the intermediate amplifiers of the remaining I / O perform normal operations. That is, in this embodiment, only I / O0 is redundantly repaired. The above operation is shown in the timing chart of FIG.

Table 1 shows a program example of the additional information storage section of the redundant fuse circuits 276 to 279 in this embodiment.
As is clear from Table 1, the output of the additional information storage unit is 2 bits in this example, so that it is possible to represent four states, thereby distinguishing I / O0 to I / O3. .

[0024]

[Table 1]

FIG. 4 is a specific circuit diagram of the I / O determination circuit 280 in FIG. 4, 351 to 357 are inverter circuits, 358 is a 4-input NOR circuit, 359 to 362 are 3-input NAND circuits, 36
3 is an I / O connection of the redundant signal line 284 of the redundant fuse circuit 276 in FIG.
A terminal for inputting to the determination circuit, 364 is a terminal for inputting the redundant signal line 285 of the redundant fuse circuit 277 in FIG. 2 to the I / O determination circuit, and 365 is a redundant signal line 28 for the redundant fuse circuit 278 in FIG.
6, 366 is a terminal for inputting the redundant signal line 287 of the redundant fuse circuit 279 in FIG. 2 to the I / O determination circuit, and 367 is a redundant fuse circuit 276 to 279 in FIG. Terminal for inputting the output 289 of the additional information storage unit of the I / O determination circuit,
Reference numeral 368 denotes a terminal for inputting the output 290 of the additional information storage unit of the redundant fuse circuits 276 to 279 in FIG. 2 to the I / O determination circuit, and reference numeral 369 denotes an output signal 291 (I / I / I) of the I / O determination circuit 280 in FIG. O0 indicates that redundancy relief is to be performed), 370 is an output terminal of the output signal 292 (indicating that I / O1 performs redundancy relief) of the I / O determination circuit 280 in FIG. 2 is an output terminal of the output signal 293 (indicating that I / O2 performs redundancy relief) of the I / O determination circuit 280, and 372 is an output signal 294 of the I / O determination circuit 280 in FIG.
(Indicating that I / O3 performs redundancy relief).

The operation of the circuit shown in FIG. 4 is as follows. That is, when a redundant address detection signal is input to any of the redundant signal lines input to the input terminals 363 to 366, this I / O
The decision circuit becomes active, otherwise it does not work. When this circuit is active, it operates as described with reference to FIG. 2 and outputs an output as shown in (Table 1). The reason why the present circuit is controlled by the redundant address detection signal is that the output of the present circuit controls switching between redundancy and non-redundancy by an intermediate amplifier described below. That is, if this circuit is always operating, the data of the redundant data line pair will always be amplified and output by any I / O.

FIG. 5 shows a specific circuit diagram of the intermediate amplifiers 268 to 271 shown in FIG. In FIG. 5, 381 and 382 indicate inverters, 383, 384, 389 and 390 indicate NMOS transistors, and 385 to 3
88 is a PMOS transistor, 391 is a data amplifying unit, 392 is an input terminal of a normal data line pair, 393 is an input terminal of a redundant data line pair, 394 is an output terminal of an intermediate amplifier, and 395 is an I / O in FIG.
Input terminal of the output signal of the O determination circuit 280.

The operation of the circuit shown in FIG. 5 is roughly described in FIG.
The signal is controlled by the output signal of the middle I / O determination circuit 280, and when this signal does not come (when there is no need for redundancy relief for the I / O to which this intermediate amplifier belongs), the normal data line pair 392 is used. Amplify and output the data. Conversely, when the output signal of the I / O determination circuit 280 comes, the data of the redundant data line pair is amplified and output.

As shown in this embodiment, when a multi-bit memory chip is formed using the redundant fuse circuit having the portion for storing the additional information shown in the first embodiment, a very efficient redundant circuit can be formed. That is, in the configuration using the conventional redundant fuse circuit, it is impossible to distinguish between the respective I / Os (because the address is degenerated), so the redundant fuse circuit and the redundant memory cell array are shared between the respective I / Os. And couldn't use it. Therefore, each I / O had to have a redundant fuse circuit and a redundant memory cell array necessary for itself. However, by using a redundant fuse circuit having a portion for storing additional information, an address input as the additional information can store I / O determination information to be redundantly rescued. Therefore, the redundant fuse circuit and the redundant memory cell array can be shared between the I / Os, and a very efficient redundant circuit can be configured. Table 2 shows this effect in a table.

[0030]

[Table 2]

Table 2 shows how many defects can be remedied for each I / O with respect to the total number of redundant fuse chips between the conventional example and the present invention. For example, comparing the conventional 16-bit configuration with 16 redundant fuses to the same one of the present invention,
While only one defect can be remedied for each I / O, the present invention can rescue a maximum of 16 defects with one I / O. However, if you look at the whole chip, the number of fuses is
Since there are only 16, only 16 can be rescued in total. This means that the present invention is a highly efficient redundant circuit as compared with the conventional redundant circuit, and the circuit according to the present embodiment is more effective as the number of bits increases. It is clear from 2).

In this embodiment, a multi-bit memory is described as an example of a memory for compressing an address. However, the present invention degenerates another address such as a memory having a serial-parallel conversion circuit and a parallel-serial conversion circuit. The present invention can be similarly applied to a memory to be used.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 is a schematic diagram of a 4-bit memory according to a third embodiment of the present invention. In FIG. 6, 401 is I / O0
The memory cell array of 402, 402 is the memory cell array of I / O1, 4
03 is an I / O2 memory cell array, and 404 is an I / O3 memory cell array. 405 is a redundant cell array common to I / O0 to I / O3
Reference numerals 1 and 406 denote redundant cell arrays 2 common to I / O0 to I / O3. 439
Is a column predecoder, 438 is a column address bus, 440
Is a column predecode signal bus, 407 to 410 are column decoders, 411 to 414 are column decode signals, and 428 to 435 are column address redundant fuse circuits using the redundant fuse circuit having the additional information storage unit described in the first embodiment. , 441-448
Is a redundant signal line, 419 is an intermediate amplifier for I / O0, 420 is an intermediate amplifier for I / O1, 421 is an intermediate amplifier for I / O2, 422 is an intermediate amplifier for I / O3, and 415 to 418 are for each I / O. Data line pairs from the memory cell array to the intermediate amplifier, and 423 to 426 are data line pairs from the intermediate amplifier to the output circuit (not shown) in each I / O. 471 to 510 are column switches, 461 is a data line pair from the redundant cell array 1 to the intermediate amplifiers 419 to 422, 462 is a data line pair from the redundant cell array 2 to the intermediate amplifiers 419 to 422, and 463 to 470 are column switches for the redundant cell array. It is. Reference numerals 457 and 458 denote outputs of the additional information part of the redundant fuse circuits 428 to 431 (degenerated addresses for decoding I / O0 to I / O3), and reference numerals 459 and 460 denote outputs of the additional information parts of the redundant fuse circuits 432 to 435. (Degenerate address for decoding I / O0 to I / O3), 436 is a first I / O determination for decoding outputs 457 and 458 of the additional information section and determining I / O0 to I / O3 Circuit, 43
7 decodes the outputs 459 and 460 of the additional information section to execute I / O0 to I / O
The second I / O determination circuit that performs the determination of 3, 449 to 452 are the first I / O
An output signal of the O determination circuit 436 (indicating which I / O of I / O0 to I / O3 performs redundancy repair), and 453 to 456 are second I / O determination circuits
437 output signal, 511 is a column decoder of the first redundant cell array, 512 is a column decoder of the second redundant cell array,
513 is a column decode signal of the first redundant cell array, 514
Is a column decode signal of the second redundant cell array.

In the present embodiment configured as described above,
The following describes the 4-bit memory.
This embodiment has a configuration in which an independent redundant memory array is added to the memory in the second embodiment. The memory according to the second embodiment has only one pair of data lines from the redundant array, and two or more I / O
If there was a defect, relief was impossible. Therefore, in this embodiment, a memory that can perform redundancy repair even when two I / Os have a defect at the same time is shown. That is, as described above, all redundant circuits have two systems (redundant memory cell array, redundant fuse circuit, redundant data line pair, redundant memory cell array column decoder, I / O determination circuit, etc.). Program to generate a redundant address detection signal for the same address,
In addition, by storing a degenerated address designating another I / O in each additional information storage unit, it is possible to perform redundancy repair for a defect in another I / O at the same address. In this configuration, the only difference between the memory and the circuit configuration in the second embodiment is the intermediate amplifier.

FIG. 7 shows a specific circuit diagram of the intermediate amplifiers 419 to 422 shown in FIG. 7, 550 to 554 are inverters, 555 is a two-input NOR circuit, 558 to 563 are NMOS transistors, 564 to 569 are PMOS transistors, 570 is a data amplifier, 572 is an input terminal of a normal data line pair, and 573 is a 1 redundant memory cell array data line pair input terminal, 574 second
571, the input terminal of the data line pair of the redundant memory cell array
Is an output terminal of the intermediate amplifier, 556 is an input terminal of an output signal of the first I / O determination circuit 436 in FIG. 6, and 557 is a second I / O in FIG.
Input terminal of the output signal of the determination circuit 437.

The operation of the circuit shown in FIG. 7 is roughly the same as that described with reference to FIG. 5, but the operation of the circuit is different from the first I / O shown in FIG. It is controlled by two control signals, the output signal of the determination circuit 436 and the output signal of the second I / O determination circuit 437, and when this signal does not come (the I / O to which this intermediate amplifier belongs is When it is not necessary), the data of the normal data line pair 572 is amplified and output. Conversely, when an output signal from either of the two I / O determination circuits comes, the data amplification unit 570 supplies the data line pair 573 from the first redundant memory cell or the data line pair 573 from the second redundant memory cell. It amplifies and outputs the data of 574.

With the above-described configuration, redundancy can be repaired even when two I / Os have a defect at the same time. However, when three or four I / Os have the same address defect at the same time, For the rescue, an independent redundant circuit may be added in the same manner as described in this embodiment.

Although the present embodiment has been described with reference to a memory having a 4-bit configuration, the same effect can be obtained by adopting a similar configuration in a configuration having a larger number of bits.

[0040]

The semiconductor integrated circuit according to the present invention has not only a circuit for determining a redundant address but also a portion for storing additional information. For example, by storing the degenerated address in the additional information storage unit, the degenerated address is input when the redundant address is input.
Carried out of the occur.

According to the present invention, unlike the conventional multi-bit chip, the present invention eliminates the necessity of having a redundant circuit for each block in which the address is degenerated, and can use the redundant circuit very efficiently. A large number of fuse circuits, redundant memory cells, and the like are not required, and the area occupied by the redundant circuit does not increase, and the chip size can be reduced. Therefore, the efficient use of the redundant circuit and the reduction in chip size can improve the yield and reduce the cost. Therefore, DRAM design including design for reducing the chip size, efficiency of the redundant circuit, and design of a circuit for decoding the address associated therewith can be easily performed, thereby shortening the DRAM development period. It can also contribute to reducing development costs.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a redundant fuse circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a 4-bit memory according to a second embodiment of the present invention;

FIG. 3 is an operation waveform diagram of a memory having a 4-bit configuration according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram of a degenerate address decode circuit of a 4-bit memory according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram of an intermediate amplifier circuit of a 4-bit memory according to a second embodiment of the present invention;

FIG. 6 is a schematic diagram of a 4-bit memory according to a third embodiment of the present invention;

FIG. 7 is a circuit diagram of an intermediate amplifier circuit of a 4-bit memory according to a third embodiment of the present invention;

FIG. 8 is a schematic diagram of a 4-bit memory in a conventional example.

FIG. 9 is a schematic diagram in a memory cell array.

FIG. 10 is a circuit diagram of a redundant fuse circuit in a conventional example.

FIG. 11 is an operation waveform diagram of a memory having a 4-bit configuration in a conventional example.

[Explanation of symbols]

 235 Additional information storage unit 276-279 Redundant fuse circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirohito Kikukawa 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Hisaka Kotani 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-210699 (JP, A) JP-A-5-74189 (JP, A JP-A-6-111596 (JP, A) JP-A-3-80500 (JP, A) JP-A-4-64999 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 29/00

Claims (2)

(57) [Claims] 1. A circuit for determining a redundancy repair address, and an additional information storage circuit for generating a compressed address stored in advance when determining the redundancy address, wherein the circuit for determining the redundancy repair address is an input. A redundant address detection signal is generated from the generated redundancy repair address, and the additional information storage circuit includes a redundant fuse circuit having a function of generating the degenerated address from the redundant address detection signal; and a plurality of address degeneration units. A semiconductor integrated circuit , wherein a redundant fuse circuit is shared between the address compression units. 2. The semiconductor integrated circuit according to claim 1 , wherein
Semiconductors characterized by sharing redundant memory cells
Integrated circuit .