JP2975459B2 - Multilayer ceramic chip capacitors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic chip capacitor.

[0002]

2. Description of the Related Art Multilayer ceramic chip capacitors are:
It is widely used as a small, large-capacity, high-reliability electronic component, and the number used in one electronic device is large. In recent years, with the miniaturization and high performance of devices, demands for further miniaturization, large capacity, low price, and high reliability of multilayer ceramic chip capacitors have become more and more severe.

A multilayer ceramic chip capacitor is usually manufactured by laminating a paste for an internal electrode layer and a paste for a dielectric layer by a sheet method, a printing method, or the like, and simultaneously firing them.

The conductive material of the internal electrode layer is generally Pd or Pd.
Although d alloys are used, Pd is expensive, and relatively inexpensive base metals such as Ni and Ni alloys are being used. When a base metal is used as the conductive material of the internal electrode layer, if the firing is performed in the air, the internal electrode layer is oxidized. Therefore, the simultaneous firing of the dielectric layer and the internal electrode layer must be performed in a reducing atmosphere. is there. However, when firing in a reducing atmosphere, the dielectric layer is reduced and the specific resistance is reduced, and thus non-reducing dielectric materials have been proposed.

However, a multilayer ceramic chip capacitor using a non-reducing dielectric material has a problem that the life of the insulation resistance IR is short and the reliability is low.

Further, when exposing the dielectric to a DC electric field, the dielectric constant epsilon _s is caused a problem that decreases over time. When the thickness of the dielectric layer is reduced in order to increase the size and capacitance of the chip capacitor, the electric field applied to the dielectric layer when a DC voltage is applied increases, so that the relative dielectric constant ε _s changes with time,
That is, the change with time of the capacitance becomes extremely large.

By the way, X7R specified in the EIA standard
In a standard called characteristics, the rate of change of the capacitance is defined to be within ± 15% (reference temperature 25 ° C.) between −55 ° C. and 125 ° C. Further, in a standard called the B characteristic defined in the JIS standard, the rate of change in capacity is from -25 ° C to 85 ° C.
It is specified that the temperature is within ± 10% (reference temperature: 20 ° C.).

As a dielectric material satisfying the X7R characteristic and the B characteristic, for example, a composition of BaTiO ₃ + SrTiO ₃ + MnO system disclosed in Japanese Patent Application Laid-Open No. 61-36170 is known. However, according to this method, the capacitance changes with time under a DC electric field is large.
-30%, so that the X7R characteristic and the B characteristic cannot be satisfied.

Other non-reducing dielectric porcelain compositions include BaTiO ₃ + MnO + MgO disclosed in JP-A-57-71866 and JP-A-61-2.
No. 50905 (Ba _1-x Sr _{x
O) a Ti 1-y Zr} y O 2 + α ((1-z) MnO + z
(CoO) + β ((1-t) A ₂ O ₅ + tL ₂ O ₃ ) + w
SiO ₂ (where A = Nb, Ta, V, L = Y or a rare earth element), barium titanate disclosed in JP-A-2-83256, and BaαCa _1- α in a glassy state
One to which SiO ₃ is added is exemplified. However, any of these dielectric ceramic compositions can satisfy all of the characteristics that the temperature characteristics of the capacitance are good, the capacitance changes with time under a DC electric field are small, and the accelerated life of the insulation resistance is long. Did not. For example, those disclosed in JP-A-61-250905 and JP-A-2-83256, respectively, have a short insulation resistance accelerated life.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has a temperature characteristic X7 which is a capacitance.
It is an object of the present invention to provide a multilayer ceramic chip capacitor that can satisfy the R characteristics and the B characteristics, has a small change in capacitance with time under a DC electric field, and has a long accelerated life of an insulation resistance IR.

[0011]

This and other objects are achieved by the present invention which is defined below as (1) to (4).

(1) A multilayer ceramic chip capacitor having a capacitor chip body having a structure in which dielectric layers and internal electrode layers are alternately stacked, wherein the dielectric layer comprises:
Based on 100 mol of the barium titanate converted to BaTiO ₃ , the main component of which is barium titanate, 0.5 to 3 mol of magnesium oxide converted to MgO, and 0.1 to 0.5 mol converted to MnO. Manganese oxide and CoO
Contains 0.05 to 0.3 mol of cobalt oxide as a sub-component, and further, as a sub-component, a glassy (B
a _x Ca _1-x O) _y · SiO ₂ (however, 0.3 ≦ x ≦
0.7, 0.95 ≦ y ≦ 1.05. ) To the above B
aTiO _3, MgO, multilayer ceramic chip capacitors which comprises 3 to 7% by weight relative to the sum of MnO and CoO.

(2) The multilayer ceramic chip capacitor according to the above (1), wherein the conductive material contained in the internal electrode layer is Ni or a Ni alloy.

(3) The multilayer ceramic chip capacitor according to (2), which is fired in an atmosphere having an oxygen partial pressure of 10 ^-8 to 10 ^-12 atm in a temperature range of 1200 to 1380 ° C.

(4) The multilayer ceramic chip capacitor as described in (2) or (3) above, which has been annealed in an atmosphere having an oxygen partial pressure of 10 ^-6 atm or more within a temperature range of 1100 ° C. or less after firing. .

[0016]

[Specific Configuration] Hereinafter, a specific configuration of the present invention will be described in detail.

[Laminated Ceramic Chip Capacitor] FIG. 1 is a sectional view of a preferred embodiment of the laminated ceramic chip capacitor of the present invention.

As shown in FIG. 1, a multilayer ceramic chip capacitor 1 according to the present invention has a structure in which dielectric layers 2 and internal electrode layers 3 are alternately stacked.
0, and the outer surface of the capacitor chip body 10 has an external electrode 4 which is electrically connected to the internal electrode layer 3. The shape of the capacitor chip body 10 is not particularly limited, but is generally a rectangular parallelepiped. The size is not particularly limited and may be an appropriate size depending on the application.
6mm) × (0.5-5.0mm) × (0.5-1.9mm)
It is about. The internal electrode layer 3 is laminated so that the end faces thereof are alternately exposed on the two opposing surfaces of the capacitor chip body 10, and the external electrodes 4 are formed on the two opposing surfaces of the capacitor chip body 10, Configure the circuit.

<Dielectric Layer 2> The dielectric layer 2 contains barium titanate as a main component, and is converted to MgO with respect to 100 moles of the above barium titanate converted to BaTiO ₃ .
5 to 3 mol, preferably 1.0 to 1.5 mol of magnesium oxide, 0.1 to 0.5 mol, preferably 0.2 to 0.4 mol of manganese oxide and CoO in terms of MnO
0.05 to 0.3 mol, preferably 0.1 to
Containing 0.2 mol of cobalt oxide as a sub-component, further, as a secondary component, glassy _{(Ba x Ca 1-x O} ) y
・ SiO ₂ (however, 0.3 ≦ x ≦ 0.7, 0.95 ≦
y ≦ 1.05. ) Is replaced with BaTiO ₃ , Mg
It contains 3 to 7% by weight, preferably 4 to 6% by weight, based on the total of O, MnO and CoO. The oxidation state of each oxide is not particularly limited as long as the content of the metal element constituting each oxide is within the above range.

The reasons for limiting the contents of the above subcomponents are as follows.

If the content of magnesium oxide is less than the above range, the temperature characteristics of the capacity cannot be set in a desired range. When the content of magnesium oxide exceeds the above range, the sinterability rapidly deteriorates, the densification becomes insufficient, and
The R accelerated life is reduced, and a high relative dielectric constant cannot be obtained.

If the manganese oxide content is less than the above range, good reduction resistance cannot be obtained, the IR accelerated life becomes insufficient, and it becomes difficult to reduce the loss tan δ. If the manganese oxide content exceeds the above range, it is difficult to reduce the change over time of the capacity when a DC electric field is applied.

When the content of cobalt oxide is less than the above range, the life of the insulation resistance IR is insufficient, the reduction resistance is also insufficient, and the loss tan δ increases. When the content of cobalt oxide exceeds the above range, the change with time of the capacity when a DC electric field is applied becomes large.

Glassy (Ba _x Ca _1-x O) _y · Si
When the content of O ₂ is less than the above range, the change with time of the capacity when a DC electric field is applied becomes large, and the IR accelerated life becomes insufficient. Exceeding the above range causes a sharp drop in the relative dielectric constant. If the value of x in (Ba _x Ca _{1- x} O) _y · SiO ₂ is out of the above range, or the value of y is out of the above range, sinterability is reduced and densification becomes insufficient.

In the present invention, the dielectric layer has a so-called core-shell structure. That is, BaTiO ₃ +
Around the crystal grains (core) of the high dielectric constant phase composed of MnO + CoO + MgO or the like, CaTiO ₃ + (Ba _x C
a _1-x O) _y · SiO ₂ + MnO + CoO + MgO The structure is surrounded by crystal grain boundaries (shells) of a low dielectric constant phase composed of, for example, a.

Although the average crystal grain size of the dielectric layer is not particularly limited, fine grains can be obtained by the above composition, and the average crystal grain size is usually about 0.2 to 0.7 μm. The average width of the crystal grain boundary is 0.02 to 0.2 μm
It is about.

The Curie temperature of the dielectric layer can be appropriately set by selecting the composition according to the applicable standard, but is generally 85 ° C. or higher, usually 120 to 130.
About ℃.

The thickness of one dielectric layer is 100 μm.
m, particularly 50 μm or less, and more preferably about 5 to 30 μm. The present invention is effective in preventing the capacitance of a multilayer ceramic chip capacitor having such a thin dielectric layer from changing over time. The number of stacked dielectric layers is usually about 2 to 200.

<Internal Electrode Layer 3> The conductive material contained in the internal electrode layer 3 is not particularly limited, but a base metal can be used because the material constituting the dielectric layer 2 has reduction resistance.
As the base metal used as the conductive material, Ni or a Ni alloy is preferable. As the Ni alloy, an alloy of one or more elements selected from Mn, Cr, Co, and Al and Ni is preferable, and the Ni content in the alloy is preferably 95% by weight or more.

It should be noted that various trace components such as P may be contained in Ni or Ni alloy in an amount of about 0.1% by weight or less.

The thickness of the internal electrode layer may be appropriately determined according to the application and the like, but is usually 1 to 5 μm, particularly 2 to 3 μm.
It is preferred that it is about.

<External Electrode 4> The conductive material contained in the external electrode 4 is not particularly limited.
u or an alloy thereof can be used.

The thickness of the external electrode may be appropriately determined according to the application and the like, but is usually preferably about 10 to 50 μm.

[Production Method of Multilayer Ceramic Chip Capacitor] In the multilayer ceramic chip capacitor of the present invention, a green chip is prepared by a usual printing method or sheet method using a paste, and after firing, a green chip is formed. It is manufactured by printing or transferring and firing.

<Dielectric Layer Paste> The dielectric layer paste is manufactured by kneading a dielectric material and an organic vehicle.

As the dielectric material, a mixture of the above-mentioned composite oxide, oxide and glass can be used. In addition, various compounds which become the above-mentioned composite oxide and oxide by firing, such as carbonate, It can be appropriately selected from oxalates, nitrates, hydroxides, organometallic compounds, and the like, and used by mixing. The content of each compound in the dielectric material is
What is necessary is just to determine so that it may become the above-mentioned composition of a dielectric layer after baking.

The dielectric material usually has an average particle diameter of 0.1 to
It is used as a powder of about 1 μm.

The organic vehicle is obtained by dissolving a binder in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from various ordinary binders such as ethyl cellulose. In addition, the organic solvent to be used is not particularly limited, and may be appropriately selected from various organic solvents such as terpineol, butyl carbitol, acetone, and toluene according to a method to be used such as a printing method and a sheet method.

<Paste for Internal Electrode Layer> The paste for the internal electrode layer is made of a conductive material made of the above-mentioned various conductive metals or alloys, or various oxides, organometallic compounds, resinates, etc. which become the above-mentioned conductive material after firing. And the above-mentioned organic vehicle.

<Paste for External Electrode> The paste for the external electrode may be prepared in the same manner as the paste for the internal electrode layer described above.

<Organic Vehicle Content> The content of the organic vehicle in each of the above-mentioned pastes is not particularly limited, and ordinary contents, for example, about 1 to 5% by weight of a binder and about 10 to 50% by weight of a solvent. And it is sufficient. Further, each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, and the like, as necessary.
The total content of these is preferably 10% by weight or less.

<Preparation of Green Chip> When the printing method is used, the paste for the dielectric layer and the paste for the internal electrode layer are laminated and printed on a substrate such as PET, and cut into a predetermined shape. Chips.

When the sheet method is used, a green sheet is formed by using a dielectric layer paste, an internal electrode layer paste is printed thereon, and these are laminated to form a green chip.

<Binder Removal> The binder removal performed before firing may be performed under ordinary conditions. When a base metal such as Ni or Ni is used as the conductive material of the internal electrode layer, the binder removal is particularly performed under the following conditions. Is preferred. Heating rate: 10 to 300 ° C / hour, especially 50 to 100 ° C
/ Hour Holding temperature: 600 to 1200 ° C., especially 700 to 900 ° C. Temperature holding time: 0.5 to 5 hours, especially 1 to 3 hours Oxygen partial pressure: 10 ^-4 to 10 ^-8 atm, especially 10 ^-5 to 10 It is preferable to use a humidified N ₂ gas or the like as an atmospheric gas at the time of the ^-6 atm binder removal treatment.

<Firing> The atmosphere for firing the green chip may be appropriately determined according to the type of the conductive material in the internal electrode layer paste. When a base metal such as Ni or a Ni alloy is used as the conductive material, The oxygen partial pressure in the firing atmosphere is 1
The pressure is preferably from 0 ^-8 to 10 ^-12 atm. If the oxygen partial pressure is less than the above range, the conductive material of the internal electrode layer may abnormally sinter and be interrupted. If the oxygen partial pressure exceeds the above range, the internal electrode layer tends to be oxidized.

The holding temperature during firing is 1200 to 1
It is preferably 380 ° C, particularly preferably 1260-1340 ° C. If the holding temperature is lower than the above range, the densification is insufficient, and if the holding temperature is higher than the above range, the change with time of the capacity when a DC electric field is applied becomes large.

Various conditions other than the above conditions are preferably as follows. Heating rate: 50 to 500 ° C / hour, especially 200 to 300
° C / hour Temperature holding time: 0.5-8 hours, especially 1-3 hours Cooling rate: 50-500 ° C / hour, especially 200-300
C / hour The firing atmosphere is preferably a reducing atmosphere. As the atmosphere gas, for example, a mixed gas of N ₂ and H ₂ is preferably used after being humidified.

<Annealing> When firing in a reducing atmosphere, the capacitor chip is preferably annealed. Annealing is a process for reoxidizing the dielectric layer, which can significantly increase the IR accelerated life.

The oxygen partial pressure in the annealing atmosphere is preferably 10 ⁻⁶ atm or more, particularly preferably 10 ⁻⁵ to 10 ⁻⁴ atm. When the oxygen partial pressure is less than the above range, it is difficult to reoxidize the dielectric layer, and when the oxygen partial pressure exceeds the above range, the internal electrode layer tends to be oxidized.

The holding temperature at the time of annealing is preferably 1100 ° C. or less, particularly preferably 500 to 1000 ° C. If the holding temperature is less than the above range, the oxidation of the dielectric layer tends to be insufficient and the life tends to be short, and if the holding temperature exceeds the above range, the internal electrode layer is oxidized and the capacity is reduced, It tends to react with the substrate and shorten its life. Note that the annealing may be configured only by raising and lowering the temperature. In this case, the temperature holding time is zero, and the holding temperature is synonymous with the maximum temperature.

Various conditions other than the above conditions are preferably as follows. Temperature holding time: 0 to 20 hours, especially 6 to 10 hours Cooling rate: 50 to 500 ° C / hour, especially 100 to 300
C / hour It is preferable to use a humidified N ₂ gas or the like as the atmosphere gas.

In the above-mentioned binder removal processing, firing and annealing, for example, a wetter or the like may be used to humidify the N ₂ gas or the mixed gas. In this case, the water temperature is preferably about 5 to 75 ° C.

The binder removal treatment, firing and annealing are performed as follows.
It may be performed continuously or independently.

In the case where these steps are continuously performed, after removing the binder, the atmosphere is changed without cooling, and then the temperature is raised to the holding temperature at the time of firing, firing is performed, and then cooling is performed. It is preferable to perform annealing by changing the atmosphere when the temperature reaches the threshold value.

[0055] Also, when performing these independently, at the time of firing, after raising the temperature under N ₂ gas atmosphere with N ₂ gas or wet to the holding temperature of the binder removal processing, the temperature is further raised to change the atmosphere After cooling to the holding temperature at the time of annealing, it is preferable to change the atmosphere to N ₂ gas or a humidified N ₂ gas atmosphere again and continue cooling. Further, at the time of annealing, the temperature may be raised to a holding temperature in an N ₂ gas atmosphere, and then the atmosphere may be changed, or the entire annealing process may be performed in a humidified N ₂ gas atmosphere.

<Formation of External Electrodes> The capacitor chip body obtained as described above is subjected to edge polishing by, for example, barrel polishing or sand blasting, and the external electrode paste is printed or transferred and baked. Form.
The firing conditions for the external electrode paste are, for example, 600 to 8
It is preferable to set the temperature at 00 ° C. for about 10 minutes to 1 hour.

Then, if necessary, on the surface of the external electrode 4,
A coating layer is formed by plating or the like.

The multilayer ceramic chip capacitor of the present invention thus manufactured is mounted on a printed circuit board or the like by soldering or the like, and is used for various electronic devices and the like.

The dielectric layer of the multilayer ceramic chip capacitor of the present invention has a thickness of 0.02 V / μm when used.
A DC electric field of 0.2 V / μm or more, especially 0.5 V / μm or more, generally about 5 V / μm or less, and an AC component superimposed on the electric field are applied. , The change with time of the capacity is extremely small.

[0060]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to specific examples of the present invention.

The following pastes were prepared. BaTiO ₃ , MgCO ₃ , Mn having a dielectric particle paste particle size of 0.1 to 1 μm
CO ₃ , CoO, and (Ba _0.5 Ca _0.5 ) SiO ₃ powder were wet-mixed by a ball mill for 16 hours and then dried by a spray drier to obtain a dielectric material. By changing the mixing ratio of each powder, a plurality of dielectric materials were produced.

100 parts by weight of each dielectric material were kneaded with 34 parts by weight of an organic vehicle (12 parts by weight of ethylcellulose resin dissolved in 88 parts by weight of butyl carbitol) and 50 parts by weight of terpineol with a three-roll mill, and the paste was mixed. It has become.

100 parts by weight of Ni particles having an average particle diameter of 0.8 μm for the internal electrode layer paste, 40 parts by weight of an organic vehicle (8 parts by weight of ethyl cellulose resin dissolved in 92 parts by weight of butyl carbitol) and 10 parts by weight of butyl carbitol By weight and kneaded with three rolls to form a paste.

100 parts by weight of Cu particles having an average particle diameter of 0.5 μm for the external electrode paste, 35 parts by weight of an organic vehicle (8 parts by weight of ethyl cellulose resin dissolved in 92 parts by weight of butyl carbitol) and 7 parts by weight of butyl carbitol And kneaded to form a paste.

Using the above-mentioned pastes for the dielectric layers and the pastes for the internal electrode layers, a multilayer ceramic capacitor having the structure shown in FIG. 1 was produced.

First, a dielectric layer paste and an internal electrode layer paste were alternately laminated by a printing method to obtain a green chip. The number of layers of the dielectric layer paste was set to 20 layers.

Next, the green chip was cut into a predetermined size, and binder removal processing, firing and annealing were continuously performed under the following conditions to produce a capacitor chip body.

Binder removal temperature rise rate: 100 ° C./hour Holding temperature: 800 ° C. Temperature holding time: 2 hours Atmospheric gas: humidified N ₂ gas Oxygen partial pressure: 10 ^-4 atm

Baking temperature raising rate: 200 ° C./hour Holding temperature: 1300 ° C. Temperature holding time: 2 hours Cooling rate: 300 ° C./hour Atmospheric gas: humidified mixed gas of N ₂ and H ₂ Oxygen partial pressure: 10 ^{− 9} atm

Annealing holding temperature: 900 ° C. Temperature holding time: 9 hours Cooling rate: 300 ° C./hour Atmospheric gas: humidified N ₂ gas Oxygen partial pressure: 10 ⁻⁵ atm

A wetter was used for humidifying each atmosphere gas, and the water temperature was 35 ° C.

After polishing the end face of the obtained capacitor chip body by sandblasting, the above-mentioned external electrode paste was transferred to the end face, and baked at 800 ° C. for 10 minutes in an N ₂ + H ₂ atmosphere to form an external electrode. Then, a multilayer ceramic chip capacitor sample was obtained.

The size of each sample manufactured in this manner was 3.2 mm × 1.6 mm × 1.2 mm, the thickness of the dielectric layer was 20 μm, and the thickness of the internal electrode layer was 2.5 μm. Was.

Table 1 shows the composition of the dielectric layer of each sample.
Shown in In addition, these compositions were calculated according to the above-mentioned criteria. Further, the glass in Table 1 means (Ba _0.5 Ca
_0.5 ) SiO ₃ .

The following measurement was performed for each sample. Table 1 shows the results.

Temperature Characteristics of Capacitance The capacitance was measured at a measurement voltage of 1 V at -55 to 125 ° C. using an LCR meter to check whether or not the following characteristics were satisfied. When satisfied, it was evaluated as ○, and when it was not satisfied, as ×.

X7R characteristics: Capacitance change within ± 15% between −55 ° C. and 125 ° C. (reference temperature 25 ° C.)

B characteristic: the rate of change of capacity is within ± 10% between -25 ° C. and 85 ° C. (reference temperature 20 ° C.)

Time-dependent change of capacitance under DC electric field A DC electric field of 1.8 V (voltage applied to the sample: 36 V) per 1 μm of the thickness of the dielectric layer was applied at 40 ° C. for 1000 hours. After being left at room temperature for 24 hours, the capacitance was measured, and the amount of change ΔC from the capacitance C ₀ (initial capacitance) before the application of the DC electric field was obtained to calculate the rate of change ΔC / C ₀ . The capacity was measured under the above conditions.

An acceleration test was performed under the electric field of 10 V / μm at an accelerated life of insulation resistance IR at 200 ° C.
The time until the resistance (IR) became 2 × 10 ⁵ Ω or less was defined as the life time.

Relative permittivity ε _s The relative permittivity at 25 ° C. was measured.

[0082]

[Table 1]

From the results shown in Table 1, the effect of the present invention is clear. That is, in a sample in which the composition of the dielectric layer is within the range of the present invention, the X7R characteristic or the B characteristic is satisfied, and the rate of change with time of the capacitance under a DC electric field is 10%.
Below, and the insulation resistance I in the accelerated test
R has a long life.

The scanning electron micrographs of the cross section of the dielectric layer of Sample No. 9 of the present invention and Sample No. 1 of Comparative Example are shown in FIGS. 2 and 3, respectively. A photograph was taken after the cross section was mirror-polished and etched with a mixed aqueous solution of hydrofluoric acid and nitric acid. From these figures, it can be seen that the average crystal grain size of sample No. 1 (FIG. 3), which is
μm, and the average width of the crystal grain boundaries is about 0.2 μm. In the sample No. 9 of the present invention (FIG. 2), the average crystal grain size is about 0.3 μm.
5 μm, and the average width of the crystal grain boundaries is as fine as about 0.2 μm. Note that a similar relationship was observed for the other comparative samples shown in Table 1 and the sample of the present invention.

Further, transmission electron micrographs of the dielectric layer of Sample No. 2 of the comparative example were taken before and after the application of the DC electric field. FIG. 4 shows a photograph before the application, and FIG. 5 shows a photograph after the application. 4 and 5 that the domain is reduced by the application of the DC electric field.

[0086]

According to the present invention, by setting the dielectric layer to a predetermined composition, the X7R characteristic and the B
A multilayer ceramic chip capacitor that satisfies the characteristics, has a small change in capacitance under a DC electric field with time, and has a long accelerated life of the insulation resistance IR can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a preferred embodiment of a multilayer ceramic chip capacitor according to the present invention.

FIG. 2 is a scanning electron micrograph of a cross section of a dielectric layer of a multilayer ceramic chip capacitor of the present invention, which is a drawing substitute photograph showing a particle structure.

FIG. 3 is a drawing substitute photograph showing a particle structure, and is a scanning electron microscope photograph of a cross section of a dielectric layer of a conventional multilayer ceramic chip capacitor.

FIG. 4 is a drawing substitute photograph showing a particle structure, and is a transmission electron micrograph of a dielectric layer of a multilayer ceramic chip capacitor.

FIG. 5 is a drawing substitute photograph showing a particle structure, and is a transmission electron microscope photograph of a dielectric layer of a multilayer ceramic chip capacitor after application of a DC electric field.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer ceramic chip capacitor 10 Capacitor chip body 2 Dielectric layer 3 Internal electrode layer 4 External electrode

Claims (4)

(57) [Claims] 1. A multilayer ceramic chip capacitor having a capacitor chip body having a structure in which dielectric layers and internal electrode layers are alternately stacked, wherein the dielectric layer contains barium titanate as a main component, and
For 100 moles of the barium titanate converted to TiO ₃ , 0.5 to 3 moles of magnesium oxide converted to MgO, and 0.1 to 0.5 moles of manganese oxide and CoO converted to MnO. includes 0.05 to 0.3 mol of cobalt oxide as a secondary component Te, further, as a secondary component, glassy _{(Ba x Ca 1-x O} ) y · SiO 2 ( provided that, 0.3 ≦ x ≦ 0 0.7, 0.95 ≦ y ≦ 1.05) with respect to the total of BaTiO ₃ , MgO, MnO and CoO in an amount of 3 to 7% by weight. 2. The method according to claim 1, wherein the conductive material contained in the internal electrode layer is N
The multilayer ceramic chip capacitor according to claim 1, wherein the capacitor is an i or Ni alloy. 3. The multilayer ceramic chip capacitor according to claim 2, wherein the multilayer ceramic chip capacitor is fired in an atmosphere having an oxygen partial pressure of 10 ^-8 to 10 ^-12 atm in a temperature range of 1200 to 1380 ° C. 4. The multilayer ceramic chip capacitor according to claim 2, wherein after firing, the multilayer ceramic chip capacitor is annealed in an atmosphere having an oxygen partial pressure of 10 ⁻⁶ atm or more within a temperature range of 1100 ° C. or less.