JP2970594B2 - Flip-flop circuit and integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit connected to an input terminal and an output terminal of a macro cell in which a scan path test is executed separately from a peripheral circuit, and the flip-flop circuit is connected to the macro cell. The present invention relates to an integrated circuit device connected to an input terminal and an output terminal.

[0002]

2. Description of the Related Art Conventionally, there is a scan path test method as a test method for an integrated circuit device. In this test method, a test pattern is generally created by an automatic creation program. However, the RAM (Rand
am Acess Memory)
Since this is tested separately from the surrounding circuits, for example, a flip-flop circuit is provided on the wiring between its input and output to hold a test pattern.

However, since this flip-flop circuit is a device for the scan path test method and is unnecessary in normal operation, a wiring bypassing the flip-flop circuit is also formed, and this wiring and the wiring of the flip-flop circuit are selected. A selector circuit is also provided.

A conventional example of the above-described integrated circuit device will be described below with reference to FIGS. 5 is a block diagram showing a main part of the integrated circuit device, FIG. 6 is a circuit diagram showing an internal structure of the flip-flop circuit, and FIG. 7 is a circuit diagram showing an internal structure of the selector circuit.

As shown in FIG. 5, the integrated circuit device 1 includes a macro cell 2 in which a scan path test is executed separately from peripheral circuits. Are provided with flip-flop circuits 5 and 6, respectively.

Further, wirings 7 and 8 that bypass these flip-flop circuits 5 and 6 are also formed in parallel with the wirings 3 and 4, and these wirings 3 and 4 and the wirings 7 and
8 is connected to the selector circuits 9 and 10. A control circuit 11 is connected to the selector circuits 9 and 10, and the control circuit 11 generates a test mode switching signal.

The flip-flop circuits 5 and 6 are arranged as shown in FIG.
As shown in the figure, the input terminal 21 and the output terminal 22 of the processing data of the macro cell 2, the input terminal 23 of the shift mode switching signal, and the input terminal 2 of the scan mode switching signal
4, a clock signal input terminal 25, and the like.

An input terminal 21 for processing data includes an inverter circuit 26, a transfer gate 27, a first latch circuit 28, a second latch circuit 29, an inverter circuit 30,
Are connected in series.
Are connected to the output terminal 22.

In the latch circuits 28 and 29, transfer gates 33 and 34 and inverter circuits 35 and 36 are arranged in series on wires 31 and 32 communicating from the input terminal to the output terminal. Wirings 37 and 38 for returning from the output terminals of the first inverter circuits 35 and 36 to the input terminals are formed, and the inverter circuits 39 and 40 and the transfer gates 41 and 42 are arranged in series on the wirings. ing.

The transfer gates 33, 34, 4
1, 42 are p-channel and n-channel MOS (Meta
l Oxide Semiconductor) A transistor in which the source and the drain of a transistor are connected, and the gates of the p-channel and n-channel transistors are used as input terminals for a clock signal.

An input terminal 23 for a shift mode switching signal
Are provided in parallel with the processing data input terminal 21 and are connected to the input terminal of the first latch circuit 28 via the transfer gate 43. Two inverter circuits 44 and 45 are connected in series to the input terminal 24 of the scan mode switching signal, and the output terminals of these inverter circuits 44 and 45 are connected to the transfer gates 27 and 43. . Two inverter circuits 46 and 47 are also connected in series to the input terminal 25 of the clock signal. The output terminals of these inverter circuits 46 and 47 are connected to the transfer gates 33 and 34 of the latch circuits 28 and 29, respectively. 41 and 42 are connected.

The selector circuits 9 and 10 include an input terminal 51 for processing data connected to the wirings 3 and 4, an input terminal 52 for processing data connected to the wirings 7 and 8, an output terminal 53 for processing data, An input terminal 54 for a switching signal connected to the control circuit 11 is provided.

The input terminal 51 includes an inverter circuit 5
5, a transfer gate 56 and an inverter circuit 57 are connected in series, and the inverter circuit 57 is connected to the output terminal 53. The input terminal 52 is also connected to an inverter circuit 58 and a transfer gate 59, and the transfer gate 59 is connected to the output terminal 53 via the inverter circuit 57. The transfer gates 56 and 59 are connected, and the output terminals of two inverter circuits 60 and 61 connected in series to the input terminal 54 of the switching signal are connected to the transfer gates 56 and 59.

In the integrated circuit device 1 having the above structure,
During normal operation, the control circuit 11 causes the selector circuit 9 to select the wirings 7 and 8 bypassing the flip-flop circuits 5 and 6, so that input data is input to the macro cell 2 without passing through the flip-flop circuit 5, and The output data is output without passing through the flip-flop circuit 6.

When the scan path test is executed, the control circuit 11 controls the selector circuit 9 to store the flip-flop circuits 5 and 5.
The wirings 3 and 4 of 6 are selected, and these flip-flop circuits 5 and 6 are connected to the input terminal and the output terminal of the macro cell 2.

[0016]

In the integrated circuit device 1 as described above, the selector circuits 9 and 10 switch between the wirings 3 and 4 where the flip-flop circuits 5 and 6 are arranged and the wirings 7 and 8 that are bypassed. Since it is connected to the macro cell 2, both the normal operation and the scan path test can be executed without any trouble.

However, because of this, the selector circuits 9, 10
And the wirings 7 and 8 are required, the circuit becomes large-scale, and the productivity is lowered. In particular, the selector circuits 9 and 10
Is composed of a large number of inverter circuits 55 and transfer gates 56 and the like, so that the structure is complicated and the circuit scale is large. For example, in the case of the integrated circuit device 1 described above, the flip-flop circuits 5 and 6 and the selector circuits 9 and 10 have a total of 13 gates.

The present invention has been made in view of the above-described problems, and has a flip-flop circuit capable of reducing the scale of an integrated circuit device capable of performing both a normal operation and a scan path test without hindrance; It is an object of the present invention to provide an integrated circuit device capable of performing both a normal operation and a scan path test without any trouble and having a reduced scale.

[0019]

A flip-flop circuit according to the present invention is a flip-flop circuit connected to an input terminal and an output terminal of a macro cell in which a scan path test is executed separately from peripheral circuits. Two latch circuits are arranged in series on a line communicating from a data input terminal to an output terminal, and in these latch circuits, a transfer gate and an inverter circuit are connected in series on a first line communicating from an input terminal to an output terminal. And an inverter circuit and a transfer gate are arranged in series on a second wiring that returns from an output terminal of the inverter circuit to an input terminal, and an input terminal of a clock signal is connected to each of the transfer gates. A signal causes the two transfer gates of the latch circuit to alternately change between a conductive state and a non-conductive state. In the flip-flop circuit, the input data is alternately latched by the two latch circuits, and the input terminals of the test mode switching signal and the two latch circuits are turned on in response to the test mode switching signal. And a switching circuit for holding.

Therefore, when the switching circuit keeps the two latch circuits conductive in response to the switching signal in the test mode, the input data of the flip-flop circuit does not change via the two internal latch circuits. Is output. When the switching circuit releases the conduction state of the two latch circuits in response to the switching signal in the test mode, the flip-flop circuit executes a normal operation of alternately latching input data by the two latch circuits.

The various circuits referred to in the present invention only need to be formed so as to realize their functions. For example, various circuits can be formed uniformly by a thin film technique, and circuits composed of independent chips can be used. Connections, combinations thereof, and the like are allowed.

In another aspect of the flip-flop circuit described above, the switching circuit is also connected to an input terminal of a clock signal, and switches the clock signal and a control signal for holding the latch circuit in a test mode. Selectively output in response to the switching signal. Therefore, when the switching circuit outputs a control signal to the latch circuit in response to the switching signal in the test mode, the input data of the flip-flop circuit is output without change via the two internal latch circuits. When the clock signal is output to the latch circuit, the flip-flop circuit performs a normal operation of alternately latching the input data by the two latch circuits.

In another aspect of the flip-flop circuit as described above, the switching circuit holds the transfer gate of the first wiring of the latch circuit in a conductive state in response to the switching signal, and sets the transfer gate of the second wiring to Keep disconnected. Therefore, when the transfer circuit holds the transfer gate of the first wiring of the latch circuit in a conductive state and the transfer gate of the second wiring in a non-conductive state in response to the switching signal, the latch circuit changes the input data to the first state. Since the data is passed through the transfer gate of the wiring and then inverted by the inverter circuit, the output data that has passed through the two latch circuits is output in the same state as at the time of input.

In another aspect of the flip-flop circuit as described above, a plurality of data lines in which two latch circuits are arranged in series are formed on a line communicating from an input terminal to an output terminal. A switching circuit is commonly connected to the latch circuits of the plurality of data lines. Therefore, the latch circuits of a plurality of data lines are controlled by one switching circuit.

An integrated circuit device according to the present invention includes at least one macro cell for which a scan path test is executed separately from a peripheral circuit, and a flip-flop according to the present invention connected to an input terminal and an output terminal of the macro cell. And a control circuit connected to the input terminal of the test mode switching signal of the flip-flop circuit.

Therefore, the flip-flop circuits connected to both ends of the macro cell are switched between the normal state and the test state by the test mode switching signal output from the control circuit. In the normal state, the flip-flop circuit outputs the input data without being changed by the two latch circuits, so that the macro cell can input and output various data without any trouble. In the test state, the flip-flop circuit alternately latches the input data by the two latch circuits, so that the test pattern can be held by the flip-flop circuit even if the macro cell is excluded from the scan path test.

[0027]

FIG. 1 shows a first embodiment of the present invention.
This will be described below with reference to FIG. Note that the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names, and detailed description is omitted. FIG. 1 is a circuit diagram showing an internal structure of a flip-flop circuit of this embodiment.
FIG. 2 is a block diagram showing a main part of the integrated circuit device according to the present embodiment.

As shown in FIG. 2, in the integrated circuit device 101 of the present embodiment, a scan path test is executed separately from peripheral circuits, as in the integrated circuit device 1 described above as a conventional example. A macrocell 102 is provided, and wirings 103 and 104 for input and output of the macrocell 102 are provided.
The flip-flop circuits 105 and 10 of the present embodiment
6 are provided. However, the aforementioned integrated circuit device 1
Unlike the flip-flop circuits 105 and 10
No wiring or selector circuit is provided to bypass 6,
The control circuit 107 controls the flip-flop circuits 105 and 1
06.

That is, as shown in FIG. 1, the flip-flop circuits 105 and 106 of the present embodiment include an input terminal 111 and an output terminal 112 for processing data of the macrocell 102, an input terminal 113 for a shift mode switching signal,
It has an input terminal 114 for a scan mode switching signal, an input terminal 115 for a clock signal, and the like, as well as an input terminal 116 for a test mode switching signal.

An inverter circuit 117, a transfer gate 118, a first latch circuit 119, a second latch circuit 120, an inverter circuit 121, and the like are connected in series to an input terminal 111 for processing data. 121 is connected to the output terminal 112.

The latch circuits 119 and 120 have wirings 131 and 132 communicating from the input terminals to the output terminals.
In addition, transfer gates 133 and 134 and inverter circuits 135 and 136 are arranged in series. And
Wirings 137 and 138 that return from the output terminals of the first inverter circuits 135 and 136 to the input terminals are formed, and the inverter circuits 139 and 140 and the transfer gates 141 and 142 are arranged in series on these wirings. .

The input terminal 113 for the shift signal is provided in parallel with the input terminal 111 for the processing data, and is connected via the transfer gate 143 to the first latch circuit 119.
Is connected to the input terminal of The input terminal 114 of the scan mode switching signal has two inverter circuits 14
4, 145 are connected in series, and the output terminals of these inverter circuits 144, 145 are connected to the transfer gates 118, 143.

A switching circuit 151 is connected to the input terminal 115 for the clock signal and the input terminal 116 for the switching signal for the test mode, and the switching circuit 151 is connected to the transfer gates 13 of the latch circuits 119 and 120.
3, 134, 141 and 142.

More specifically, in the switching circuit 151,
The input terminals 115 and 116 are connected to a NOR gate 152, and the NOR gate 152
53 are connected. The output terminals of the NOR gate 152 and the inverter circuit 153 are connected to the two transfer gates 134, 1 of the second latch circuit 120.
42 are connected to input terminals of a pair of clock signals.

The input terminal 116 is connected to an inverter circuit 154.
4 and the input terminal 115 are connected to a NAND gate 155. An inverter circuit 156 is connected to the NAND gate 154, and output terminals of the NAND gate 154 and the inverter circuit 156 are connected to the two transfer gates 13 of the first latch circuit 119.
3, 141 are connected to input terminals of a pair of clock signals.

In the above-described configuration, the integrated circuit device 101 of the present embodiment can execute both the normal operation and the scan path test without any trouble. More specifically, when the integrated circuit device 101 executes the scan path test, the control circuit 107 receives the input terminal 1 of the flip-flop circuits 105 and 106 as a test mode switching signal.
16 is in a low state.

Then, NOR gate 152 connected to input terminal 116 inverts the clock signal input from the other input terminal 115 and outputs the inverted signal. Therefore, this clock signal and the inverted clock through inverter circuit 153 are output. Is output to the transfer gates 134 and 142 of the second latch circuit 120 as a control signal.

At the same time, a NAND gate 155 connected to the input terminal 116 via the inverter circuit 154 is also provided.
Since the clock signal input from the other input terminal 115 is inverted and output, the inverted clock and the clock signal via the inverter circuit 156 are transmitted to the transfer gates 133 and 141 of the first latch circuit 119 as control signals. Is output.

Therefore, the flip-flop circuits 105, 1
In No. 06, the input data is alternately latched by the two latch circuits 119 and 120 in accordance with the clock signal, so that the scan path test in which the macro cell 102 is separated can be easily executed.

On the other hand, when the integrated circuit device 101 performs a normal operation, the control circuit 107 sets the input terminals 116 of the flip-flop circuits 105 and 106 to a high state as a test mode switching signal.

Then, the NOR gate 152 connected to the input terminal 116 outputs a low signal irrespective of the clock signal input from the other input terminal 115. Therefore, the NOR gate 152 outputs the low signal via the inverter circuit 153. The high signal is output to the transfer gates 134 and 142 of the second latch circuit 120 as a control signal.

At the same time, a NAND gate 155 connected to the input terminal 116 via the inverter circuit 154 is also provided.
Since a low signal is output irrespective of the clock signal input from the other input terminal 115, the low signal and the high signal via the inverter circuit 156 are transmitted to the transfer gates 133 and 141 of the first latch circuit 119. It is output as a control signal.

Therefore, the first and second latch circuits 119, 1
In 20, the transfer gates 133 and 134 of the first wirings 131 and 132 are kept conductive, and the transfer gates 141 and 1 of the second wirings 137 and 138 are held.
42 will be kept in a disconnected state. In such a state, the first latch circuit 119 inverts the input data by the inverter circuit 135 of the first wiring 131 and then passes the transfer gate. Output in the same state.

That is, the flip-flop circuit 105
The input data is output to the macro cell 102 without being changed, and the output data of the macro cell 102 is output without being changed by the flip-flop circuit 106.
It can function similarly to the state where 106 is not present.

As described above, the integrated circuit device 101 of the present embodiment can execute both the normal operation and the scan path test without any trouble, but for this purpose, the wiring bypassing the flip-flop circuits 105 and 106 is provided. Since no circuit or selector circuit is required, the circuit can be reduced and productivity can be improved. For example, in the case of the integrated circuit device 101 of the present embodiment, the flip-flop circuit 10
The number of gates of 5,106 is 11 in total, which is a reduction of nearly 20% compared to 13 in one conventional example.

The present invention is not limited to the above-described embodiment, but allows various modifications without departing from the gist of the present invention. For example, in the above embodiment, the flip-flop circuit 1
05, 106 input terminal 111, 113 to output terminal 1
The two latch circuits 119 and 12
Although 0 is exemplified as having one data line arranged in series, as shown in FIGS. 3 and 4, a plurality of data lines as described above may be provided.

In the integrated circuit device 201 of this modified example,
The macro cell 202 corresponds to 2-bit processing data. For this reason, there are two data lines 205 and 206 in which the two latch circuits 119 and 120 of the flip-flop circuits 203 and 204 are arranged in series, and each of the two data lines 205 and 206 has two data lines. The number of the switching circuits 151 connected to the latch circuits 119 and 120 is one. That is, the operation of the four latch circuits 119 and 120 can be controlled by one switching circuit 151 in all of the two data lines, and therefore, compared to a conventional 2-bit flip-flop circuit (not shown). The number of gates can be reduced favorably and the circuit scale can be reduced.

[0048]

Since the present invention is configured as described above, it has the following effects.

The flip-flop circuit according to the first aspect of the present invention is a flip-flop circuit connected to an input terminal and an output terminal of a macro cell in which a scan path test is executed separately from peripheral circuits, Two latch circuits are arranged in series on the wiring that communicates from the input terminal to the output terminal, and in these latch circuits, the transfer gate and the inverter circuit are arranged in series on the first wiring that communicates from the input terminal to the output terminal In addition, an inverter circuit and a transfer gate are arranged in series on a second wiring that returns from an output terminal of the inverter circuit to an input terminal, and an input terminal of a clock signal is connected to each of the transfer gates. The two transfer gates of the latch circuit are alternately changed between a conductive state and a non-conductive state. In the flip-flop circuit for latching alternately two of the latch circuit inputs data Te,
By providing an input terminal for a test mode switching signal and a switching circuit for holding the two latch circuits in a conductive state in response to the test mode switching signal, a flip-flop is provided by the test mode switching signal. Since the flip-flop circuit can switch between a state in which the input data is alternately latched by the two latch circuits and a state in which the input data is output without changing the input data, the flip-flop circuit is bypassed to realize these states. Wiring and a selector circuit are not required, and the number of gates of an integrated circuit device in which this flip-flop circuit is connected to a macro cell can be reduced, so that the circuit scale can be reduced.

According to a second aspect of the present invention, in the flip-flop circuit according to the first aspect, the switching circuit is also connected to the input terminal of the clock signal, and holds the clock signal and the latch circuit in a conductive state. By selectively outputting the control signal and the test mode switching signal, it is easy to alternately latch the input data and output the input data without changing the two latch circuits. Can switch.

The third aspect of the present invention is the first or second aspect.
The flip-flop circuit according to the above, wherein the switching circuit holds the transfer gate of the first wiring of the latch circuit in a conductive state and holds the transfer gate of the second wiring in a non-conductive state in response to the switching signal, A state in which input data is output without being changed by the two latch circuits can be easily realized.

The invention described in claim 4 is the first to third aspects of the present invention.
The flip-flop circuit according to any one of the above, wherein a plurality of data lines in which two latch circuits are arranged in series are formed on a line communicating from an input terminal to an output terminal, and one switching circuit includes a plurality of switching circuits. Connected in common to the data line latch circuit, the flip-flop circuit and the macro cell can reduce the number of gates of the integrated circuit device corresponding to a plurality of pieces of processing data, thereby reducing the circuit scale. it can.

According to a fifth aspect of the present invention, there is provided the integrated circuit device, wherein the scan path test is executed separately from the surrounding circuits, and at least one macro cell is connected to the input terminal and the output terminal of the macro cell. Item 5 includes the flip-flop circuit according to any one of Items 1 to 4, and a control circuit connected to the input terminal of the test mode switching signal of the flip-flop circuit. Since the flip-flop circuit does not change the processing data to be output and the flip-flop circuit holds the test pattern input / output to / from the macro cell in the test state, the normal operation using the macro cell and the test excluding the macro cell are performed. Can be performed well, and this can be achieved on a small scale with a reduced number of gates. Kill.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an internal structure of a flip-flop circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a main part of the integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a circuit diagram showing an internal structure of a flip-flop circuit according to a modification.

FIG. 4 is a block diagram illustrating a main part of an integrated circuit device according to a modified example.

FIG. 5 is a block diagram showing a main part of an integrated circuit device according to a conventional example.

FIG. 6 is a circuit diagram showing an internal structure of a conventional flip-flop circuit.

FIG. 7 is a circuit diagram showing an internal structure of a conventional selector circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 integrated circuit device 2 macrocell 3,4 wiring 5,6 flip-flop circuit 7,8 wiring 9,10 selector circuit 11 control circuit 21,23 to 25 input terminal 22 output terminal 26 inverter circuit 27 transfer gate 28,29 latch circuit 30 Inverter circuits 31, 32 Wiring 33, 34 Transfer gates 35, 36 Inverter circuits 37, 38 Wiring 39, 40 Inverter circuits 41, 42 Transfer gates 44 to 47 Inverter circuits 51, 52, 54 Input terminals 53 Output terminals 55 Inverter circuits 56 Transfer Gate 57, 58 Inverter circuit 59 Transfer gate 60, 61 Inverter circuit 101 Integrated circuit device 102 Macrocell 103, 104 Wiring 105, 106 Flip-flop circuit 107 Control circuit 11 1,113-116 Input terminal 112 Output terminal 117 Inverter circuit 118 Transfer gate 119,120 Latch circuit 121 Inverter circuit 131,132 Wiring 133,134 Transfer gate 135,136 Inverter circuit 137,138 Wiring 139,140 Inverter circuit 141-143 Transfer gate 144, 145 inverter circuit 151 switching circuit 152 NOR gate 153, 154 inverter circuit 155 NAND gate 156 inverter circuit 201 integrated circuit device 202 macrocell 203, 204 flip-flop circuit 205, 206 data line

Claims (5)

(57) [Claims] 1. A flip-flop circuit connected to an input terminal and an output terminal of a macro cell in which a scan path test is performed separately from a surrounding circuit, wherein the wiring communicates from an input terminal to an output terminal of data. Two latch circuits are arranged in series, and in these latch circuits, a transfer gate and an inverter circuit are arranged in series on a first wiring communicating from an input terminal to an output terminal, and an output terminal of the inverter circuit is provided. An inverter circuit and a transfer gate are arranged in series on a second wiring returning to the input terminal from the input terminal; a clock signal input terminal is connected to each of the transfer gates; and the two transfer gates of the latch circuit are operated by a clock signal. Is alternately changed between a conductive state and a non-conductive state, and input data is exchanged by the two latch circuits. A flip-flop circuit that latches a test mode, comprising: an input terminal for a test mode switching signal; and a switching circuit that holds the two latch circuits in a conductive state in response to the test mode switching signal. A flip-flop circuit characterized by the following. 2. The switching circuit is also connected to an input terminal of a clock signal, and selectively outputs the clock signal and a control signal for keeping the latch circuit in a conductive state in response to a test mode switching signal. The flip-flop circuit according to claim 1, wherein: 3. The switching circuit according to claim 2, wherein the switching circuit holds the transfer gate of the first wiring of the latch circuit in a conductive state and holds the transfer gate of the second wiring in a non-conductive state in response to the switching signal. 3. The flip-flop circuit according to 1 or 2. 4. A data line in which two latch circuits are arranged in series on a line communicating from an input terminal to an output terminal, and one switching circuit is provided for a plurality of data line latch circuits. 4. The flip-flop circuit according to claim 1, wherein the flip-flop circuits are connected in common. 5. The macro-cell according to claim 1, wherein the macro-cell is connected to an input terminal and an output terminal of the macro-cell, wherein the scan-path test is performed separately from surrounding circuits. An integrated circuit device, comprising: a flip-flop circuit; and a control circuit connected to an input terminal of a test mode switching signal of the flip-flop circuit.