JP2962808B2 - Output buffer circuit - Google Patents

Description

The present invention relates to an output buffer circuit provided between an internal circuit of a semiconductor integrated circuit device and an output terminal.

(Prior Art) In an output buffer circuit, a MOS transistor having a large channel width is used so that a large current can flow. When a large current instantaneously flows through the MOS transistor of the output buffer circuit, the time change di / dt of the current increases, and a spike voltage is generated, which becomes noise. Therefore, in order to prevent the MOS transistor of the output buffer circuit from being turned on instantaneously, the meandering of the polycrystalline silicon gate electrode provides a propagation delay time due to the resistance of the gate electrode, and the total current flowing through the output transistor Are distributed over time.

(Problems to be Solved by the Invention) In order to meander the polycrystalline silicon gate electrode in the output buffer circuit, it is necessary to change the layout of the MOS transistors registered by CAD or the like.

To change the propagation delay time, it is necessary to change the number and size of the sub-transistors formed along the meandering gate electrode, which lacks design flexibility.

The present invention disperses the entire current of the output buffer circuit over time to effectively reduce di / dt and reduce spike voltage, and eliminates the need to largely change the layout of the output MOS transistor, and also reduces the propagation delay time. It is another object of the present invention to provide an output buffer circuit which can be easily changed.

(Means for Solving the Problems) In the present invention, one or two or more continuous band-shaped gate electrodes are formed in one active region between an internal circuit of a semiconductor integrated circuit device and an output terminal, and the gate electrode is formed under the gate electrode. The threshold voltage of the channel formed in the above is set to be different depending on the location within a range where the threshold voltage is turned on by the voltage applied to the gate electrode.

(Operation) Since the threshold voltage of the channel differs depending on the location, when an input voltage is applied to the gate electrode from an internal circuit, the MOS transistor formed along the gate electrode may be, for example, an N-channel type. For example, if the threshold voltage is low, they are sequentially turned on, and the entire current of the output buffer circuit flows in a dispersed manner over time.

(Embodiment) FIG. 1 shows an embodiment, and FIG. 2 shows an equivalent circuit thereof.

Reference numeral 2 denotes one active region surrounded by a field oxide film on the surface of the silicon substrate, and a plurality of polycrystalline silicon gate electrodes 4 are formed across the active region 2. The gate electrode 4 is integrated, and an input signal is applied from an internal circuit through the through hole 5.

An impurity diffusion region is formed in the active region 2 by ion implantation or diffusion using the gate electrode 4 as a mask.
The diffusion region is a source region 6s, a drain region 6d, a source region 6s, a drain region 6d,... Sequentially sandwiching a channel region below the gate electrode 4. A plurality of contact holes 7 are provided in each of the diffusion regions, the source regions are commonly connected to each other and connected to the ground terminal or the power supply voltage terminal, and the drain regions are commonly connected to the output terminal. It is connected.

A channel region is formed below the gate electrode 4 between the source region 6s and the drain region 6d, and impurities are implanted into the channel region to control the threshold voltage. In this example, the threshold voltage of the gate electrode (the leftmost gate electrode in the figure) closest to the input signal through hole 5 is the lowest, and the threshold of the gate electrode (the rightmost in the figure) closest to the contact hole on the output signal side. The threshold voltage of each gate electrode 4 is sequentially increased from left to right in the figure so as to maximize the value voltage, and each threshold voltage is higher than the high level of the input signal. Set to a lower range. As a result, the sub-transistors a, b, c,... Having different threshold voltages for each gate electrode from left to right in the figure.
i are configured.

 Next, the operation of the present embodiment will be described.

Assuming that the source region 6s is connected to the ground terminal, when a high-level signal is input to the input terminal 5 from the internal circuit, the MOS transistors a with the lower threshold voltage, b,
.., are turned on with a time lag, finally, all the MOS transistors are turned on, and a predetermined total current flows from the output terminal to the ground terminal. As a result, the effective value of the time change di / dt of the current decreases.

In order to control the threshold voltage by controlling the amount of impurities to be implanted into the channel region, ions may be implanted by a direct writing method.

As another method for making the threshold voltage different in location, the thickness of the gate oxide film may be made different in location.

(Effect of the Invention) In the present invention, the threshold voltage of the channel formed in the output buffer circuit is made different depending on the location, so that when an input signal is applied, the output MOS transistor is partially turned on with a time lag. Therefore, the effective value of the time change of the output current is reduced, and the spike voltage generated by switching is reduced. Such an output buffer circuit is particularly effective, for example, for an ultra-high-speed CMOS semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a layout pattern showing one embodiment,
FIG. 2 is an equivalent circuit diagram of the embodiment. 2 ... active region, 4 ... gate electrode, 6 s ... source region, 6 d ... drain region, a to i ... sub-MOS transistor.

Claims (1)

(57) [Claims] An active region between an internal circuit of a semiconductor integrated circuit device and an output terminal is formed with one or more continuous band-shaped gate electrodes, and a channel formed under the gate electrode is formed. The threshold voltage is set differently depending on the location within a range where the threshold voltage is turned on by the voltage applied to the gate electrode, and the gate electrode is connected to an internal circuit,
An output buffer circuit in which one of the drains is connected to an output terminal and the other is connected to a high-voltage power supply terminal or a low-voltage power supply terminal.