JP2945193B2 - IC card test method, and IC card and test apparatus suitable for implementing the method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for an IC card, and more particularly to a test method for simultaneously testing a plurality of IC cards.

[0002]

2. Description of the Related Art In recent years, as a new information storage medium, IC
Cards are getting attention. In particular, I with a built-in CPU
The C card has a function of performing not only storage of information but also arithmetic processing, and is therefore being used for various purposes. Generally, such an IC card with a built-in CPU includes an I / O card for transferring information between a reader / writer device and a storage device such as a ROM, a RAM, and an EEPROM in addition to the CPU.
An / O device is built in.

[0003] When an IC card having such a complicated function is supplied to the market, it is necessary to perform a strict test before shipment. That is, a predetermined test command is given to the IC card as an input signal, a response obtained by executing the test command is taken out as an output signal, and it is determined whether or not this response logically matches the expected result. Test whether the IC card functions normally. To efficiently test mass-produced IC cards, for example, see
Japanese Patent Publication No. 296165 discloses an IC card test apparatus capable of simultaneously testing a plurality of IC cards.

[0004]

When performing a test on a plurality of IC cards at the same time, a point to keep in mind is that even when a test command is given to the plurality of IC cards at the same time from the test apparatus side, each test is performed. The response from the IC card is not always the same. This is
This is because the C card has an EEPROM as a storage device. To test the EEPROM, it is necessary to write some data here. However, EE
Since the time required for writing to the PROM differs for each device, when a test command for instructing the writing operation to the EEPROM is given to a plurality of IC cards, the response returns from the IC cards vary.

[0005] Therefore, the above-mentioned Japanese Patent Application Laid-Open No. 2-296165 has been proposed.
In the test apparatus disclosed in Japanese Patent Application Laid-Open Publication No. H10-264, buffers as many as the number of IC cards to be tested are prepared, and each IC card is prepared.
In this method, the response returned from the card is temporarily stored in this buffer, and each response is read out from this buffer and a test is performed later. However, there is a limit to the capacity of a buffer that can be prepared in the test apparatus, and as the number of IC cards to be tested increases, the buffer capacity assigned to one IC card must be reduced. For this reason, if the time difference between the writing time of the IC card with the fastest processing and the writing time of the IC card with the slowest processing is large, the buffer for storing the response from the IC card with the fastest processing overflows. Even so, a situation occurs in which a response from the IC card that is the slowest in processing is not returned. When such a situation occurs, the IC card for which the response could not be correctly recognized must be tested again.

Accordingly, an object of the present invention is to provide a test method capable of reliably performing a test on a plurality of IC cards.

[0007]

According to the present invention, a predetermined test command is transmitted to a plurality of IC cards, and a response returned from each IC card in response to the command is received. In the IC card test method for testing each IC card by determining whether or not the response is a function of temporarily holding a response to be returned to each IC card in an internal memory, a predetermined response request command Is provided, a function of returning a response held in the internal memory is added. When it is expected that responses have been prepared for all of the plurality of IC cards, the response request is sent to each IC card. A command is given, and a response returned from each IC card is received at the same time.

[0008]

[Operation] First, a predetermined test command is transmitted from a test apparatus to a plurality of IC cards. Each IC card performs a predetermined process (for example, a process of writing to an EEPROM) based on the test command, and generates a response to be returned. This response is temporarily stored in the internal memory (for example, RAM) of the IC card. When a predetermined set time has elapsed since the test command was transmitted to the IC card, a plurality of I
This time, a response request command is transmitted to the C card. If the predetermined set time is set to a time at which the preparation of the response is expected to be completed for all of the plurality of IC cards, the internal memory of all the IC cards is set when the response request command is transmitted. , The response to be returned is already held.
If each IC card performs a process of returning the temporarily held response to the test device in response to the response request command, the test device can simultaneously obtain responses from a plurality of IC cards.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a block diagram illustrating a method for testing an IC card according to an embodiment of the present invention. This block diagram includes an IC card test apparatus 100 used for this test method and a plurality of IC cards 1, 2, 3, 3.
…It is shown. The IC card test device 100 includes a reader / writer unit 110 and an inspection processing unit 120. The reader / writer unit 110 has a function of transmitting data to the plurality of IC cards 1, 2, 3, and a function of receiving data. The inspection processing unit 120
This is a part that performs a substantial process of the test, generates a predetermined test command, transmits it to each IC card via the reader / writer unit 110, and transmits a response from each IC card to the reader / writer unit 110. And a function of testing whether the received response is logically expected data or not.

The IC card 1 includes an I / O device 11 for transmitting and receiving data to and from a reader / writer unit 110, a CPU 12
And ROM13, RAM14, EE as internal memory
A PROM 15. The CPU 12 has a ROM 13
Various processes are executed based on the programs in the program. IC
The cards 2, 3,... Have exactly the same configuration.

Now, consider the case where the IC card test apparatus 100 tests the EEPROM of each IC card. Of course, the IC card test apparatus 100 has a function of testing a program in the ROM of each IC card, a test of the RAM, and the like. However, the feature of the present invention lies in the test of the EEPROM. Here, only the test of the EEPROM will be considered. First, the IC card test apparatus 100
A predetermined test command is transmitted to the card. For example, in the IC card 1, a test command transmitted from the reader / writer unit 110 is fetched by the I / O device 11 and executed by the CPU 12. This test command is a command for instructing a write operation to the EEPROM 15. The CPU 12 has an EEPROM 15
Completes the write operation to the specific address of the I / O device 1
This response is sent back to the reader / writer unit 110 via the PC 1. The inspection processing unit 120 compares this response with predetermined logical data to determine whether the response is normal.

FIG. 2 is a time chart of such a test operation. FIG. 2A shows a reader / writer unit 110 and an IC.
FIG. 2B shows transfer data between the reader / writer unit 110 and the IC card 2, and FIG.
(c) shows transfer data between the reader / writer unit 110 and the IC card 3 respectively. In each case, data transmitted from the reader / writer unit 110 is shown above the horizontal line, and data transmitted from the IC card is shown below the horizontal line. Now, it is assumed that at time t1, the test command A is simultaneously transmitted from the reader / writer unit 110 to each IC card. Upon receiving the test command A, each IC card performs a predetermined write operation to the EEPROM, and upon completion of the write operation, generates a response corresponding to the write operation and returns it to the reader / writer unit 110. However, as described above, since the time for writing to the EEPROM differs depending on each IC card, the time for returning a response also varies for each IC card. In the example of FIG. 2, the response a3 is returned from the IC card 3 at time t2, the response a1 is returned from the IC card 1 at time t3, and the response a2 is returned from the IC card 2 at time t4. I have. As described above, in order to cope with the responses returned with a time lag, the IC card test apparatus 100 shown in FIG. 1 is provided with a buffer 121, and after each response is temporarily stored in the buffer 121, A comparison test with the expected logical value is performed. Subsequently, at time t5, the reader / writer 11
0, a test command B is transmitted to each IC card at the same time.
A predetermined write operation is performed, and when the write operation is completed, a response corresponding to this is generated and returned to the reader / writer unit 110. In the example of FIG. 2, the response b3 is returned from the IC card 3 at time t6, the response b1 is returned from the IC card 1 at time t7, and the response b2 is returned from the IC card 2 at time t8. I have. Responses b1 to b3
Is also stored in the buffer 121, and then a comparison test with a logical value to be expected is performed.

The above operation is described in Japanese Patent Laid-Open No. 2-296 described above.
165 discloses a test method. However, as described above, this method has a problem of overflow because the capacity of the buffer 121 is limited. For example, in the example of FIG.
If the time difference between the time t2 and the time t4 is too large, the response a3 is returned before the time t4 when the response a2 is returned.
Buffer overflows. In this case, a correct test cannot be performed for the responses a1 to a3. The present invention has been devised to enable a correct test even when such a situation occurs.

In the test method according to the present invention, it is necessary to add two new functions to the IC card. This new function is added by modifying the program in the ROM. The first function is to send a response to the test command when returning a response to the test command.
This is a function for temporarily writing to M. In other words, the response is returned to the reader / writer unit 110 and the
It will also be written to AM. Therefore, RAM
It is necessary to secure a special area for temporarily holding this response. For example, in the example of FIG. 2, at time t2, a response a3 is returned from the IC card 3 to the reader / writer unit 110.
The response a3 is also written to the RAM 34 in the IC card 3 and is temporarily stored. Similarly, at time t3, the response a1 is returned and the RAM
At time t4, the response a2 is returned and simultaneously written to the RAM 24. Note that R
Since the holding in the AM is temporary, when the next test command B is transmitted, the responses a1 to a3
It is not necessary to temporarily hold. Therefore, for example, at time t
6, when the response b3 is temporarily stored in the RAM, the response a3 is stored at the same address in the RAM.
May be replaced with the response b3.

A second function added to the IC card is a function of, when a response request command X is given from the reader / writer unit 110, returning a response held in the RAM at that time to the reader / writer unit 110. It is. For example, in the time chart shown in FIG.
Up to 4, it is assumed that the same processing as in the time chart shown in FIG. 2 has been performed. Here, assuming that the response request command X is transmitted from the reader / writer unit 110 to each IC card at the time t5, the responses a1 to a3 are simultaneously returned from all the IC cards at the time t6. Each IC card has RAM at that time
Is read out, and the response is returned to the reader / writer unit 110 as it is. In this case, since no write operation to the EEPROM is involved, the time required for returning the response depends on which IC
It is almost the same for the card, and it can be considered that a response is returned at the same time at time t6.

In order to execute the test method according to the present invention, it is necessary to add a new function to the IC card test apparatus 100 as well. That is, the function is to transmit a response request command X to each IC card at a predetermined time. Regarding the timing of transmitting the response request command X, some embodiments are conceivable. In the simplest embodiment, after transmitting a test command at time t1, a response request command X is transmitted at a predetermined time t5 at which responses from all IC cards can be expected to be completed. I just need. That is, the IC card test apparatus 100 only needs to automatically transmit the response request command X when a predetermined set time has elapsed after transmitting the test command. As shown in FIG. 3, if the response request command X is transmitted at time t5, responses a1 to a3 are obtained simultaneously at time t6, so that a predetermined test process may be performed on this response. Although responses are individually obtained at times t2, t3, and t4, these may be ignored. Therefore, in the case of this embodiment, it is not necessary to prepare the buffer 121 on the IC card test apparatus 100 side. When the test processing on the response obtained at time t6 is completed, a test command B is transmitted at time t7,
Then, when a predetermined time has elapsed, the response request command X may be transmitted in the same manner.

In the above-described embodiment, the same response is returned twice each. In other words, the first response returned individually for each IC card is ignored,
Only the second response returned from all IC cards at the same time is used for the test. Thus, the method of returning the same response twice is useless. One way to eliminate such waste is to stop individual response return processing by each IC card. For example, in the example shown in FIG. 3, the response return processing at times t2, t3, and t4 may be stopped. After generating the response, the IC card performs only the process of temporarily storing the response in the RAM, and performs the process of returning the response only when the response request command X is given. In this way, the response is always returned only once at the same time for all the IC cards, thereby eliminating waste.

Another method for reducing waste is to transmit the response request command X only when necessary. The problem of the conventional method using the buffer 121 occurs when the buffer overflows. Therefore, there is no problem as long as the buffer does not overflow. Therefore, the test is usually performed after accumulating the responses returned with a time difference in the buffer by the conventional method. That is, usually, FIG.
The test is performed according to the method shown in the time chart of FIG. However, each response is stored in RAM when returned.
To save temporarily. The response temporarily stored in the RAM is not normally used. In the event of a buffer overflow, a method unique to the present invention is implemented.
That is, when the buffer overflows, the response request command X is transmitted from the IC card test apparatus 100 at an appropriate point in time, and the response temporarily stored in the RAM is returned. According to such a method, a lean and efficient test can be performed.

[0019]

As described above, according to the method for testing an IC card according to the present invention, the response to be returned from the IC card is temporarily stored in the internal memory. It can be performed reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a method for testing an IC card according to an embodiment of the present invention.

FIG. 2 is a time chart showing a test operation according to a conventional test method.

FIG. 3 is a time chart showing a test operation by a test method according to the present invention.

[Explanation of symbols]

 1, 2, 3 ... IC card 11, 21, 31 ... I / O device 12, 22, 32 ... CPU 13, 23, 33 ... ROM 14, 24, 34 ... RAM 15, 25, 35 ... EEPROM 100 ... IC card Test device 110: Reader / writer unit 120: Inspection processing unit 121: Buffer A, B: Test command a1 to a3, b1 to b3: Response X: Response request command

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-90984 (JP, A) JP-A-3-90985 (JP, A) JP-A-3-90983 (JP, A) JP-A-2- 296165 (JP, A) JP-A-2-93390 (JP, A) JP-A-2-59937 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06K 19/07 G06K 11 / 22 330 G06K 17/00

Claims (3)

(57) [Claims] 1. A predetermined test command is transmitted to a plurality of IC cards, a response returned from each IC card is received in response to the command, and it is determined whether or not the response is as expected. Thus, there is provided an IC card test method for testing each IC card, wherein each IC card has a function of temporarily holding a response to be returned in an internal memory, and a method of receiving a predetermined response request command. And a function of returning a response held in the internal memory, and when the response is expected to be ready for all of the plurality of IC cards, the response request command is given to each IC card. A method for testing an IC card, wherein a response returned from the IC card is simultaneously received. 2. An IC card capable of performing the test method according to claim 1, wherein when a predetermined test command is given from a test device, a function to generate a response to be returned in response to the command. A function of temporarily holding the generated response in an internal memory; and a function of returning a response held in the internal memory when a predetermined response request command is given from a test device. An IC card characterized by the above-mentioned. 3. A test apparatus for performing the test method according to claim 1, wherein a function of transmitting a predetermined test command to a plurality of IC cards, and a predetermined set time from the time of transmitting the test command. After the lapse of time, a function of giving a response request command to each of the IC cards, and a response returned from each of the IC cards in response to the response request command, and determining whether or not the response is as expected And a function for testing each IC card.