JP2944618B1 - Current control circuit - Google Patents

Abstract

A current flowing through a current mirror circuit is selectively controlled to a current determined by an external resistor or an internal resistor depending on whether an external resistor is connected to an external resistor connection terminal or short-circuited to GND. To provide a current control circuit that enables A current mirror circuit has first and second input terminals.
A first terminal of a second switch is connected, a second terminal of the first switch is connected to an input terminal for connecting an external resistor, and a second terminal of the second switch is connected to an internal resistor. Connected to the input terminal through, when the input terminal is set to the reference potential, the second switch is turned on, the first switch is turned off, an external resistor is connected to the input terminal At this time, there is provided circuit means for switching control so that the first switch is turned on and the second switch is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a current control circuit, and more particularly to a circuit for controlling an output current of a current mirror circuit.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional current control method for a current mirror circuit. Referring to FIG. 2, a P-channel MOS transistor PM having a source and a gate connected to a power supply and a drain connected to a resistor R1 or an internal resistor R2.
1, the source is connected to the power supply and the gate is a P-channel MO.
A P-channel MOS transistor PM4 commonly connected to the gate of the S-transistor PM1 to take out an output current from the drain thereof.
1 or a current determined by the internal resistance R2 and the P-channel MOS transistor PM1
The output is made from the drain of the OS transistor PM4.

As described above, in the conventional circuit configuration,
An internal resistor R2 is inserted into the LSI to determine a current flowing through the P-channel MOS transistor PM4, or
By connecting an external resistor R1 to the outside of the LSI, the current flowing through the P-channel MOS transistor PM4 is determined.

[0004]

However, in the above-described circuit configuration, when the current flowing through the P-channel MOS transistor PM4 is determined using the internal resistance R2 in the LSI, the internal resistance generally has the value of the resistance value. Large variations, and therefore large variations in output current,
There is a problem that.

Conversely, when the external resistor R1 is used, a pin for connecting the external resistor R1 is required, although the variation in the resistance value of the external resistor is small.

If it is not possible to determine which of the internal resistance and the external resistance has the greater advantage, a method of switching between the two can be used. In this case, the external resistance R1 connection pin is used. In addition, it is necessary to provide a control pin for switching control or a register.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a current mirror circuit by connecting an external resistor to an external resistor connection terminal or by short-circuiting to GND. The present invention is to provide a current control circuit capable of selectively controlling a current flowing through a resistor to a current determined by an external resistor or an internal resistor.

[0008]

To achieve the above object, the present invention relates to a circuit for controlling a current flowing to an output terminal of a current mirror circuit by limiting a current flowing to an input terminal of the current mirror circuit with a resistor. A configuration in which the external resistor or the internal resistor is selected as a resistor for limiting an input current flowing to an input terminal of the current mirror circuit depending on whether an external resistor is connected to the terminal or the terminal is used as a reference potential. It is said.

The present invention is a circuit for controlling a current flowing to an output terminal of the current mirror circuit by limiting a current flowing to an input terminal of the current mirror circuit with a resistor. The first terminal of the second switch is connected, the second terminal of the first switch is connected to an input terminal for connecting an external resistor, and the second terminal of the second switch is connected to an internal resistor. When the input terminal is set to the reference potential, the second switch is turned on, the first switch is turned off, and an external resistor is connected to the input terminal. Circuit means for controlling the switching so that the first switch is turned on and the second switch is turned off when the first switch is turned on.

[0010]

Embodiments of the present invention will be described. In the embodiment of the present invention, an LSI including a circuit for limiting a current flowing to an input terminal of a current mirror circuit (PM1, PM4 in FIG. 1) with a resistor to limit a current flowing to an output terminal of the current mirror circuit. , The first terminals of the first and second switching transistors (PM2 and PM3 in FIG. 1) are connected to the input terminal side of the current mirror circuit, and the first switching transistors (PM2 and PM3 in FIG. 1) are connected.
The second terminal 2) is an input terminal for connecting an external resistor (FIG. 1).
Of the second switch transistor (PM3 of FIG. 1) is connected to the input terminal (terminal 1 of FIG. 1) via the internal resistance (R2 of FIG. 1) of the LSI. A first inverter (INV1 in FIG. 1) having an input terminal (terminal 1 in FIG. 1) connected to the input terminal and an output terminal connected to the control terminal of the first switching transistor (PM2 in FIG. 1).
And the output terminal of the first inverter is connected to the input terminal, and the output terminal is connected to the second switching transistor (PM3 in FIG. 1).
Of the second inverter (INV in FIG. 1)
2).

In the embodiment of the present invention, when the input terminal (terminal 1 in FIG. 1) is set to the first reference potential (GND in FIG. 1), the second switching transistor (FIG.
PM3) is on, the first switching transistor (PM2 in FIG. 1) is off, and the input terminal (terminal 1 in FIG. 1) is connected to the reference potential via an external resistor. One switch transistor (PM2 in FIG. 1)
Is in the ON state, the second switching transistor (FIG. 1)
The switching control is performed such that PM3) is turned off.

The first inverter (INV in FIG. 1)
The logic threshold level of 1) is determined when a reference potential (GND level) is applied to the input terminal (terminal 1 in FIG. 1).
An external resistor (R1 in FIG. 1) is connected to the input terminal (terminal 1 in FIG. 1).
Are set such that the logic levels of the outputs thereof are complementary to each other when they are connected to the reference potential via.

In the embodiment of the present invention, the current supply transistor of the current mirror circuit is switched by the internal resistor (R2 in FIG. 1) without providing a control pin or a register for switching the external resistor and the internal resistor. (PM4 in FIG. 1) or to determine the current flowing in the current supply transistor (PM4 in FIG. 1) of the current mirror circuit by an external resistor (R1 in FIG. 1). can do.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention is:
First P-channel M with source and gate connected to power supply
The OS transistor PM1 and the source are connected to the power supply,
A fourth P-channel MOS transistor PM4 having a gate commonly connected to the gate of the first P-channel MOS transistor PM1 and an output current taken out from a drain;
A source is connected to the drain of the first P-channel MOS transistor PM1, and the drain is connected to the terminal 1; the second P-channel MOS transistor PM2; and the connection between the drain of the second P-channel MOS transistor PM2 and the terminal 1 Inverter INV whose point is connected to the input terminal
1, a second inverter INV2 having an input terminal connected to a connection point between the gate of the second P-channel MOS transistor PM2 and the output terminal of the first inverter INV1, and a source connected to the first and fourth P-channel MOS transistors PM2. Transistor PM1,
A third P-channel MOS transistor PM3 having a gate connected to the commonly connected gate of PM4 and a gate connected to the output terminal of the second inverter INV2;
A second transistor having one end connected to the drain of the S transistor PM3
The other end of the second resistor R2 is connected to the connection point between the second P-channel MOS transistor PM2 and the terminal 1 and is connected to the input terminal of the first inverter INV1. The resistor R1 is connected between the terminal 1 and GND.

The first inverter INV1 is designed so that a threshold (threshold) voltage VT is lower than an intermediate potential (a potential near an intermediate point between the power supply potential VDD and the ground potential GND). The inverter INV2 is an inverter having a normal threshold voltage.

The first resistor R1 is a resistor connected to the outside of the LSI, and the second resistor R2 is an internal resistor of the LSI.

Depending on whether the resistor R1 is connected to the terminal 1 or the terminal 1 is short-circuited to the GND, the current flowing through the fourth P-channel MOS transistor PM4 is determined by the current determined by the external resistor R2. Or
Alternatively, it can be controlled whether the current is determined by the internal resistance R1.

The operation of one embodiment of the present invention will be described. In FIG. 1, by attaching an external resistor R1, the terminal 1 forming the input terminal of the first inverter INV1 has an intermediate potential. Since the threshold voltage VT1 of the first inverter INV1 is designed so that the intermediate potential is greater than VT1, the output of the first inverter INV1 having the intermediate potential as input is at a low level. Therefore, the output of the second inverter INV2 becomes High level, and the third P-channel MOS transistor PM3 turns off.
F, the second P-channel MOS transistor PM2 is ON
And the current determined by the external resistor R1 and the first P-channel MOS transistor PM1 is transferred to the fourth P-channel MO
It can flow to the S transistor PM4.

Further, the external resistor R1 is eliminated, and the terminal 1
Is shorted to GND (GND potential), the first
The output of the inverter INV1 is at a high level, the output of the second inverter INV2 is at a low level,
P-channel MOS transistor PM2 is OFF, the third
P-channel MOS transistor PM3 is turned on,
A current determined by the internal resistance R2 and the first P-channel MOS transistor PM1 can flow through the fourth P-channel MOS transistor PM4.

According to the present embodiment, the P-channel MOS transistor P for supplying the output current depends on whether the external resistor R1 is connected to the terminal 1 or is short-circuited to GND without increasing the control pin or register setting.
It is possible to select whether the current flowing through M4 is a current determined by the external resistor R1 or a current determined by the internal resistor R2.

In the above embodiment, a circuit configuration using MOS transistors has been described as an example. However, it is needless to say that the present invention can be applied to a circuit configured with bipolar transistors.

[0023]

As described above, according to the present invention,
Connect an external resistor to the external resistor connection terminal without increasing the control pin or register setting.
There is an effect that the current flowing through the current mirror circuit can be selectively controlled to a current determined by an external resistor or an internal resistor depending on whether the current mirror circuit is short-circuited to ND.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a configuration of a conventional current control circuit.

[Explanation of symbols]

 INV1, INV2 Inverters PM1 to PM4 P-channel MOS transistors R1 External resistance R2 Internal resistance

Claims (7)

(57) [Claims] In a current control circuit configured to control an output current with a resistor for limiting a current on an input side, the current is controlled by connecting an external resistor to a terminal or setting the terminal to a reference potential. A current control circuit, wherein the external resistance or the internal resistance is selected as a resistance to be controlled. 2. A semiconductor device comprising a circuit for controlling an output current with a resistor for limiting a current on an input side, wherein first terminals of first and second switches are connected to the input side, The second terminal of the switch is connected to an input terminal for connecting an external resistor, the second terminal of the second switch is connected to the input terminal via an internal resistor, and the input terminal is connected to a reference potential. When set to, the second switch is on, the first switch is off, the output current is controlled by the internal resistance, and when an external resistance is connected to the input terminal, The first switch is turned on, the second switch is turned off,
A current control circuit comprising circuit means for performing switching control so as to control the output current with the external resistor. 3. A semiconductor device comprising a circuit for controlling an output current with a resistor for limiting a current on an input side, wherein first terminals of first and second switch transistors are connected to an input side of a current mirror circuit. Connected, a second terminal of the first switch transistor is connected to an input terminal for connecting an external resistor, and a second terminal of the second switch transistor is connected to the input terminal via an internal resistor. A first inverter having the input terminal connected to the input terminal and an output terminal connected to the control terminal of the first switch transistor; and a first inverter having the output terminal connected to the input terminal and having the output terminal connected to the input terminal. A second inverter connected to a control terminal of a second switch transistor, wherein when the input terminal is set to the reference potential, the second switch transistor is in an on state; When one switch transistor is turned off, the output current is controlled by the internal resistance, and the input terminal is connected to a reference potential via an external resistor, the first switch transistor is turned on. Current control circuit, wherein the second switch transistor is turned off, and the output current is controlled by the external resistor. 4. A current control circuit for controlling a current flowing to an output terminal of the current mirror circuit by determining a current flowing to an input terminal of the current mirror circuit by a resistor connected to the input terminal side. The external resistor or the internal resistor is selected as a resistor for limiting an input current flowing to an input terminal of the current mirror circuit depending on whether a resistor is connected or the terminal is set to a reference potential. A current control circuit, characterized in that: 5. A semiconductor device comprising a circuit for controlling a current flowing to an output terminal of the current mirror circuit by determining a current flowing to an input terminal of the current mirror circuit by a resistor connected to the input terminal side. The first terminal of the first and second switches is connected to the input terminal side of the mirror circuit, the second terminal of the first switch is connected to an input terminal for connecting an external resistor, The second terminal of the second switch is connected to the input terminal via an internal resistor. When the input terminal is set to the reference potential, the second switch is turned on, and the first switch is turned off. Circuit means for switching so that the first switch is turned on and the second switch is turned off when an external resistor is connected to the input terminal. Current control Circuit. 6. A semiconductor device comprising a circuit for controlling a current flowing to an output terminal of the current mirror circuit by determining a current flowing to an input terminal of the current mirror circuit by a resistor connected to the input terminal. The first terminal of the first and second switch transistors is connected to the input terminal side of the current mirror circuit, and the second terminal of the first switch transistor is connected to the input terminal for connecting an external resistor. A second terminal of the second switch transistor is connected to the input terminal via an internal resistor, the input terminal is connected to an input terminal, and an output terminal is connected to a control terminal of the first switch transistor. A first inverter, and a second inverter that connects the output terminal of the first inverter to the input terminal and connects the output terminal to the control terminal of the second switch transistor; When the input terminal is set to the reference potential, the second switch transistor is turned on, the first switch transistor is turned off, and the input terminal is set to the reference potential via an external resistor. The current control circuit according to claim 1, wherein when connected, the first switch transistor is turned on and the second switch transistor is turned off. 7. A logic threshold level of the first inverter is determined when the reference potential is applied to the input terminal and when the input terminal is connected to the reference potential via the external resistor. 7. The current control circuit according to claim 3, wherein a logic level of the output is set to a complementary logic value.