JP2943307B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a built-in test circuit for a high-speed test.

[Conventional technology]

Conventional test circuits for semiconductor integrated circuits are mainly circuits for increasing the failure detection rate of internal circuits like scan path circuits, etc. Ring oscillators with inverters connected in cascade are used as test circuits for high-speed testing. Alternatively, there is a circuit in which an output delay time is shortened by inserting a D-type flip-flop for retiming immediately before an output stage of a semiconductor integrated circuit so that a test can be easily performed by an LSI tester.

In the high-speed operation test using a ring oscillator, a result obtained by directly or dividing the oscillation frequency is measured, and the operation speed of an actual circuit on the same chip or the same wafer is estimated based on the frequency.

When actually measuring the operating speed of an LSI without measuring the oscillation frequency, use an LSI tester to input a test pattern that is strict in terms of circuit operation into the semiconductor integrated circuit under test, and compare the output with the expected value. It is done by doing.

In this case, a high-speed test can be performed to some extent by inserting a flip-flop for retiming immediately before the output of the semiconductor integrated circuit to shorten the output delay time.

[Problems to be solved by the invention]

In this conventional semiconductor integrated circuit, when a high-speed operation test using a ring oscillator is performed, a test is not directly performed on a location where the speed is severe in terms of the operation of the semiconductor integrated circuit. There is a problem that if there is no such information, it will not be an effective sorting means.

When an operation speed test is performed using an LSI tester, the LSI tester basically needs to have a test speed higher than the operation speed of the semiconductor integrated circuit to be tested.

In recent years, the operating speed of semiconductor integrated circuits has become faster.
Some CMOS-type semiconductor integrated circuits exceed tens of MHz, and LSI testers for this purpose are very expensive, and are required for maintenance such as test pattern generation and skew adjustment at the time of expected value comparison. It requires a lot of man-hours and is not realistic.

[Means for solving the problem]

The semiconductor integrated circuit of the present invention includes a test clock input, a toggle flip-flop driven by the clock, a test counter, and an output terminal for monitoring the output of the counter outside the semiconductor integrated circuit. A data output of a first D-type flip-flop and a second D-type flip-flop.
In a circuit having a configuration in which a gate circuit is inserted between the gate and a data input of a type flip-flop, the test clock is supplied to the first and second D-type flip-flops via a first switching circuit. The output of the toggle flip-flop is connected to the data input of the first D-type flip-flop via a second switching circuit, and the trigger input terminal of the test counter is connected to the output of the second D-type flip-flop. Is connected.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of a first embodiment of the present invention.

The test clock input 1 is connected via the input buffer 10 to the switching circuit 2 and the trigger input terminal T of the toggle flip-flop 3.

The switching circuit 1 has a clock input terminal 11 and an input buffer 2
, A normal operation clock and a test clock input through the first D-type flip-flop 5.
And the second D-type flip-flop 7.

The output of the toggle flip-flop 3 is connected to the data input of the first D-type flip-flop 5 via the switching circuit 4.

The path from the Q output of the first D-type flip-flop 5 to the data input of the second D-type flip-flop 7 via the gate circuit 6 is where the operation speed becomes a problem in circuit operation.

The Q output of the second D-type flip-flop 7 is connected to the internal circuit and is input to the trigger terminal T of the test counter 8.

The count result of the test counter 8 can be externally monitored using the output buffer 13 and the monitor terminal 9.

When testing a semiconductor integrated circuit having this test circuit,
First, a test pattern is applied from the LSI tester in a normal state, and the output of the first D-type flip-flop 5
The input value to the gate circuit 6 is set so as to propagate to the input of the second D-type flip-flop 7 through.

Next, the switching circuit 2 is set to a test state, and a test clock having a desired frequency is input. By monitoring the count output of the test counter 8 after inputting a predetermined number of test clocks, it can be determined whether the circuit under test can operate at a desired frequency.

FIG. 2 is a partial block diagram of a second embodiment of the present invention. Instead of the first D-type flip-flop 5, the gate circuit 6, and the second D-type flip-flop 7 shown in the first embodiment, first to (n + 1) -th D-type flip-flops as shown in FIG. Also in the case of the configuration composed of 71 and 61 of the gate circuit 1 to 62 of the gate circuit n, the operation speed can be measured by a test circuit similar to FIG.

〔The invention's effect〕

As described above, according to the present invention, a toggle flip-flop, a test clock terminal, a test counter, and a monitor terminal for counting the output are added to a normal semiconductor integrated circuit, so that the measurement can be performed in a frequency band where measurement by an LSI tester is not easy. A high-speed operation test of an operating semiconductor integrated circuit can be easily performed.

The AC input required at this time is only one test clock, so there is no need to adjust skew, etc. Also, the output of the test counter is kept as it is if no clock is input, so the expected value matching circuit is also fast. There is an advantage that no operation is required.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a partial block diagram of a second embodiment of the present invention. 1 ... Test clock input, 2 ... Switching circuit 1, 3 ...
... Toggle flip-flop, 4 ... Switching circuits 2, 5, ...
... First D-type flip-flop, 6... Gate circuit, 61... Gate circuit 1, 62... Gate circuit n, 7.
Second D-type flip-flop, 71... (N + 1)
D-type flip-flop, 8 …… Test counter,
9 monitor terminal, 10 input buffer 1, 11 clock input terminal, 12 input buffer 2, 13 output buffer.

Claims (1)

(57) [Claims] A clock input for testing, a toggle flip-flop driven by the clock, a counter for testing, and an output terminal for monitoring the output of the counter outside the semiconductor integrated circuit; In a circuit having a configuration in which a gate circuit is inserted between a data output of a first D-type flip-flop and a data input of a second D-type flip-flop, the test clock is supplied via a first switching circuit. Is supplied to the first and second D-type flip-flops, and the data input of the first D-type flip-flop is connected to the output of the toggle flip-flop via a second switching circuit. D
A semiconductor integrated circuit, wherein a trigger input terminal of the test counter is connected to an output of a type flip-flop.