JP2830244B2 - Tri-state buffer circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a tri-state buffer circuit, and more particularly to a tri-state buffer circuit used for a semiconductor integrated circuit.

[Conventional technology]

FIGS. 3 and 4 show examples of this type of conventional tristate buffer circuit. FIG. 3 shows a high active tristate buffer circuit, and FIG. 4 shows a low active tristate buffer circuit.

In a third view, the logic "0" from the input terminal T ₂ enable signal E is NAND gate (low level, hereinafter "L" hereinafter)
When applied to one input terminal of G _12, the output signal of the NAND gate G ₁₂ is (referred to as high-level, hereinafter "H") logic "1", P-type MOS transistor M ₂₁ is "gate H "Is applied and turned off. Since at the same time to the input terminal of the inverter I ₁ "L" is applied, the output signal of the inverter I ₁ becomes "H".

Since the one input terminal of NOR gate G ₂₂ "H" is supplied the output signal becomes "L", N-type MOS transistor M
_{In 12} , “L” is applied to the gate and the gate is turned off.

Since both of the MOS transistors M ₁₂ and M ₂₂ are turned off in response to the enable signal E of “L”, the output terminal T ₀ is in a high impedance state.

The highly active tri-state buffer circuit is
The state is enabled by the enable signal E of “H”.

When the “H” enable signal E and the “L” data signal A are applied to the input terminals T ₁ and T ₂ , the output signal of the NAND gate G ₁₂ becomes “H”, and the MOS transistor M ₂₁ is connected to the gate. It is turned off because “H” is applied.

At the same time the data signal A and the enable signal E of the NOR gate G ₂₂ "L" signal of the inverted "L" is applied by the inverter I _1, the output signal of the NOR gate G ₂₂ becomes "H", MOS transistor M ₂₂ is turned on since the "H" to the gate is applied.

MOS transistor M ₂₁ is turned off and the MOS transistor M ₂₂ is turned on, the output terminal T ₀ appears output signal Y of "L".

Conversely, when the “H” enable signal E and the “H” data signal A are applied to the input terminals T ₁ and T ₂ , the output signal of the NAND gate G ₁₂ becomes “L”, and the MOS transistor M ₂₁ The gate is turned on because “L” is applied to the gate.

At the same time the NOR gate G _22, since "H" data signal A and the enable signal E is a signal of inverted "L" is applied by the inverter I _1, the output signal of the NOR gate G ₂₂ becomes "L", since MOS transistor M ₂₂ is the "L" to the gate is applied is turned off.

Since MOS transistor M ₂₁ is turned on, the MOS transistor M ₂₂ is turned off, the output terminal T ₀ appears output signal Y "H".

Table 1 shows the operation of the high-active tristate buffer circuit of FIG. 3 described above in a truth table.

That is, when the "L" enable signal E is applied, the output signal Y enters a high impedance state regardless of the logic of the data signal A, and conversely, the "H" enable signal E
When There is applied, the logic of the data signal A appears at the output terminal T _0.

Next, Table 2 shows a truth table of the operation of the low-active transistor state buffer circuit shown in FIG.

In other words, when the "H" enable signal E is applied, the output signal Y enters a high impedance state regardless of the logic of the data signal A, and conversely, the "L" enable signal E
There the logic of the applied data signal A appears at the output terminal T _0.

The NAND gates G ₁₂ ,
G ₁₃ and NOR gates G ₂₂ and G ₂₃ are each composed of four MOS transistors, and inverters I ₁ and I ₂ are each composed of two MOS transistors. Therefore, the conventional tristate buffer circuit shown in FIGS. 3 and 4 is composed of 12 MOS transistors.

[Problems to be solved by the invention]

The conventional tri-state buffer circuit described above requires 12 MOS transistors each. Therefore, in a semiconductor integrated circuit using a large number of tri-state buffer circuits, the number of elements increases and the chip size increases. There is a disadvantage that it becomes larger.

An object of the present invention is to provide a tri-state buffer circuit capable of reducing the number of MOS transistors and reducing the chip size of a semiconductor integrated circuit.

[Means for solving the problem]

A tri-state buffer circuit according to the present invention is configured such that a data signal is input to a first input terminal and an enable signal is input to a second input terminal. When the enable signal is at a first level, the tri-state buffer circuit responds to the level of the data signal. A gate circuit for outputting a signal having a first level and a second level and outputting a signal having a second level when the enable signal is at the second level; and a drain connected to the source and the first power supply terminal. Is connected to an output terminal, and the output signal of the gate circuit is input to the gate, and this output signal is turned on when the output signal is at a first level, and turned off when the output signal is at a second level, and a first MOS transistor of one conductivity type; A second MOS transistor of a reverse conductivity type, which is connected to the output terminal of the drain and inputs the enable signal to the gate, and turns on when the enable signal is at a first level and turns off when the enable signal is at a second level. And a source connected to the second power supply terminal, a drain connected to the source of the second MOS transistor, and a gate supplied with an output signal of the gate circuit. When the output signal is at the first level, the output is off. And a third MOS transistor of the opposite conductivity type that is turned on when at the second level.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is a high active type tri-state buffer circuit in which a data signal A is input to a first input terminal, an enable signal E is input to a second input terminal, and the enable signal E is set to a high level (“H”). "), A signal of low level (" L ") and high level (" H ") is output according to the level of the data signal A. When the enable signal is low (" L "), a high level (" H ") is output. NAND gate G that outputs a signal
₁₁ , a source connected to the first power supply terminal (power supply voltage V _DD ), a drain connected to the output terminal T _0, and a gate connected to the NAND gate ₁₁
Input signal and this output signal is low level (“L”)
On time of the high level ( "H") and the first MOS transistor M ₁ of the P type which becomes off when, the enable signal E to input enable signal E to the gate connected to the drain output terminal T ₀ turned on when the high level ( "H"), the low level ( "L") when off the second MOS transistor M ₂ of N-type which becomes a source second power supply terminal (power supply voltage V _SS, ground potential ) and connected the drain of the second MOS transistor receives the output signal of the M ₂ source and connected to NAND gate GG ₁₁ to gate the output signal is at a low level ( "L", hereinafter simply referred to as "L") , The N-type third MOS transistor M _{3 which is} turned on at a high level (“H”, hereinafter simply referred to as “H”).
And a configuration having:

 Next, the operation of this embodiment will be described.

Enable signal E input from the terminal T ₂ "L" is a NAND gate
When applied to one input of G ₁₁ output signal of the NAND gate G ₁₁ become "H", MOS transistor M ₁ so the gate of the MOS transistor M _1, M ₃ is "H" is applied off, MOS transistor M ₃ is turned on.

At the same time, the “L” enable signal E is output from the MOS transistor M ₂
Since the applied gate MOS transistor M ₂ is turned off.

Since both the MOS transistors M ₁ and M ₂ are turned off in response to the enable signal E of “L”, the output terminal T ₀ is in a high impedance state.

Then the enable signal E at the "H" when the "L" data signal A is applied to the input terminal T ₂ and the input terminal T _1, respectively, NAND
The output signal of the gate G ₁₁ become "H", MOS transistor
Since “H” is applied to the gates of M ₁ and M _3, the MOS transistor M ₁ is turned off and the MOS transistor M ₃ is turned on.

At the same time, the enable signal E of “H” is output from the MOS transistor M ₂
Since the applied gate MOS transistor M ₂ is turned on.

MOS transistor M ₁ is turned off and the MOS transistor M _2, M ₃ is turned on, the output terminal T ₀ appears output signal Y of "L".

On the contrary, when the data signal A of the enable signal E "H" of the "H" is applied, the output signal of the NAND gate G ₁₁ goes to "L", the gate of the MOS transistor M _1, M ₃ is since "L" is applied, MOS transistor M ₁ is turned on, MOS transistor M ₃ are turned off.

At the same time, the enable signal E of “H” is output from the MOS transistor M ₂
MOS transistor M ₂ applied to the gate of the turned on. Since MOS transistor M ₁ is turned on, the MOS transistor M ₃ is turned off, the output terminal T ₀ appears output signal Y "H".

The operation of the high-active tristate buffer circuit according to the first embodiment described above is shown in a truth table as shown in Table 3.

In other words, when the "L" enable signal E is applied, the output signal Y enters a high impedance state regardless of the logic of the data signal A, and conversely, when the "H" enable signal E is applied, the output signal Y becomes high. logic appears at the output terminal T _0.

 FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

This embodiment is a tri-state buffer circuit of the low active, the gate circuit NOR gate G _21, a first MO
Conductivity type to N-type S transistor M _11, the second, the conductivity type of the third MOS transistor M _12, M ₁₃ and the P-type, the first power supply terminal V _SS side (low potential side, a ground terminal) In addition, the power supply terminal of FIG. 2 is on the _VDD side (high potential side).

If the operation of this embodiment is converted into a truth table, it is as shown in Table 4.

That is, when the "H" enable signal E is applied, the output signal Y enters a high impedance state regardless of the logic of the data signal A, and conversely, when the "H" enable signal E is applied, the output signal Y becomes high. logic appears at the output terminal T _0.

The number of MOS transistors in these embodiments is NAND
Since there are four gates G ₁₁ and NOR gates G ₂₁ , the total number is seven each.

Also, the second and third transistors M ₂ , M ₃ , M ₁₂ , M 2 connected in series between the output terminal T ₀ and the power supply terminal
_Assuming that the channel width of each of the transistors ₁₃ is doubled in order to maintain the driving capability of the conventional example, the number of MOS transistors is equivalent to nine. Since this is significantly reduced as compared with the conventional tristate buffer circuit, the chip size of the semiconductor integrated circuit including the tristate buffer circuit can be reduced.

〔The invention's effect〕

As described above, the present invention provides a MOS transistor which is turned on / off by an enable signal between an output terminal and a second power supply terminal.
With the structure in which the transistors are provided, the structure of the gate circuit is simplified, so that the total number of MOS transistors can be reduced, so that the chip size of the semiconductor integrated circuit can be reduced.

[Brief description of the drawings]

FIGS. 1 and 2 are circuit diagrams showing first and second embodiments of the present invention, respectively, and FIGS. 3 and 4 are first and second examples of a conventional tristate buffer circuit, respectively. It is a circuit diagram. G _{11 to} G ₁₃ …… NAND gate, G _{21 to} G ₂₃ …… NOR gate, I ₁ ,
I ₂ …… Inverter, M _{1 to} M ₃ , M _{11 to} M ₁₃ , M _{21 to} M ₂₄ … MOS
Transistor.

Claims (1)

(57) [Claims] 1. A data signal is input to a first input terminal and an enable signal is input to a second input terminal. When the enable signal is at a first level, a first level is provided according to the level of the data signal. A gate circuit for outputting a signal having a second level and outputting a signal having a second level when the enable signal is at the second level; a source connected to the first power supply terminal and a drain connected to the output terminal; A first MOS transistor of one conductivity type, which is connected to a gate and receives an output signal of the gate circuit and turns on when the output signal is at a first level and turns off when the output signal is at a second level; A second MOS transistor of an opposite conductivity type, which is connected to a terminal and is supplied with the enable signal to a gate and turned on when the enable signal is at a first level and turned off when the enable signal is at a second level; Power supply And the drain is connected to the source of the second MOS transistor, and the output signal of the gate circuit is input to the gate. The output is off when the output signal is at the first level and is on when the output signal is at the second level. A tri-state buffer circuit, comprising: a third MOS transistor of an opposite conductivity type.