JP2826717B2 - Method for manufacturing capacitor of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a high-integrated DRAM (dy).
natural random access memory
y) The present invention relates to a method for manufacturing a capacitor of a semiconductor device which is compatible with a high dielectric film capacitor required as a capacitor of the device.

[0002]

2. Description of the Related Art Conventionally, with the increasing integration of semiconductor devices, 1
Although 6Mbits and 64Mbits DRAMs are mass-produced, 256Mbits and 1Gbits DRAMs
Is still in development. That is, since the capacitance area of a unit cell is reduced in accordance with the high integration of the DRAM, studies for obtaining a desired capacitance in the reduced area are being actively conducted. Therefore, a high dielectric material (high dielectric constant) is required.
Research on forming a high dielectric thin film using a capacitor derivative film of (t material) has been progressing, and the substance of the high dielectric material is in the form of a complex oxide,
Mainly, BaSrTiO ₃ (BST), BaTiO ₃ , S
rTiO ₃ , PbZrO _{3 and the} like are used.

[0003] The form of such a composite oxide is 6
Since film deposition is performed at a high temperature of 00 to 700 ° C., it is a main issue to obtain an electrode material and an electrode structure that are compatible with the high temperature. Therefore, conventionally, polycrystalline silicon has been used as a material of the electrode. However, since the polycrystalline silicon is oxidized and diffused at the time of vapor deposition, a material that suppresses the oxidation to some extent should be used. Therefore, when using a high dielectric film for a capacitor derivative,
A diffusion barrier layer (diffusion barrier layer) for preventing the diffusion between the dielectric and the substrate by forming a multilayer structure of the electrode.
er), an electrode layer having conductivity by suppressing oxidation to some extent, and a connection plug for electrically connecting to the substrate.

That is, in a conventional method of manufacturing a capacitor of a semiconductor device, as shown in FIG. 2, an FET having a pair of insulated gate electrodes 2a and 2b on a semiconductor substrate 1 is used.
A transistor (not shown) is formed, an insulating layer 3 is formed on the gate electrodes 2a and 2b, and a connection hole is formed on the central substrate 1 of the insulating layer 3 by etching. A source or drain region 6 is formed,
A polycrystalline silicon plug 4 was formed in the connection hole on the upper surface of the source or drain region 6, and a capacitor 5 was formed on the upper surface of the polycrystalline silicon plug 4 and the insulating layer. In the structure and formation of the capacitor 5, a barrier layer 9 made of a conductive material such as Ta or TiN is first formed on a predetermined portion of the upper surface of the polycrystalline silicon plug 4 and the insulating layer 3. A lower electrode 7a was formed thereon, a dielectric film 8 of BaSrTiO ₃ was coated on both the upper surface of the lower electrode 7a and the side surfaces of the barrier layer 9, and an upper electrode 7b was formed on the dielectric film 8.

[0005]

However, the conventional method for manufacturing a capacitor of a semiconductor device has the following disadvantages. A dielectric film 8 on the upper surface and both side surfaces on which the lower electrode 7a and the barrier layer 9 are laminated.
When the dielectric film 8 is coated, filling and leaking occurs at the corners 10a and 10b of the laminating step, and an insulating material such as SiO ₂ is easily deposited on the filling and leaking portion. I was sorry. During the deposition of the dielectric film 8, both sidewalls of the barrier layer 9 are exposed, so that the high-temperature barrier layer 9 is oxidized to cause contact resistance, and the oxide on both sidewall surfaces of the barrier layer 9 causes the barrier layer 9 to be exposed. And the lower electrode 7a has reduced adhesiveness. The adhesion between the barrier layer 9 and the polycrystalline silicon plug 4 is reduced due to oxidation of the side wall surfaces of both the barrier layer 9 and the surface of the polycrystalline silicon plug 4 is oxidized.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device which can easily perform etching when forming a multilayer electrode and reduce the occurrence of misalignment due to a reduction in capacitor area. Things.

Another object of the present invention is to prevent the performance of the capacitor from being degraded due to the oxidation of the surface of the plug, and to prevent the electrode from cracking due to the volume expansion and stress caused by the oxidation of the barrier layer. An object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device.

According to a first aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of forming an insulating film on a semiconductor substrate, selectively etching the insulating film, and forming a connection hole in a predetermined portion of the insulating film. Forming a conductive plug in the connection hole, forming a barrier layer on the conductive plug in the connection hole, and forming a first metal layer on the barrier layer and the insulating film. Forming a mask pattern on the first metal layer so as to correspond to the connection holes, and etching the first metal layer with a BCl ₃ / Cl ₂ gas using the mask pattern as a mask. Forming a first electrode pattern; removing a mask pattern formed on the first electrode pattern; forming a dielectric layer over the entire surface of the semiconductor substrate including the mask pattern; Up Successively performing the step of forming a second electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of:
Depositing a polysilicon layer on the connection hole and the insulating film between the step of forming the connection hole and the step of forming the conductive plug in the connection hole; and etching back the polysilicon layer. And is done in addition.

According to a third aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of:
In the step of forming the barrier layer, a metal alloy of TiN, Ta, W, and Mo and a metal silicide thereof (Silicid) are used.
e) Use one of the above.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of:
The fourth metal layer is formed using one of Pt, Pd, Ru, RuO ₂ and an oxide having conductivity.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of:
The dielectric layer is formed of Ta ₂ O ₅ , BaSrTiO ₃ , S
This is performed using any one material selected from the group consisting of rTiO ₃ , BaTiO ₃ , PbZrO ₃ , PZT, and PLZT.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of:
The second electrode is made of any one of Pt, W, and TiN.

[0014]

Embodiments of the present invention will be described below. In a capacitor of a semiconductor device manufactured by the method according to the present invention, as shown in FIG. 1J, an insulating film 28 formed on a semiconductor substrate 20 and having a connection hole 29, and a TiN film of the insulating film. The plug 35, the plug 32 formed in the connection hole 29 of the TiN plug 35 and the insulating film 28 with a thickness smaller than the thickness of the insulating film 28, and the upper surface of the plug 32 in the connection hole 29 A first capacitor electrode 36 formed on the formed barrier layer 28, a dielectric layer 40 formed on the first capacitor electrode 36, and a second capacitor electrode 42 formed on the dielectric layer 40 And

In the method for manufacturing a capacitor of a semiconductor device according to the present invention, as shown in FIG. 1A, a gate electrode 22 having a predetermined shape and an n ⁺
Formed impurity diffusion (source / drain) regions 24 and 25 and a field oxide film 26 are formed, respectively. Then, on their gate electrode 22, ^{n +} -type impurity diffusion (source / drain) regions 24 and 25 and the field oxide film 26, as shown in FIG. 1 (B), the insulating thickness of 3000Å film 2
8 is deposited by a chemical vapor deposition method. Next, as shown in FIG. 1C, photo-etching is performed on a predetermined portion of the insulating film 28, and a capacitor storage node (capacitor) is formed.
A connection hole 29 in which a storage node is formed is formed. After that, a polycrystalline silicon layer 30 having a thickness of 2000 .ANG.
Is deposited by a low pressure chemical vapor deposition method.

Then, as shown in FIG. 1D, the polycrystalline silicon layer 30 is removed by etching back to a thickness of 3000 ° using Cl ₂ / O _2, and the insulating film in the connection hole 29 is removed. The plug 32 is about 1000 ° below the upper surface of the plug.
To form In this case, the plug 32 is formed of polycrystalline silicon. Next, as shown in FIG.
A TiN layer 34 serving as a barrier layer is deposited on the plug 32 and the first insulating film 28 to a thickness of 1500 °.
In this case, the TiN layer 34 can be replaced with any one of a metal alloy of Ta, W, and Mo and a metal silicide thereof.

Next, as shown in FIG.
The iN layer 34 is formed by RIE (Reac) using BCl ₃ / Cl _2.
1500 by the active ion etching method.
Etching is performed to a thickness of Å to form a TiN plug 23 on the plug 32 in the connection hole 29. Then, FIG.
As shown in (G), a capacitor first electrode 36 having a thickness of 2000 Å is deposited on the TiN plug 35 and the insulating film 28 by a sputtering method.
The first electrode 36 uses Pt, and instead of Pt, Pt is used.
Any one of d, Ru, RuO ₂ and an oxide having conductivity can be used.

Next, as shown in FIG. 1 (H), a photosensitive film 38 for a mask is formed on the upper surface of the capacitor first electrode 36, and the Pt capacitor first electrode 36 is photo-etched to form a capacitor. A region where a storage node is to be formed is formed, and is etched by RIE using BCl ₃ / Cl ₂ to form a capacitor first electrode 36 having a predetermined shape.
To form Thereafter, as shown in FIG. 1I, the photosensitive film 38 on the capacitor first electrode 36 is made of H ₂ SO ₄
Dip in / H ₂ O ₂ wet solution to remove completely.

Next, as shown in FIG. 1 (J), 500 μm is formed on the capacitor first electrode 36 and the insulating film 28.
A dielectric layer 40 having a thickness of Å is deposited by a chemical vapor deposition method. In this case, the dielectric layer 40 has BaSrTiO ₃ , SrTiO ₃ , BaTiO ₃ having a dielectric constant of 3 or more,
PbZrO _3, PZT, and one material selected from the group consisting of PLZT used. Thereafter, a capacitor second electrode 42 of Pt is deposited on the dielectric layer 40. In this case, instead of Pt, W or TiN is used.
Can also be used.

In the method of manufacturing a capacitor of a semiconductor device according to the present invention manufactured as described above, the first electrode of the capacitor can be easily formed by etching the thin film of Pt. The process is performed very easily. In addition, even if a mis-alignment occurs between the connection of the node and the pattern of the node, the single crystal silicon plug is not exposed, and the Ti of the barrier layer is not exposed.
Since the N plug is exposed, the electrode is prevented from being broken due to the oxidation of the barrier layer, and the reliability of the capacitor is improved.

[0021]

As described above, in the method of manufacturing a capacitor of a semiconductor device according to the present invention, a TiN plug of a barrier layer is formed in a connection hole of an insulating film, and a TN plug is formed.
Since the first electrode of the capacitor is formed on the iN plug, the problem of oxidation of the barrier layer, which occurs during the conventional deposition of a dielectric film, is solved, and the electrode is prevented from cracking due to stress. This has the effect of improving the performance.

[Brief description of the drawings]

1 (A) to 1 (J) are manufacturing process diagrams of a capacitor of a semiconductor device according to the present invention.

FIG. 2 is a longitudinal sectional view showing a structure of a capacitor of a conventional semiconductor device.

[Explanation of symbols]

 1, 20: semiconductor substrate 2a, 2b, 22: gate electrode 3: insulating layer 4: polycrystalline silicon plug 5: capacitor 6: source or drain region 7a: lower electrode 7b: upper electrode 8: dielectric film 9: barrier layer 24 , 25: impurity diffusion (source / drain) region 26: field oxide film 28: insulating film 30: polycrystalline silicon layer 32: plug 34: barrier layer 35: TiN plug 36: capacitor first electrode 38: photosensitive film 40: dielectric Body layer 42: Capacitor second electrode

Continuation of the front page (56) References JP-A-8-335680 (JP, A) JP-A-2-83978 (JP, A) JP-A-3-127826 (JP, A) (58) Fields investigated (Int) .Cl. ⁶ , DB name) H01L 27/108 H01L 21/28 301 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (6)

(57) [Claims] 1. A method of manufacturing a capacitor of a semiconductor device, comprising: forming an insulating film on a semiconductor substrate; selectively etching the insulating film; and forming a connection hole in a predetermined portion of the insulating film. Forming a conductive plug in the connection hole, forming a barrier layer on the conductive plug in the connection hole, forming a first metal layer on the barrier layer and the insulating film. Forming, forming a mask pattern on the first metal layer corresponding to the connection hole, using the mask pattern as a mask, and forming the first metal layer on a BC.
forming a first electrode pattern by etching with l ₃ / Cl ₂ gas; removing the mask pattern formed on the first electrode pattern; and entire surface of the semiconductor substrate including the mask pattern Forming a second electrode on the dielectric layer, and sequentially forming a second electrode on the dielectric layer. 2. A step of depositing a polycrystalline silicon layer on the connection hole and the insulating film between the step of forming the connection hole and the step of forming a conductive plug in the connection hole; Etching back the silicon layer;
2. The method for manufacturing a capacitor of a semiconductor device according to claim 1, further comprising: 3. The step of forming the barrier layer, the step of forming
2. The method according to claim 1, wherein one of a metal alloy of N, Ta, W, and Mo and a metal silicide thereof is used. 4. The method according to claim 1, wherein the first metal layer comprises Pt, Pd, Ru,
The method for manufacturing a capacitor of a semiconductor device according to claim 1, wherein the capacitor is formed using one of RuO ₂ and an oxide having conductivity. 5. The method according to claim 1, wherein the dielectric layer is formed of Ta ₂ O ₅ , B
aSrTiO ₃ , SrTiO ₃ , BaTiO ₃ , PbZ
The method of claim 1, wherein the method is performed using any one material selected from the group consisting of rO ₃ , PZT, and PLZT. 6. The method according to claim 6, wherein the second electrode comprises Pt, W, and TiN.
The method for manufacturing a capacitor of a semiconductor device according to claim 1, wherein the capacitor is manufactured by any one of the following.