JP2813103B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interface between chips on a board on which a plurality of LSI chips are mounted,
Specifically, a high frequency clock (for example, 50 MHz or more)
An input circuit applicable to both data (hereinafter referred to as high-speed data) and data (hereinafter referred to as low-speed data) operating with a low-frequency clock (for example, 50 MHz or lower), and a data transfer circuit including the input circuit; Or C
TT (center tapped termination) and GTL (Gunning
The present invention relates to a semiconductor integrated circuit having an output buffer that outputs a small amplitude signal of a transceiver logic level.

Conventionally, the input / output level of an LSI is generally TTL or CMOS, but if the input / output level is kept at this level, the influence of signal reflection and the influence of crosstalk will occur when the transfer data frequency exceeds 50 MHz. As a result, waveform distortion occurs due to ringing or the like, and normal data transfer becomes difficult. Therefore, attention has been paid to small-amplitude input / output interfaces (CTT, GTL) in which the signal level is suppressed to 1 V or less. According to this, high-speed data transfer of 100 MHz far exceeding 50 MHz or higher can be realized.

[0003]

BACKGROUND OF THE INVENTION first conventional example Figure 29 is a block diagram of a conventional data transfer circuit. Here, although not particularly limited, an example of a semiconductor memory is shown. In this figure, reference numeral 1 denotes an LSI chip for outputting data (hereinafter, an output chip), and reference numeral 2 denotes an LSI chip for inputting data (hereinafter, an input chip). Data D generated inside the output chip 1 includes an inverter gate 11, a NOR gate 12, an inverter gate 13, and a transistor 1
4 and the non-inverting path B including the NOR gate 15, the inverter gate 16, and the transistor 17 are transmitted to the output circuit 18. Output circuit 18
Is an inverting drive unit 2 including transistors 19 to 22
3, a non-inverting drive unit 28 including transistors 24 to 27, and an output unit 31 including two transistors 29 and 30 that operate by push-pull in response to the output of each drive unit. Is "1" or H
In the case of the logic, the transistor 29 of the output unit 31 is opened to drive the data line 32 with the potential of V _CC (for example, +3.3 V). Open transistor 30 of
V _SS potential (e.g. + 0V) is for driving the data line 32 at.

When the HiZ control signal is set to L logic, both transistors 29 and 30 of the output unit 31 can be turned off regardless of the logic of the data D, and the output can be opened to be in a high impedance state. it can. This is a function required when the data line 32 is used as a bus line. The potential change of the data line 32, that is, the transfer data Dt is taken into the input chip 2 from the input terminal Pi, and when a predetermined control signal (for example, a signal generated from the write enable signal WE) is L logic, the NOR gate 33 and the buffer circuit 34 and transmitted to the latch circuit 35. The buffer circuit 34 is turned on when a CMOS circuit including transistors 36 and 37 and a predetermined control signal (for example, a signal generated from the row address strobe signal RAS) is at L logic, and turned off when the signal is at H logic. Two transistors 38, 39,
While the two transistors 38 and 39 are off, the input terminal Pi and the latch circuit 35 are disconnected from each other to prevent unintentional inversion of the latch due to noise or the like.

The latch circuit 35 has four transistors 4
A flip-flop constituted by connecting the first to fourth crosses, and two switching transistors 45 and 46
And one inverter gate 47. When H logic is input, L logic is set (output = L), and when L logic is input, H logic is set (output = H). The output of the latch circuit 35 is transmitted to each unit in the chip via, for example, inverter gates 48 and 49.

In such a configuration, the transfer data Dt
, That is, the input / output level of the LSI chip is TTL (assuming that V _CC = + 3.3 V and V _SS = 0 V), and the upper limit frequency is about 50 MHz. 50M
In order to enable high-speed transfer exceeding Hz, for example, a GTL method in which the output side is open drain and V _OH is pulled up by a resistor may be adopted. Further, the small amplitude signal is supplied to the internal level of the input chip 2 (for example, TTL or CMO).
For high-speed conversion to S), a differential amplifier circuit may be provided at the first input stage of the chip 2.

Second Conventional Example Both CTT and GTL terminate a signal line to a voltage lower than a power supply voltage, and a driving current of an output buffer flowing through the terminating resistor causes a signal amplitude of 1 V or less to be applied to both ends of the resistor. By adjusting the value of the terminating resistor to the characteristic impedance of the signal line, signal reflection is prevented and high-speed data transfer is enabled. [Example of CTT Interface] In FIG. 30, 101 and 102 are chips,
These chips have transceivers of the same configuration. The configuration of a transceiver will be described with the chip 102 as a representative. 103 is an input buffer including a differential amplifier 104 and an inverter gate 105, 106 is inverter gates 107 to 110, NAND gates 111 and 112, NOR gates 113 and 114, and a two-stage CMOS. Output unit 11
5, an output buffer including 116. Front-stage CMOS
The unit 115 is a P-channel MOS transistor (hereinafter, referred to as a second PMOS transistor) 115a between the high-potential-side power supply V _CC (for example, +3 V) and the low-potential-side power supply V _SS (0 V).
And an N-channel MOS transistor (hereinafter referred to as a second NM
OS transistor 115b is push-pull connected, and similarly, CMOS transistor 116 at the subsequent stage also has a P-channel MOS transistor (hereinafter, first PMOS transistor) 116a and an N-channel MOS transistor (hereinafter, first PMOS transistor) between V _CC and V _SS . One NMOS transistor) 116b is push-pull connected. 117 is a signal line 118
Input and output terminals connected to one end of the terminating resistor 119 and 120, 121 the other end a pull-up power supply _{V TT (V TT = V CC} / 2 termination resistors 119 and 120; the V _CC + 3V to the +
Reference voltage terminal connected to 1.5 V), 122 is an arbitrary internal circuit that generates a signal (denoted by A for convenience) to be output to the outside of the chip via the output buffer 106, and 123 is the output from the input buffer 103 TSC is a tri-state control signal (a tri-state control mode when it is at the H level).

In such a configuration, the level of the signal B is determined by the potential relationship between the inverting input (-) and the non-inverting input (+) of the differential amplifier 104. That is, the inverting input (-)
Is V _TT = + 1.5 V, the signal B goes low when the potential of the non-inverting input (+) exceeds +1.5 V, and goes high when the potential is +1.5 V or less. If the signal A is input at the H level while the signal B is at the H level (the signal TSC is at the L level), the inverter gate 1
09, the output of the NAND gate 112, the NOR gate 114, and the output of the inverter gate 110 all become L level. Therefore, the PMOS transistors 115a and 116a of the two-stage CMOS sections 115 and 116 are turned on, the NMOS transistors 115b and 116b are turned off, and V _CC
→ PMOS transistor 115a (116a) → current flows + I _L in the direction of the terminating resistor 119,120 → V _TT.

Therefore, the potential of the non-inverting input (+) of the differential amplifier 104 is higher than the potential of the inverting input (-) by I _L × R.
_The signal B changes to the L level when _L ( _RL is the parallel combined value of the terminating resistors 119 and 120; for example, 25Ω). On the other hand, when the signal B is at the L level, the signal A
Is input at the L level (however, the signal TSC is at the L level), the inverter gate 109, the NAND gate 112,
The outputs of the NOR gate 114 and the inverter gate 110 all become H level. Therefore, the two-stage CMOS unit 1
15, 116 PMOS transistors 115a, 116
a is off, the NMOS transistors 115b and 116
b is turned on and V _TT → NMOS transistor 1
15b (116b) → V _SS direction to the current -I _L of flows.

Therefore, the potential of the non-inverting input (+) of the differential amplifier 104 is higher than the potential of the inverting input (−) by I _L × R.
_The signal B changes to the H level at the time when it becomes “low” by _L. Here, the potential of the input / output terminal 117 is
Since the signal B changes along a time constant curve determined by a capacitance of 8 or the like, the signal B does not change unless a time corresponding to the time constant elapses after the level of the signal A transitions.

Therefore, when the signal A transitions from L to H, the two Ps are not changed until the signal B changes to the L level.
MOS transistor 115a, but (in other words a low resistance) through 116a drive current + I _L is flown, when the signal B changes to the L level, only through the first PMOS transistor 116a (a high resistance in other words) the drive current + I _L Is shed. This is the same when the signal A transitions from H to L, and until the signal B changes to the H level, the two NMOS transistors 115 b and 116 b
While b through the driving current -I _L is passed through, the signal B changes to H level first NMOS transistor 116b
Drive current -I _L is flowed through only.

For this reason, a large driving current can flow in the first half of the output transition period, and a small driving current can flow in the second half of the output transition period, whereby the transition of the output signal can be hastened, and ringing and overshoot of the output signal can be achieved. Can be avoided. When the tristate control signal TSC is set to the H level, the outputs of the inverter gate 109 and the NAND gate 112 are fixed at the H level, and the outputs of the NOR gate 114 and the inverter gate 110 are fixed at the L level regardless of the state of the signals A and B. And four MOSs of two-stage CMOS units 115 and 116
Transistors 115a, 115b, 116a, 116b
Can be all turned off. [Example of CTT / GTL interface] FIG.
This is an example of a chip on which a transceiver for both TT and GTL is mounted. Note that the same reference numerals are given to circuit elements common to FIG. This transceiver operates with the CTT interface when the signal GTL (bar) is set at H level, and operates with the GTL interface when the signal GTL (bar) is set at L level.

When the signal GTL is set to H level (CTT mode), the AND gates 130 and 131 and the NOR gate 13
2 and the output of the inverter gate 133 have the opposite logic to the signal A, so that when the signal A is at the H level, the PMOS transistors 115a and 116a are in the on state and the signal A is at the L level.
At the time of level, the NMOS transistors 115b and 11
6b is turned on, and the input / output terminal 117 is driven at V _CC or V _SS . When the logic of the input / output terminal 117 is determined to be H level or L level, the differential amplifier circuit 1
04, inverter gate 134 and NOR gate 135
, The logic of the signal B from the input buffer 136 becomes opposite to the logic of the input / output terminal 117, the output logic of the AND gate 131 and the NOR gate 132 of the output buffer 137 is inverted, and the second PMOS transistor 115a or the second The NMOS transistor 115b is turned off.

On the other hand, when the signal GTL is set to L level (GTL mode), the NOR gate 135 of the input buffer 136 is set.
(Ie, signal B) is fixed at L level, and AND gates 130 and 131 of output buffer 137 are output.
Is fixed at the H level, only the NMOS transistors 115b and 116b are turned on / off according to the state of the signal A, and the output buffer 137 operates with an open drain.

Note that the NMOS transistor 138 and the resistor 139 added to the inverter gate 133 of the output buffer 137 are connected to the first NMO in the GTL mode.
This is for delaying the cutoff of the S-transistor 116b to avoid a sudden snap-off of the output signal.

[0016]

First Problem In the first conventional example (FIG. 29), a pull-up resistor is connected to the data line 32, and a differential amplifier circuit is provided at the first input stage of the chip 2. 50MHZ
Although effective for realizing high-speed data transfer exceeding z, there is a problem that it cannot be applied to applications where power consumption performance is more important than high-speed transfer.

For example, when a notebook personal computer or EWS is used on a battery, the clock speed of the CPU is reduced (ie, the frequency of the transfer data is reduced).
In order to extend the life of the battery, the above measures waste power consumed by the pull-up resistor and power consumed by the differential amplifier, and the number of pull-up resistors and differential amplifiers reduces the number of transfer data. Since it is proportional to the number of bits, a power loss that cannot be ignored as a whole occurs.

Further, in the first conventional example, since the transfer data is inputted to the NOR (NOR) gate 33, the NOR for judging the high / low of the input voltage is provided.
There is a problem that the "threshold" of the gate fluctuates due to the influence of manufacturing conditions or fluctuates due to the rise of the ground potential due to the current during operation (see the configuration diagram of the NOR gate 33 shown in FIG. 32). ).

Second Problem In the second conventional example (FIG. 30 or 31), the CTT
And a signal interface of a small amplitude (several hundred mV) such as GTL or GTL, but a signal interface of a large amplitude exceeding 1 V (for example, CMOS or TT)
When applied to L), there is a problem that a large distortion is generated in the output signal and a transition of the output signal is delayed.

The terminating resistor 11 shown in FIG.
By removing the components 9 and 120, the logic amplitude on the signal line 118 can be made almost full of the power supply width and can be used for a large-amplitude signal interface. First PMOS transistor 116a and first NMO dominating CTT or GTL level
Internal resistance of S transistor 116b (ON resistance R _ON )
Is, if the logic amplitude on the signal line 118 is 0.4V,
It can be obtained from the following equation (1).

[0021] 0.4 / (1.5-0.4) = 25 / R ON ...... (1) where 1.5 of V _TT voltage (V _CC / 2), 25 terminating resistor 119 and 120 Is a parallel composite value of From the above equation (1), R _ON is 68.75 [Ω]. To obtain this internal resistance, the size of the first PMOS transistor 116a and the first NMOS transistor 116b is set to “gate length L
= 1 μm, gate width W = 100 μm ”. However, this size depends on the size of a general CMOS output transistor (for example, L = 100 μm, W
= 1000 μm), so that the CMOS
The driving power is clearly insufficient for the level or TTL level output transistor.

Therefore, due to the shortage of the driving force, for example, not only can the reflected wave due to the inductance component of the signal line be suppressed to eliminate the distortion of the output signal, but also a large capacitive load (100
(Approximately [PF]), it is not possible to quickly charge / discharge, so that the change of the output signal becomes slow and the transition time is prolonged.

A first object of the present invention is to provide an input circuit which can be applied to both high-speed transfer (emphasis on transfer speed) and low-speed transfer (emphasis on power consumption) in view of the above first problem. Another object of the present invention is to provide a semiconductor integrated circuit. A second object of the present invention is to solve the above-mentioned second problem by connecting two sets of output transistors having optimized internal resistance to a signal interface (CTT or GTL) of a small amplitude level and a large-amplitude signal interface. It is an object of the present invention to provide a semiconductor integrated circuit that can exhibit performance suitable for each mode and has excellent compatibility (compatibility) by properly using a signal interface (CMOS or TTL).

[0024]

In order to achieve the first object, the semiconductor integrated circuit according to the first aspect of the present invention has a first power supply line and a second power supply line. Provided in the first
Frequency or a second frequency lower than the first frequency
A differential circuit for determining a logic level of an input signal having
A first power line provided between the first power supply line and the differential circuit.
Switch means, between the second power supply line and the differential circuit
A second switch means provided in the
When at the second frequency, the logic level of the input signal is
In response, the first switch means or the second switch
And control means for making one of the switch means conductive . The semiconductor integrated circuit according to claim 2, wherein, in the semiconductor integrated circuit according to claim 1, wherein the first and second
The second switch means is a transistor, and the control means
Includes a resistance element having a value larger than the impedance matching load resistance value of the bus line outside the semiconductor integrated circuit.
The input signal is transmitted to the transformer via the resistance element.
It is characterized in that it is coupled to the gate of the transistor .

According to a third aspect of the present invention, in order to achieve the first object, an input signal changing at a first frequency or a second frequency lower than the first frequency is applied to one control electrode. And a pair of differential transistors for applying a reference voltage corresponding to a substantially intermediate value of the logical amplitude of the input signal to the other control electrode, between the pair of differential transistors and the low potential side power supply. An intervening low-potential-side transistor, a high-potential-side transistor interposed between the differential transistor and the high-potential-side power supply, and, when the frequency of the input signal is near the first frequency, regardless of the logic state of said generating a control voltage for both the low-side transistor and the high side transistor in the oN state, the field frequency of the input signal is close to the second frequency The, characterized by comprising a control voltage generating means for generating a control voltage to one of the on state of the low side transistor or the high side transistor in accordance with the logic state of the input signal. Claim 4
The semiconductor integrated circuit according includes a comparator circuit for detecting the level of the voltage of the input signal to a reference and becomes the voltage, the first
Between the power supply and the comparator circuit and between the second power supply and the
First and second transistors provided between the first and second transistors , respectively, provided between the first and second transistors;
The input signal is coupled to a control electrode of the
, The first and second transistors are both conductive.
And the second input signal is lower than the first frequency.
, In response to the logic level of the input signal
Selectively one of the first and second transistors
And an input circuit including control means for conducting .

The semiconductor integrated circuit according to claim 5, wherein, for the above first object achieved, the input signal having a second logic amplitude greater than the first logic amplitude or the first logic amplitude <br / > is applied to one control electrode of, applying of the logical amplitude control electrode reference voltage corresponding to a substantially intermediate value the other of said input signal
A pair of differential transistors, a low-potential-side transistor interposed between the pair of transistors and the low-potential-side power supply, and a high-potential side interposed between the pair of differential transistors and the high-potential-side power supply. A transistor and the high potential side transistor
Coupled to control electrode of transistor and low side transistor
Wherein the input signal has the first logic amplitude,
Both high-potential side transistor and low-potential side transistor
In a conductive state, and when the input signal has the second logic amplitude,
The high potential side in response to the logic level of the input signal.
And one of the low-potential side transistors is selectively turned on.
And control means for causing, characterized Rukoto to have a.

According to a sixth aspect of the present invention, in the signal transfer circuit according to the first aspect,
A transmission line for transmitting a signal, and a first line when a logical amplitude of the signal is a first amplitude.
A voltage source for generating a voltage corresponding to a substantially intermediate value of the amplitude of
And the terminating resistor connected through a predetermined switching means between the transmission line and the voltage source, the frequency of the signal first
Of the signal or the logical amplitude of the signal is defined as the first amplitude .
In the first mode, the switching means is turned on , and the frequency of the signal is set to a second frequency lower than the first frequency or the logical amplitude of the signal is set to a second frequency higher than the first amplitude. In the second mode with a logical amplitude of 2,
On / off control means for turning off the switching means.

Part 2 (corresponding to claims 7 to 20) In the semiconductor integrated circuit according to claim 7, in order to achieve the second object, as shown in FIG.
The first PM connected in series between _CC and the low-potential-side power supply V _SS
The OS transistor 230a and the first NMOS transistor 230b, and the second PMOS transistor 231a and the second NMOS transistor 231 similarly connected in series between the high-potential power supply V _CC and the low-potential power supply V _SS
b, and the four transistors 230 a, 230 b, 231 a, according to the signal logic from the chip internal circuit 232.
On / off control means 233 for selectively turning on / off the first PMOS transistor 231b.
0a and the connection point P ₂₀₀ between the first NMOS transistor 230b and the connection point P between the second PMOS transistor 231a and the second NMOS transistor 231b.
₂₀₁ are connected to the signal line 234, and the mode designation signal CMO is applied to the semiconductor integrated circuit that drives the signal line 234 by the selective on / off operation of the four transistors 230a, 230b, 231a, and 231b.
S is the signal line 234 and when viewing the first transfer mode used by connecting a terminating resistor 235 between the predetermined constant voltage V _TT, the first PMOS transistor 230a or the first The NMOS transistor 230b controls the signal line 234 to be driven, while the mode designation signal CMOS outputs the signal line 23.
4 is not connected to the terminating resistor 235, when the second transfer mode is displayed, the control is performed such that the signal line 234 is driven by the second PMOS transistor 231a or the second NMOS transistor 231b. A mode control means 236 for performing the operation is provided. The semiconductor integrated circuit according to claim 8 is the semiconductor integrated circuit according to claim 7, wherein the mode control means 236
Means that when the mode designation signal CMOS indicates the second transfer mode, the first PMOS transistor 23
0a and the second PMOS transistor 231a or the first NMOS transistor 230b and the second NMOS transistor 231b are controlled to drive the signal line 234. According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the seventh aspect, the potential of the reference voltage terminal 607 of the chip is compared with a predetermined constant voltage (V _CTT or V _GTL ) and the result of the comparison is determined. 601 or 602 for generating the mode designation signal in a logic state, and switch means 603 or 604 capable of cutting off the power supply current of the comparator, and the potential of the reference voltage terminal of the chip is a predetermined high potential or open state. Wherein the switch means is turned off when the switch is in the position. The semiconductor integrated circuit according to claim 10 is the semiconductor integrated circuit according to claim 7,
When the mode designating signal indicates the first transfer mode, the potential of the reference terminal of the chip at that time is used as a reference voltage of the input buffer circuit, while the mode designating signal indicates the second transfer mode. Is displayed, an intermediate potential of the power supply voltage is used as a reference voltage of the input buffer circuit. In the semiconductor integrated circuit according to the eleventh aspect, in the semiconductor integrated circuit according to the seventh aspect, a third NMOS transistor is connected in parallel with the first NMOS transistor, and a mode designation signal indicates the first transfer mode. And the first NMO
When the S transistor is turned on, the third NMOS transistor is turned on at the same time. 13. The semiconductor integrated circuit according to claim 12, wherein the input circuit determines a logic level of the input signal based on a reference voltage, and a mode designation signal based on a voltage value of a reference voltage terminal. A mode determination circuit that generates
Means for responding to the mode designation signal, selecting one of a voltage applied to the reference voltage terminal and an internally generated internal reference voltage, and supplying the selected voltage to the input circuit as the reference voltage. , Is provided. According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit of the first aspect, an amplitude of the input signal having the first frequency is smaller than an amplitude of the input signal having the second frequency. And The semiconductor integrated circuit according to claim 14, wherein in the semiconductor integrated circuit according to claim 12, the input circuit, when the mode determination circuit detects that no voltage is applied to the reference voltage terminal, Receiving the internal reference voltage as a reference voltage and receiving the voltage applied to the reference voltage terminal as the reference voltage when the mode determination circuit detects that a voltage is applied to the reference voltage terminal. It is characterized by the following. The semiconductor integrated circuit according to claim 15,
13. The semiconductor integrated circuit according to claim 12, further comprising an output circuit for switching a driving force based on the mode designation signal. In order to achieve the second object, the semiconductor integrated circuit according to the present invention provides an input circuit for determining a logic level of an input signal based on a reference voltage, and a mode designating signal based on a voltage value of a reference voltage terminal. A mode determining circuit for generating, a voltage generating circuit for generating an internal reference voltage, and selecting one of the external reference voltage applied to the reference voltage terminal and the internal reference voltage in response to the mode designating signal. A switching circuit that supplies the input voltage to the input circuit as the reference voltage, and an output circuit that switches a driving force based on the mode designation signal. 18. The semiconductor integrated circuit according to claim 17, wherein the mode determination circuit is configured to determine a voltage value of the external reference voltage, and the external reference voltage is provided to the reference voltage terminal. When the reference voltage terminal is open, the power supply control switch means cuts off the power supply voltage to the comparator when the reference voltage terminal is open. I do. A semiconductor integrated circuit according to claim 18 is the semiconductor integrated circuit according to claim 7, wherein the first PMOS transistor and the first N
The on-resistance of the MOS transistor is set based on the signal amplitude on the signal line in the first transfer mode and the value of the terminating resistance, and the on-resistance of the second PMOS transistor and the second NMOS transistor is set to the above-mentioned value. The setting is based on the signal amplitude on the signal line in the second transfer mode. 20. A semiconductor integrated circuit according to claim 19, wherein the first CMOS is connected in parallel with each other.
An output buffer circuit and a second CMOS output buffer circuit, control means for controlling the first CMOS output buffer circuit and the second CMOS output buffer circuit in response to an operation mode signal, and the first CMOS output buffer In a semiconductor integrated circuit having an output of a circuit and a signal line connected to an output of the second CMOS output buffer circuit, the operation mode signal connects a terminating resistor between the signal line and a predetermined constant voltage. When the first transfer mode is used, the control means applies a control signal to the first CMOS output buffer circuit to drive the signal line, and the operation mode signal causes the signal line to When the second transfer mode is used without connecting to the terminating resistor,
The control means is configured to apply a control signal to the second CMOS output buffer circuit to drive the signal line. 20. The semiconductor integrated circuit according to claim 20, wherein the driving power of the first CMOS output buffer circuit is the second CMOS output buffer circuit.
Is smaller than the driving power of the CMOS output buffer circuit.

[0029]

[Action] In the 1 invention, the frequency of the input signal when the first frequency or the amplitude is at the first logic amplitude, both the low potential side transistor and the high potential side transistor is always turned on, the pair The differential amplification operation by the differential transistor is allowed. Further, the frequency of the input signal is a second frequency (however, lower than the first frequency) or the amplitude thereof is a second logical amplitude (however, larger than the first logical amplitude).
, One of the low-potential-side transistor and the high-potential-side transistor is turned on in accordance with the logic state of the input signal, so that the differential amplification operation by the pair of differential transistors is inhibited and The input signal is taken into the chip through the low-potential side transistor or the high-potential side transistor without being amplified.

Therefore, it is possible to provide an input circuit applicable to both the high-speed transfer mode and the low-power mode (low-speed, high-amplitude data transfer mode). In the signal transfer circuit of the present invention, the termination resistor is connected when the high-speed transfer mode is required, and the termination resistor is disconnected when the low-power mode is required, so that power loss of the termination resistor in the low-power mode is avoided. it can.

Further, in the present invention, the same chip can be used for high-speed transfer only or for low-power use. This is simply the difference between using and not using a terminating resistor. From the manufacturer's point of view, there is no need to make different types of chips for high-speed and low-power use, so chips can be supplied at low cost. become. In addition, since the same component (semiconductor integrated circuit to which the present invention is applied) can be used for a high-speed or low-power application depending on the intended use, the user has the advantage of reducing the number of components in stock. That is, not only is it possible to electrically connect / disconnect the terminating resistor,
There is a significant effect of contributing to cost reduction of parts.

[0032] In Part 2 Fig. 2, R _{ON (230a)} is the on-resistance of the first PMOS transistor 230a, R _{ON (230b)} the first NMO
The ON resistance of the S transistor 230b, R _{ON (231a )} is the _ON resistance of the second PMOS transistor 231a, R _{ON
ON (231b)} is the ON resistance of the second NMOS transistor 231b, and R _L is the termination resistance 235. R _{ON (2 30a)} and R _{ON (230b)} the first PMOS transistor 230
a and the size of the first NMOS transistor 230b are L
= 1 μm and W = 200 μm, it is approximately 70 [Ω], and R _{ON (231a)} and R _{ON (231b)} are the second P
The size of the MOS transistor 231a and the second NMOS transistor 231b is L = 1 μm and W = 1000 μm
This is about 15 [Ω].

Now, when using in the signal transfer mode of the minute amplitude (first transfer mode), the terminal voltage _{VTT is set} to 1.5.
Assuming that V and R _L are 25Ω, from the above equation (1), R
By connecting signal line 234 to V _CC or V _SS via _{ON (230a)} or R _{ON (230b)} , signal line 234
The target signal amplitude (for example, 0.
4V) is obtained.

On the other hand, when used in the large-amplitude signal transfer mode (second transfer mode), the signal line is connected via R _{ON (231a)} or R _{ON (231b),} which is _{almost the} same as a general CMOS output transistor. By connecting 234 to V _CC or V _SS , a sufficient driving force is secured and the target signal amplitude (for example, approximately 3 V) of the transfer mode on the signal line 234 is obtained.
Is obtained.

In the second transfer mode, R
_It is desirable to use _{ON (230a)} and R _{ON (231a )} in parallel, and R _{ON ( 230b)} and R _{ON (231b)} in parallel. This is because the internal resistance can be further reduced and the driving force can be further increased.

[0036]

【Example】

Embodiments according to the first to sixth and thirteenth aspects of the present invention FIGS. 3 to 15 are views showing an embodiment of an input circuit and a data transfer circuit including the input circuit according to the present invention. As shown in FIG. 3, the input circuit according to this embodiment includes a differential amplifier (AMP) 360 that amplifies and outputs an input signal V _IN.
And switch elements (SW ₁ , SW ₂ ) 361, 362 inserted in the power supply path of the differential amplifying section 360. It is controlled according to the frequency or amplitude of _IN .

FIG. 4 is an overall configuration diagram of the input circuit including the control circuits 363 and 364. The differential amplifier 360 includes a transistor Q ₃₀₁ receiving the input signal V _IN at its gate, a high-potential power supply V _CC (+3.3 V) and a low-potential power supply V _SS (0 V).
A transistor Q ₃₀₂ receiving at its gate a reference voltage V _REF having a substantially intermediate potential (+1.65 V) of a pair of differential transistors Q ₃₀₁ and a current mirror transistor (active load) connected to the drain side of Q ₃₀₂ )
Provided with a Q _303, Q _304, and insert the low potential side transistor Q ₃₀₅ corresponding to the switching element 362 of FIG. 3 between the Q _301, Q _{30 2} and the low potential side power source V _SS, further Q
_303, Q ₃₀₄ and the high side transistor Q ₃₀₆ corresponding to the switching element 361 of FIG. 3 between the high-potential power supply V _CC,
Q ₃₀₇ is inserted. Reference numeral 365 denotes an inverter gate that logically inverts the potential V _OUT of the node Na between Q ₃₀₁ and Q ₃₀₃ and outputs the result to the inside of the chip.

The drain currents ID ₃₀₁ , ID ₃₀₂ flowing through the differential transistors Q ₃₀₁ , Q ₃₀₂ are made constant by the low power supply side transistor Q ₃₀₅ , and when one increases, the other decreases. Further, when the mirror ratio of Q ₃₀₃ and Q _{304 is} , for example, n: 1 (n is an arbitrary value including 1), there is a relationship of ID ₃₀₁ × n and ID ₃₀₂ × 1.

When V _IN <V _REF , ID ₃₀₁ × n <
ID ₃₀₂ × 1, and the potential of Na is pulled to V _SS side L
Logic is output. On the other hand, if V _IN > V _REF , then I
D _{30 1} × n> ID ₃₀₂ × 1, the potential of Na is pulled to the _VCC side, and H logic is output. The logic amplitude of the output V _OUT is given by the potential change width of Na (approximately V _CC −V _SS ),
A necessary input level is secured inside the chip.

Here, the high potential side transistors Q ₃₀₆ , Q
_The control circuit 36 for generating the gate voltage (control voltage) of ₃₀₇
3 functions as the first and second control voltage generating means described in the gist of the invention, and similarly, the low potential side transistor Q
Control circuit 36 for generating a gate voltage (control voltage) of ₃₀₅
4 also functions as the first and second control voltage generating means described in the gist of the invention.

That is, the control circuit 363 (364) uses the resistor R ₃₀₁ and the capacitor C ₃₀₁ (the resistor R ₃₀₂ and the capacitor C ₃₀₂ )
An R integration circuit is configured, and the frequency of V _IN is 50, for example.
When the frequency exceeds 1 MHz (first frequency), the impedance seen from the V _IN side is made resistive, while when the frequency is lower than 50 MHz (second frequency), the impedance is made capacitive. Is what you do. Such a relationship between frequency and impedance is expressed by R ₃₀₁ and C
_It can be set by the value of ₃₀₁ ( _R302 and _C302 ). Note that the above-mentioned resistance means that the real part of the complex number of the input impedance is sufficiently larger than the line impedance (generally 50Ω). Specifically, the operating frequency in the CTT (center tap termination) system (100 MHz) at 500 Ω or more. Incidentally, R ₃₀₁ = R ₃₀₂ = 1KΩ, C ₃₀₁ =
If 0.0112 PF and C ₃₀₂ = 0.065 PF,
The time constant of the control circuit 363 on the high-potential side where the follow-up property at the TTL level becomes a problem is 1KΩ × 0.065PF × 2 =
0.13 ns, and a sufficient response speed can be obtained. The values of C ₃₀₁ and C ₃₀₂ can be substituted by the gate capacitances of Q _{305 to} Q ₃₀₇ , so that it is not necessary to separately provide a capacitance device. Further, the control circuit 363 (364) is not limited to the CR integration circuit described above. For example, an LC integration circuit using the L component of the wiring and the gate capacitance of Q _{305 to} Q ₃₀₇ may be used.

FIG. 5 is a diagram showing a preferred W / L of the transistors Q _{301 to} Q ₃₀₇ . In this example, Q ₃₀₁ and Q
₃₀₂ has the same size, and Q _{303 to} Q ₃₀₇ have the same size. Mirror ratio of Q ₃₀₃ and Q ₃₀₄ is 1: 1. In such a configuration, when the frequency of V _IN exceeds 50 MHz (first frequency), the low-potential side transistor Q ₃₀₅ viewed from V _IN , that is, including the R ₃₀₁ and R _{302 .}
Since the input impedances of the high-potential side transistors Q ₃₀₆ and Q ₃₀₇ are resistive, these transistors Q _{305 to} Q ₃₀₇ function as equivalent resistors having a value slightly larger than the channel-on resistance. I do.

Therefore, the operation of the differential amplifying section 360 is permitted, and a potential V _OUT corresponding to the difference between V _IN and V _REF can be taken out from the drain of Q ₃₀₁ , and as shown in FIG. TTL or CM from input signal (V _IN )
OS level of a large amplitude signal (V _{OU T)} can be generated. Note that V _{OUT (INV)} is V _OUT inverted by the inverter gate 365.

On the other hand, V_INFrequency is below 50MHz
For the frequency (second frequency), V _INLow potential side seen from
Transistor Q₃₀₅And high-potential side transistor
Q₃₀₆, Q ₃₀₈Input impedance is capacitive,
ChiR₃₀₁And R₃₀₂Is negligible, so Q₃₀₅Also
Is Q₃₀₆, Q₃₀₇Is V_INOnly one is off according to the logic of
State.

Therefore, power supply to differential amplifying section 360 is provided.
The supply path is cut off, and the operation of the differential amplification unit 360 is prohibited.
It is. This allows low-speed data transfer (ie, high amplitude
Wasted power in differential amplifier 360 during signal transfer)
Consumption can be avoided. In this prohibited state, for example,
V_INIs H logic (TTL or C since it is the second frequency)
If it is MOS level H logic), Q₃₀₅Is on,
Q₃₀₆, Q ₃₀₇Is turned off and Q₃₀₅And Q₃₀₁
Through V_OUTIs V_SSIt is considerably reduced. Ah
Or V_INIs conversely L logic, Q₃₀₅Is off
Condition, Q ₃₀₆, Q₃₀₇Is turned on and Q₃₀₆, Q₃₀₇
And Q₃₀₁Through V_OUTIs V_CCConsiderably higher
I can do it.

Therefore, as shown in FIG. 7, a large-amplitude signal (V _OUT ) of the same level can be generated from an input signal (V _IN ) of a TTL or CMOS level (high amplitude), and can be taken into the chip without any trouble. Can be. Note that Q
By optimizing the threshold values of _305, Q ₃₀₆ and Q ₃₀₇ , the control circuits 363 and 364 of the above embodiment can be dispensed with.

FIG. 8 shows the threshold value of Q ₃₀₅ (expressed as V _{th 305} for convenience) and the threshold values of Q ₃₀₆ and Q ₃₀₇ with respect to the logical amplitude (small amplitude D _min and large amplitude D _max ) of the input signal V _IN . FIG. ₁₄ is a correspondence diagram of values (represented by V _th306 for convenience). If V _th305 and V _th306 are designed so as to _{satisfy the} following equation (2), V _th306 + V _th305 + D _min + β = D _max (2) where β: the operating margin V _IN is a very small amplitude Transfer), Q ₃₀₅ ,
While all of Q ₃₀₆ and Q ₃₀₇ are turned on to allow the operation of differential amplifying section 360, when V _IN has a large amplitude (low-speed data transfer), Q ₃₀₅ or one of Q ₃₀₆ and Q _{307 Is} turned on according to the logic state of V _IN ,
The operation of the differential amplifier 360 can be prohibited.

FIG. 9 is a configuration diagram of an input / output circuit in a chip including the input circuit described in the above embodiment. Output circuit 3
66 supplies a signal D _OUT from the inside of the chip to output transistors 369 and 370 in a push-pull configuration via two inverter gates 367 and 368, and an AND gate 371, a NOR gate 372, resistors 373 and
74 and transistors 375, 376. N1 is an input node of the output circuit 366, N2 is a node of the gate of one output transistor 369, N3 is a node of the gate of the other output transistor 370, and N4 is a gate of one transistor 375 forming the acceleration circuit 377. node,
N5 is the other transistor 3 constituting the acceleration circuit 377
A gate node 76, N6 is an output node of the output circuit (also an input node of the input circuit), and N7 to N10 are respective nodes of the input circuit.

When D _OUT transitions from H logic to L logic, for example, nodes N2 and N3 transition from L logic to H logic, one output transistor 369 turns off from on, and the other output transistor 370 Changes from off to on. Therefore, the level of node N6 is about to be reduced to V _SS through transistor 370. Here, since the chip I / O terminal DQ is connected a data line having a large capacitance component, the potential change of the node N6 proceeds more slowly than the change in D _OUT. However, the time is extremely short in the order of ns, and ringing or the like cannot be denied.

According to the configuration of FIG. 9, ringing can be eliminated by the cooperation of the input circuit and the acceleration circuit 377. That is, in FIG. 9 and FIG.
The falling change of 6 is monitored by the input circuit, and the L logic continues to be output from the input circuit until the TTL or CMOS level L logic is determined (the level of the node N8). The node N8 is also connected to the acceleration circuit 377. During this time, the transistor 376 on the low power supply _VSS side of the two transistors of the acceleration circuit 377 is on. Thereby, the data line outside the chip connected to the I / O terminal DQ is driven twice by the two transistors 370 and 376, and the potential drop of the node N6 is promoted. After a predetermined time, when the level of the node N6 is determined to be L logic (that is, when it falls below V _REF ), H logic is output from the input circuit, whereby the transistor 376 of the acceleration circuit 377 is turned off.

Therefore, the channel connected to the I / O terminal DQ
Data line outside the tap is connected to one output transistor 370
Therefore, since it is driven in a single state, the potential change of the node N6 is
It becomes calm, and waveform distortion such as ringing is avoided.
FIG. 11 is a voltage waveform diagram of each part in the input circuit.
In this waveform diagram, the level of the node N6 is changed from the L logic.
A state in which the state transits to the H logic at the second frequency is shown.
When the level of N6 is in the L logic area, Q₃₀₆Is on
State, this Q₃₀₆And Q₃₀₃Through V_CCConsiderable H
Logic is output (refer to the input waveform of the inverter 365A).
See). When the level of the node N6 transitions to the H logic area,
This time, Q ₃₀₅Is turned on and this Q₃₀₅And Q₃₀₁
Through V_SSThe corresponding L logic is output. Of node N6
Both the logical amplitude and the input waveform amplitude of the inverter 365A are
TTL or CMOS level.

FIG. 9 may be modified as shown in FIG. This improved example is a NOR gate 38 for regulating the taking in of the data D _{OUT into} the output circuit in accordance with a predetermined control signal TSC (tristate control).
0, inverter gate 381 and NAND gate 382
And a NAND gate 383 for regulating the output from the input circuit in accordance with a predetermined control signal (for example, a signal generated by RAS).
According to this, generation of undesired input / output signals due to noise or the like can be reliably avoided.

Alternatively, the types (P-channel type, N-channel type) of the transistors constituting the differential amplifier circuit included in the input / output circuit of FIG. 9 or FIG. 12 may be changed as shown in FIG. In FIG. 13, Q ₃₁₁ , Q
₃₁₂ and Q ₃₁₅ are P-channel type MOS-FETs, Q
₃₁₃ , Q ₃₁₄ , Q ₃₁₆ and Q ₃₁₇ are N-channel M
This is an OS-FET. According to this, the same operation as in the above embodiments can be obtained, and even when the reference voltage V _REF is set to a relatively low voltage (for example, about 0.8 V), the gate-source Since a sufficient bias voltage is applied in between, there is an advantage that the gain of the input differential amplifier stage is not easily reduced.

Alternatively, as shown in FIG. 14, a transistor Q ₃₀₈ is inserted in series with the transistor Q ₃₀₅ on the low power supply side of the input circuit, and this Q ₃₀₈ is turned on / off in accordance with a predetermined control signal (for example, a signal generated by RAS). May be. In addition to avoiding generation of undesired input signals due to noise or the like, there is an advantage that the power supply of the input circuit can be cut off during standby and power consumption can be suppressed.

FIG. 15 shows data including the above input circuits.
FIG. 3 is a configuration diagram of a transfer circuit. In this figure, 390 is an input.
LSI chip including a power circuit (see FIG. 3 or FIG. 4) 391
392 is a CPU (for example, DRAM). CPU
Bit B from 392₁From bit B_nData up to
(May be an address). Each of the data
The bit is a data line (typically bit B₁Data line 3
93 is shown) through the LSI chip 390 or another chip
Is forwarded to Data line 393 and predetermined power supply line V _TT(V
_CCAnd V_SSPower supply line having an intermediate potential of, for example, +1.65
V), a CMOS switch (switching hand)
Stage) 394, 395, the termination resistors 396, 397
And the CMOS switches 394, 395
Decoding from decoder (on / off control means) 398
Signal DC is in high-speed transfer mode (frequency exceeding 50 MHz)
ON when expressing the transfer mode, and the low-speed transfer mode (5
(Transfer mode for frequencies below 0 MHz)
It is designed to

Therefore, according to this configuration, when transferring the data of the first frequency in the above-described embodiment,
The amplitude can be reduced by using the terminating resistors 396 and 397, and a transfer waveform suitable for high-speed transfer can be obtained. Further, when transferring the data of the second frequency in the above-described embodiment, the terminating resistors 396 and 397 are removed to increase the amplitude, and the terminating resistors 396 and 39 are removed.
7 can be avoided and the power consumption can be improved. That is, the CP that determines the frequency of the transfer data
Since the configuration of the data transfer path can be changed as appropriate in accordance with the instruction from U, a convenient and convenient data transfer circuit that can be shared by applications that emphasize processing speed and applications that emphasize power consumption can be realized.

FIGS. 16 to 18 are views showing a first embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit which can be used in both CTT and CMOS is shown in FIGS. It is an example. First, the configuration will be described. 16, 400 is a chip of a semiconductor integrated circuit, the transceiver circuit is in the chip 400 and an output buffer 441 and input buffer 442 are mounted. The output buffer 441 includes a first PMOS transistor 443a and a first NMOS transistor 443 connected in series between the high-potential-side power supply V _CC and the low-potential-side power supply V _SS.
b, a first CMOS unit 443, and V _CC and V
Second PMOS transistor 44 connected in series between _SS
4a and a second CMOS transistor 444b composed of a second NMOS transistor 444b, and ON / OFF operations of these four MOS transistors 443a, 443b, 444a, 444b are performed by a signal (indicated by A for convenience) from a chip internal circuit 445. ), A tri-state control signal (a signal designating an output high impedance at H level) TSC, etc., an on / off control means 446, a differential amplifier 447 and an inverter gate 4
48 and a predetermined mode designating signal (CM at L level).
A signal designating an OS transfer mode) The first CMOS section 443 and the second CMOS section 4 are based on a CMOS bar.
44, a mode control means 449 for switching the operation mode. Note that 450 is a chip internal circuit that receives the signal B from the input buffer 442, 451 is an input / output terminal,
452 is a reference voltage terminal, and the input / output terminal 451 is connected to the first PMOS transistor 443a and the first NMO
The connection point P ₄₄₃ of the S transistor 443b and the second PMO
It is connected to both the S transistor 444a and the connecting point P ₄₄₄ of the second NMOS transistor 444b, also connected to the chip 440 outside of the signal line 453. The input / output terminal 451 is connected to the chip 44.
When 0 is used in the CTT level transfer mode (first transfer mode), a predetermined constant voltage V _TT (V _TT = V _CC ) is applied via the terminating resistor 454 (the resistance value is 25Ω when both ends are used).
/ 2; +1.5 V when V _CC is +3 V), and the constant voltage V _TT is applied to the reference voltage terminal 452.
Has also been given. [CTT Operation] In such a configuration, the level of the signal B is determined by the potential relationship between the inverting input (-) and the non-inverting input (+) of the differential amplifier 447. That is, when the potential of the inverting input (−) is V _TT =
+ 1.5V, the potential of the non-inverting input (+) is
If it exceeds 1.5 V, in other words, the input / output terminal 451
Is established at the H level, the inverter gate 44
The output (signal B) of signal 8 becomes L level and is equal to or lower than +1.5 V, in other words, when the logic of the input / output terminal 451 becomes L level, the signal B becomes H level.

Now, when the signal A transitions from the L level to the H level (however, the signal TSC remains at the L level),
Output L level of the inverter gate 455 of the off control means 446, the output of inverter gate 456 becomes the H level, the output S ₄₅₈ of the output S ₄₅₇ and AND gate 458 of the NOR gate 457 becomes the H level. Immediately after the signal A transitions from L to H, the signal B is at H level (input / output terminal 4
51 is at the L level), and since the signal CMOS is also at the H level during the CTT operation, the outputs of the inverter gates 459 and 460 of the mode control means 449 are both at the L level. Therefore, the NOR gate 461 and the NAND gate 462 simply operate as inverter gates, and both the outputs S ₄₆₁ and S ₄₆₂ go to the same H level as the signal B.

[0059] Thus, the output of the inverter gate 463 of the on / off control means 446 S _{46 3,} the NAND gate 4
The output S ₄₆₄ of 64, the output S ₄₆₆ of the output S ₄₆₅ and the inverter gate 466 of the NOR gate 465 becomes all the L level. Therefore, the first PMOS transistor 443a and the second PMOS transistor 443a of the two-stage CMOS units 443 and 444 are used.
Transistor 444a are both turned on, and the first NMOS transistor 443b and the second NMOS transistor 444b of the CMOS portion 443 and 444 is turned both turned off "V _CC → first PMOS transistor 443a and the second PMOS transistor 444a
→ in the direction of the terminating resistor 454 → V _TT "current + I _L flows. Thereafter, the potential of the non-inverting input (+) of the differential amplifying unit 447 is higher than the potential of the inverting input (-) by I _L × R _L ( _RL is the value of the terminating resistor 454; for example, 25Ω). When the signal B is inverted to L level when the logic of the input / output terminal 451 (H level of CTT) is determined, two outputs S ₄₆₁ and S ₄₆₁ from the mode control means 449 are obtained.
₄₆₂ both change to L level, and the on / off control means 44
As a result of the output S ₄₆₄ of the AND gate 464 being at the H level, after the logic of the input / output terminal 451 is determined, the drive current + I _L flows only by the first PMOS transistor 443a.

On the other hand, when the signal A changes from the H level to the L level (however, the signal TSC remains at the L level), the output of the inverter gate 455 of the on / off control means 446 goes to the H level. Output S ₄₅₇
The output S ₄₅₈ of the AND gate 458 are both L level. Immediately after the signal A transitions from H to L, the signal B is at the L level.
The output of the 59 becomes the H level, the output S ₄₆₂ of the output S ₄₆₁ and NAND gate 462 of NOR gate 461 are both L level.

[0061] Thus, the output of the inverter gate 463 of the on / off control means 446 S _{46 3,} the NAND gate 4
The output S ₄₆₄ of 64, the output S ₄₆₆ of the output S ₄₆₅ and the inverter gate 466 of the NOR gate 465 are all H level. Therefore, contrary to the above, the CMOS unit 443,
444, the first PMOS transistor 443a and the second PMOS transistor 444a are both turned off,
Also, the first NMOS transistor 443b and the second NMOS transistor 44 of the CMOS units 443 and 444 are provided.
4b are turned on, and “V _TT → Terminal resistance 454 →
First NMOS transistor 443b and second NM
The current −I _{L in} the direction of “OS transistor 444b → V _SS ”
Flows. Thereafter, the potential of the non-inverting input (+) of the differential amplifying unit 447 is higher than the potential of the inverting input (-) by I _L × R _L.
Only when the signal B becomes “low”, that is, when the logic of the input / output terminal 451 (CTT L level) is determined.
When the level is inverted, the two outputs S ₄₆₁ and S ₄₆₂ from the mode control means 449 both change to the H level, and the output S ₄₆ of the NOR gate 465 of the on / off control means 446.
₅ becomes L level results, in the following the logic of the input and output terminals 451 is confirmed, the first NMOS transistor 443b
Drive current -I _L is passed through only by. [CMOS operation] Mode designation signal CMOS bar (hereinafter, referred to as CMOS bar)
When the bar is omitted), the semiconductor integrated circuit 4
40 can be used at the CMOS level. In this case, remove the terminating resistor 454 between the signal line 453 and V _TT.

When the signal CMOS is set to L level, the signal B
Output S of the mode control means 449 regardless of the logic
₄₆₁ is fixed at L level and output S ₄₆₂ is fixed at H level.
Therefore, the NAND gate 4 of the on / off control means 446
As a result, the two-stage CMOS units 443 and 444 operate in parallel on / off according to the logic of the signal A.

For example, when the signal A transitions from the L level to the H level (however, the signal TSC remains at the L level), since both S ₄₅₇ and S ₄₅₈ are at the H level, the on / off control means 446 4 outputs (S ₄₆₃ , S ₄₆₄ ,
S ₄₆₅ and S ₄₆₆ ) are all at L level and the two-stage C
Both the first PMOS transistor 443a and the second PMOS transistor 444a of the MOS units 443 and 444 are turned on. These two PMOS transistors 443
a and 444 a coincide with the H level period of the signal A.

Therefore, the output terminal 451 is connected to the H level of the signal A.
In the level period, two PMOS transistors 44
3a and 444a are driven in a double manner.
This is the same when the signal A changes to the L level. In this case, the first NMOS transistor 443b and the second NMOS transistor 443b of the two-stage CMOS units 443 and 444 are used.
The transistors 444b are both turned on.

Therefore, the output terminal 451 is connected to the low level of the signal A.
In the level period, two NMOS transistors 44
3b and 444b are driven double.
FIG. 17 is a time chart for comparing the CTT mode and the CMOS mode. In the CTT mode, the signal A
, The logic of the signals S ₄₆₄ , S ₄₆₅ , S ₄₆₃ and S ₄₆₆ matches only during the period from when the logic of the signal B is inverted until the logic of the signal B is inverted.

Therefore, in the CTT mode, 2
PMOS transistors 443a, 444a, or
The two NMOS transistors 443b and 444b
Period from immediately after the transition of signal A until the logic of signal B is inverted
Only in parallel, and after this period, the first
PMOS transistor 443a or first NMOS transistor
Only the transistor 444a is turned on. Output terminal 4
51 (that is, the amplitude of the signal appearing on the signal line 453).
Is the first PMOS transistor 443a or the first
On-resistance value R of NMOS transistor 444a_ONThe end
The value R of the terminal resistance 454_L, And termination voltage V_TTIn the size of
For example, if the signal amplitude is 0.4 V, V _TTTo 1.5
V, R_LIs 25Ω, R_ONIs 6 from the previous equation (1).
8.75Ω. This R_ONSatisfies the first P
MOS transistor 443a or first NMOS transistor
The size of the transistor 444a is set to “L = 1 μm, W = 20
It may be set to about 0 μm.

On the other hand, in the CMOS mode, the signal S
₄₆₄ , S ₄₆₅ , S _463, and S ₄₆₆ always have the same logic, and since the terminating resistor 454 is removed, the amplitude of the signal appearing at the output terminal 451 is two PMs.
OS transistors 443a, 444a or two N
It is determined by the parallel on-resistance of the MOS transistors 443b and 444b. Therefore, the first PMOS transistor 4
43a and the ON resistance of the first NMOS transistor 443b are set to about 68.75Ω,
By setting the on-resistance of the MOS transistor 444a and the second NMOS transistor 444b as small as possible, the value of the parallel on-resistance can be sufficiently reduced, and the driving force required for the CMOS level can be secured.

The second PMOS transistor 444
a and the size of the second NMOS transistor 444b are set to about the size of a general CMOS output transistor (for example, L = 1 μm, W = 1000 μm), and in principle, these second PMOS transistors 444a
And the second NMOS transistor 444b alone can provide a sufficient driving force.
The present invention is not limited to the one in which the OS transistors are driven in parallel. For example, the first PMOS transistor 443
a and the internal resistance of the first NMOS transistor 443b are set to values suitable for the CTT level, and the second PM
The internal resistances of the OS transistor 444a and the second NMOS transistor 444b may be set to values suitable for the CMOS level, and these two sets of MOS transistors may be selectively used at the CTT level and the CMOS level. Of course, if the two sets of transistors are driven in parallel, the driving force can be further increased. Therefore, the adoption of such a driving method in the CMOS mode is a natural consequence.

The mode designation signal CMOS is shown in FIG.
It is desirable to automatically generate it by the circuit shown in FIG. This circuit corresponds to the reference voltage terminal 452 of the chip 440 (FIG. 16).
(See Reference potential V _REF ), and if the potential is higher than the threshold voltage of NMOS transistor 470, that is, terminal voltage V _TT (= + 1.5 V) of CTT is applied to reference voltage terminal 452. NMOS
While the output of the CMOS inverter gate 471 (signal CMOS) to H level to turn on transistor 470, if the reference voltage terminal 452 is open or ground level, i.e. if not given, the termination voltage V _TT of CTT , Turn off the NMOS transistor 470 and output the CMOS inverter gate 471 (signal CMO).
S) is changed to L level. Note that 472 to 47
4 is a resistor, 475 is a capacitor, 472 is for applying a ground level to the gate of the NMOS transistor 470 when the reference terminal 452 is opened, and 473 is a load element of the NMOS transistor 470. Further, the resistor 472 and the capacitor 475 form an integrating circuit, which cuts input noise and prevents malfunction of the NMOS transistor 470.

When such a circuit is used, the CTT mode and the CMOS mode can be automatically switched according to the potential of the reference voltage terminal 452, and the usability of the semiconductor integrated circuit can be improved. FIGS. 19 and 20 show a second embodiment of a semiconductor integrated circuit according to the present invention.
This is an example of a semiconductor integrated circuit that can be used for the GTL in addition to the OS. Note that circuit elements common to the first embodiment are denoted by the same reference numerals.

First, the configuration will be described. In FIG.
480 is a differential amplifier, and this differential amplifier 480 is
Gates of a pair of NMOS transistors 481 and 482
To the input / output terminal 451 and the reference voltage terminal 452, respectively.
The source of the NMOS transistors 481 and 482
Is connected to the low-potential-side power supply V via the constant-current transistor 483. _SS
And the NMOS transistors 481 and 4
82 and the high potential side power supply V_CCBetween each
Two PMOS transistors 484, 485 (486,
487) are connected. Note that the PMOS transistor
The gates of the star 484 and 486 are input through a resistor 488.
The output terminal 451 is connected to the PMOS transistor 48
5 and 487 have gates of NMOS transistor 482
Connected to the rain. In addition, the constant current transistor 4
The gate of 83 is connected to the input / output terminal 451 via the resistor 489.
It is connected. The differential amplifier 480 having such a configuration is
According to the potential relationship between the output terminal 451 and the reference voltage terminal 452
Signal (signal B) from the NMOS transistor 481
The signal B is output from the input / output terminal 4
51 is higher than the potential of the reference voltage terminal 452 (H
Level), the L level is based on the potential of the input / output terminal 451.
When lower than the potential of the reference voltage terminal 452 (L level)
It becomes H level. The signal B is a signal Enable.
Through a NAND gate 490 controlled by
Is provided to the internal circuit 450, and the signal Enable
To the L level, for example, the standby mode
Signal input to the chip internal circuit 450 when
It has become so.

Reference numeral 491 denotes an on / off control means.
The difference from the on / off control unit of the embodiment is that the first PMOS
NAND gate for on / off control of transistor 443a
492, the second PMOS transistor 444
a and ON / OFF of the second NMOS transistor 444b
So-called deglitcher circuits 493 and 494 are used for control.
And the first NMOS transistor 443b
NMOS in the inverter gate 466 for on / off control
An additional circuit consisting of a transistor 495 and a resistor 496 is provided.
It is a digit. The NAND gate 492 has a predetermined mode finger.
If the constant signal GTL bar (hereinafter abbreviated to bar) is at H level
It simply functions as an inverter gate. That is,
Its output S₄₉₂Is the output S of the preceding NOR gate 457.₄₅₇
The mode designating signal GTL goes low.
(GTL mode), the output S ₄₅₇Regardless of the logic of
And its output S₄₉₂Is fixed at the H level.

Therefore, the first PMOS transistor 443a is fixed off during the L level period of the mode designation signal GTL. The deglitcher circuits 493 and 494 are
This circuit includes a multi-stage inverter gate 493a (494a) and a flip-flop 493b (494b), and inhibits re-acceptance of an input for a time determined by the multi-stage inverter gate 493a (494a) to improve noise immunity. These deglitcher circuits 493 and 494, the output S ₄₅₇ of the NOR gate 457, the two outputs S of the output S ₄₅₈ and mode control means 497 of the NAND gate 458
₄₉₉ , The output logic is determined according to the logic of _S500 (described later). The NMOS transistor 495 and the resistor 496 added to the inverter gate 466 are connected to the mode designation signal GT.
When L is at L level (GTL mode), the NMOS transistor 495 is turned off and the inverter gate 466 is turned off.
A resistor 496 is inserted in the low-potential power supply path (that is, the gate charge discharge path of the first NMOS transistor 443b) to delay the cutoff of the first NMOS transistor 443b to avoid a sudden snap-off of the output signal. Things.

The mode control means 497 includes an inverter gate 498 for removing the inverter gate 459 from the configuration of the mode control means of the first embodiment, inverting the logic of the mode designation signal GTL, and two NOR gates 499,
The difference is that 00 is added. When the mode designating signal GTL is at the H level, the two NOR gates 499 and 500 simply function as inverter gates. When the mode designating signal GTL is at the L level (GTL mode), the two NOR gates 499 and 500 are turned off. The outputs S ₄₉₉ and S ₅₀₀ are forcibly fixed at the L level. Here, the output S ₄₆₁ of the inverter gate 461 and the output S ₄₆₁ of the NAND gate 462
_{Reference numeral 462} indicates a logic opposite to that of the signal B when the mode designation signal CMOS is at the H level (inverse to the first embodiment because the inverter gate 459 is removed), but is forced when the mode designation signal CMOS is at the L level. The L level is fixed at all times.

Therefore, the logic of the outputs S ₄₉₉ and S ₅₀₀ extracted from the mode control means 497 is uniquely determined from the logic of the two mode designation signals GTL, CMOS and the signal B as shown in Table 1 below. Hereinafter, each mode will be described. [CTT mode] When both of the mode designation signals CMOS and GTL are set to H level, the CTT mode is set.

Immediately after the signal A transitions from L to H, the signal B is
Since the output is at the level, the outputs S ₄₉₉ and S ₅₀₀ extracted from the mode control means 497 are both at the H level according to Table 1 above. Therefore, the output logic of the deglitcher circuits 493 and 494 of the on / off control means 491 is the reverse logic of the signal A, and since the signal A is at the H level, the output S ₄₉₃ ,
_S494 becomes L level. As a result, all four outputs (S ₄₉₂ , S ₄₉₃ , S ₄₉₄ and S ₄₆₆ ) of the on / off control means 491 become L level, and the first PMOS transistor 443 a and the second PMOS transistor 444 a
Is turned on, and the input / output terminal 451 is driven double to the _VCC side. Then, when the logic of the input / output terminal 451 is determined to be at the H level, the signal B is inverted to the L level.
Output S taken out from the mode control means 497
_499, S ₅₀₀ are both in the L level.

Therefore, the logic of the input / output terminal 451 becomes H
Since to have been fixed at the level, the output S ₄₉₃ of deglitcher circuit 493 from the H level, the second PMOS transistor 444a is turned off, input-output terminal 451 is driven only by the first PMOS transistor 443a.
On the other hand, when the signal A is changed from H level to L level, immediately after the transition, since the signal B is at L level, the output S ₄₉₉ taken out from the mode control means 497, S
_From Table 1 above, ₅₀₀ is at the L level.

Therefore, the output S ₄₆₃ of the deglitcher circuit 493 is fixed at the H level, the output S ₄₉₄ of the deglitcher circuit 494 has the opposite logic to the signal A, and the output S ₄₉₄ is at the H level because the signal A is at the L level. As a result, the four outputs of the on / off control means 491 (S ₄₉₂ ,
S ₄₉₃ , S ₄₉₄ and S ₄₆₆ ) all become H level,
First NMOS transistor 443b and second NMOS
When the transistor 444b is turned on, the input / output terminal 4
51 is double driven to the _VSS side. Then, when the logic of the input / output terminal 451 is determined to be at the L level, the signal B is inverted to the H level, and from Table 1 above, the outputs S ₄₉₉ and S ₅₀₀ extracted from the mode control means 497 are both at the H level.

Therefore, the logic of the input / output terminal 451 is L
Since to have been fixed at the level, the output S ₄₉₄ of deglitcher circuit 494 from an L level, the second NMOS transistor 444b is turned off, input-output terminal 451 is driven only by the first NMOS transistor 443b. [CMOS mode] While terminating resistor 454 is removed,
When the mode designation signal CMOS is set to L level while the mode designation signal GTL is kept at H level, a CMOS mode is set.

[0080] In this mode, the two output taken from the mode control unit 497, from the above table 1, regardless of the signal B, the output S ₄₉₉ is H level, the output S ₅₀₀ is fixed to the L level. Therefore, the on / off control means 49
The outputs S ₄₉₃ , S of the one deglitcher circuit ₄₉₃ , 494
₄₉₄ has the opposite logic to signal A. For example, if signal A is at H level, outputs S ₄₉₃ and S ₄₉₄ will be at L level.
As a result, the four outputs (S
₄₉₂ , S ₄₉₃ , S ₄₉₄ and S ₄₆₆ ) all have the opposite logic to the signal A, and if the signal A is at the H level, the first PMO
Both the S transistor 443a and the second PMOS transistor 444a are turned on, and the input / output terminal 451
_When the signal is driven double to the _CC side or when the signal A is at the L level, the first NMOS transistor 443b and the second
NMOS transistors 444b are both turned on, and the input / output terminal 451 is driven double to the _VSS side. Driving by the two transistors is performed by the input / output terminal 45.
After the level of 1 is determined, that is, after the logic of the signal B is inverted, the large driving force required for the CMOS level can be secured. [GTL mode] When the mode designation signal GTL is set to the L level, the GTL mode is set. In this case, the mode designation signal C
MOS logic is ignored. In the GTL mode,
A termination resistor 454 is attached, and the termination voltage V _TT
Needs to be + 0.8V. In this mode, two outputs S ₄₉₉ taken out from the mode control means 497,
From Table 1 above, S ₅₀₀ is fixed at L level regardless of the signal B. Therefore, the on / off control means 49
1, the output S ₄₉₃ of the deglitcher circuit 493 is fixed at the H level.
_{492 is} also fixed at the H level. As a result, the first PMOS
Transistor 443a and second PMOS transistor 4
44a can be forcibly cut off together, GTL
The open drain required for the mode can be configured. In the GTL mode, when the logic of the input / output terminal 451 transitions from the H level to the L level, the output S ₄₆₆ (that is, the gate of the first NMOS transistor 443 b) is generated by the effect of the resistor 496 added to the inverter gate 466. Potential) is slowing down. This is because the first NMOS transistor 443b
In order to avoid a sudden snap-off of the output signal.

FIG. 20 is a time chart of the second embodiment. CTT mode, GTL mode or CMOS depending on the combination of two mode designating signals CMOS and GTL
Can be used in any of the modes. That is, C
In the TT mode, the input / output terminal 451 is driven by the two MOS transistors from immediately after the transition of the signal A until the output logic is determined (the signal B changes). I / O terminal 451 with transistor
Can be driven, and in the GTL mode, two PMOS transistors can always be cut off to form an open drain. Further, in the CMOS mode, the input / output terminal 45 always includes two MOS transistors.
1 can be driven, and a sufficient driving force can be secured.

FIGS. 21 and 22 show a third embodiment of the semiconductor integrated circuit according to the present invention, which is a modification of the second embodiment. In this example, in the CTT mode, the first
The output terminal 451 is driven using only the PMOS transistor 443a and the first NMOS transistor 443b. In FIG. 21, when the mode designating signal GTL is at the H level, the mode control
The output S ₄₉₉ of 99 as well as the mode designation signal CMOS opposite logic is intended to output S ₅₀₀ of the NAND gate 500 to a mode designation signal CMOS same logic, also when the mode designation signal GTL has the L level, Regardless of the logic of the mode designation signal CMOS, the two outputs S ₄₉₉ , S
₅₀₀ is fixed at the L level. Note that reference numeral 502 denotes an inverter gate for generating a signal having a logic opposite to the mode designation signal CMOS.

These two outputs S ₄₉₉ and S ₅₀₀ are connected to the NAND gate 50 of the on / off control means 491 A, respectively.
3 and NOR gate 504. NAND Gate 50
Reference numeral 3 simply functions as an inverter gate when the output S ₄₉₉ is at the H level, that is, when the mode designation signal GTL is at the H level and the mode designation signal CMOS is at the L level, in other words, when the CMOS mode is set.

Therefore, the output S of the NAND gate 503 is
₅₀₃ has the same logic as the signal A in the CMOS mode, and is fixed at the H level in other modes (CTT / GTL). NOR gate 504 outputs a signal when output S ₅₀₀ is at L level, that is, when mode designating signal GTL is at H level and mode designating signal CMOS is at L level, or when mode designating signal GTL is at L level, In other words, it simply functions as an inverter gate in the CMOS mode or the GTL mode.

Therefore, the output S of NOR gate 504
₅₀₄ has the same logic as the signal A in the CMOS mode or the GTL mode, and is fixed at the L level in other modes (CTT). From the above, according to the third embodiment, as shown in the time chart of FIG.
In the CTT mode, the first PMOS transistor 4
The output terminal 451 can be driven only by the first transistor 43a and the first NMOS transistor 443b, and in the other modes (GTL mode or CMOS mode), the same operation as the second embodiment can be obtained. Such a modification is suitable for a system having a long transmission distance at the CTT level. If the transmission distance is long, the second PMOS transistor 444a and the second NMOS transistor 44
This is because the acceleration effect of 4b is weak, and it is better to simplify the circuit.

Embodiments according to the ninth to twentieth aspects of the present invention FIGS. 23 to 28 are views showing an embodiment of a semiconductor integrated circuit according to the present invention. Here, this embodiment is intended to eliminate the drawback of the mode designation signal automatic generation circuit (see FIG. 18) of the above embodiment. In other words, the circuit of FIG. 18 according to the embodiment determines the logic of the mode designation signal (signal CMOS) by comparing the reference potential V _REF with the “threshold voltage” of the NMOS transistor 470. However, in general, variation in the threshold voltage of a transistor due to a manufacturing error or the like cannot be avoided, and there is room for improvement in operation stability.

FIG. 23 is a block diagram showing the principle of the present embodiment. This
In the figure, 601 and 602 are comparators,
Hereinafter, the comparator 601 is referred to as a first comparator,
If the parator 602 is called a second comparator,
1 comparator 601 has a reference voltage V_REFAnd constant voltage V
_CTTAnd V_REF> V_CTTSpecified logic when
(High level), and outputs the signal CTTM.
2 comparator 602 has a reference voltage V_REFAnd constant voltage V
_GTLAnd V_REF> V_GTLSpecified logic when
(High level) signal GTLM is output. here
And V_CTTIs the reference voltage V in the CTT mode._REFof
Value (V_CC/2=+1.65V or + 1.5V)
With a constant potential and a constant voltage V_GTLIs GTL mode
Reference voltage V when _REFGreater than the value (+ 0.8V)
Have a high potential. For example, V_CTT= + 2.2
V, V_GTL= + 1.2V is desirable.

Table 2 is a correspondence table between the reference voltage V _REF and the mode designation signals (CTTM, GTLM). In this way, the determination operation of the three modes can be stabilized depending on the accuracy of the two constant voltages V _CTT and V _GTL , and the constant voltages V _CTT and V _GTL can be generated accurately by, for example, resistance voltage division. In addition, it is possible to realize an automatic mode designating signal generation circuit suitable for an interface that is practically used for CTT / GTL / TTL.

In this embodiment, the switch elements 603 and 604 capable of cutting off the power supply current of the first and second comparators 601 and 602, and the value of the reference voltage V _REF is V _CC
(Or open), that is, a control means 605 for turning off the switch elements 603 and 604 in the TTL mode. Is set to zero.

Further, in this embodiment, the signal CTTM
V_REFOr constant voltage V_{TT L}Select one of
And the reference voltage INREF of the input buffer circuit (eg,
For example, V in FIG._REF) Is provided.
ing. When the signal CTTM is at a low level,
In T mode or GTL mode, INREF = V
_REFAnd when the signal CTTM is at a high level, that is,
In the TTL mode, INREF = V_TTLBecomes
V_TTLIs preferably V_CC/ 2. According to this, each
Automatically sets the reference voltage INREF suitable for the mode
It can be generated and provided to an input buffer circuit.

FIG. 24 shows the components of the mode designation signal automatic generation circuit.
It is a physical block diagram. In this figure, the same as FIG.
The same reference numerals are given to the functional parts. That is, the first
And the second comparators 601 and 602 are respectively
And the PMOS transistor Q_{60 1A}, Q_601B, Q_602A, Q
_602BNMOS transistor Q with a load element_601C, Q
_601D, Q_602C, Q_602DAnd the NMOS transistor Q
_601E, Q_602EAnd a constant current source.
The switch elements 603 and 604 each include two
PMOS transistor Q_603A, Q_603B, Q_604A, Q_604B
have.

The above two switch elements 603 and 604
A resistor R is connected to the gate of the transistor. ₆₀₀Through the chip
Of the reference voltage terminal 607 is applied.
Is the reference voltage V from outside the chip_REF(+ 0.8V, +
1.65V or + 1.5V) is applied (C
(TT or GTL mode)_REFLow corresponding to
Potential is high and is not applied (TTL mode)
Has a resistance R₆₀₁Through V_CCHigh electricity pulled up to
It is fixed to the place.

For this reason, the two switch elements 603, 6
Reference numeral 04 denotes an ON state in the GTL or CTT mode to allow supply of the power supply current to the first and second comparators 601 and 602, but inhibits supply of the same current in the TTL mode (cut off). Thus, the power consumption of the first and second comparators 601 and 602 can be reduced to zero.

The first comparator 601 compares the potential of the reference voltage terminal 607 with the constant voltage V _CTT . When V _CTT is lower, the output of the inverter gate 608 (signal C
TTM) to a high level. Further, the second comparator 602 calculates the potential of the reference voltage terminal 607 and the constant voltage V _GTL
When _VGTL is lower, the output (signal GTLM) of the inverter gate 609 is set to the high level.

The signal CTTM is input to a switch element 606 composed of two NMOS transistors Q _606A and Q _606B and one inverter gate I _606A . The switch element 606 is responsive to the logic state of the signal CTTM. To select either the potential of the reference voltage terminal 607 or the constant voltage _VTTL , and set the reference voltage INR for the input buffer circuit.
Output as EF. That is, when the signal CTTM is at a low level (GTL or CTT mode), the Q _606A is turned on and the potential of the reference voltage terminal 607 becomes INRE.
F, while the signal CTTM is at a high level (T
In the TL mode), the Q _606B is turned on and the constant voltage V
_TTL becomes INREF.

FIG. 25 shows an example of a circuit for generating a constant voltage V _TTL , V _CTT or V _GTL. The voltage between the high-potential power supply V _CC and the low-potential power supply V _SS is divided by resistors Ra and Rb. A constant voltage having a magnitude corresponding to the voltage division ratio is generated. FIG. 26 is a graph showing a level change of various signals (GTLM, CTTM, INREF) with respect to a potential change of the reference voltage terminal 607. Now, the reference voltage terminal 607
Potential, looking is changed to V _CC (+ 3.3V) from 0V, the region "I" of _{0V~V GTL (V GT L = +} 1.2V), is a signal GTLM, CTTM are both low level There, in the region "b" of _{V GTL ~V CTT (V CTT =} + 2.2V), only the signal GTLM becomes a high level,
Further, in the region “C” between V _{CTT and} V _CC , the signal CTTM
Also goes high. In addition, INREF indicates the area “i”.
The potential of the reference voltage terminal 607 coincides with the potential between “b”, and is fixed at V _TTL in the region “c”.

Therefore, the potential of the reference voltage terminal 607 is +0.8 V in the GTL mode, +1.65 V (or +1.5 V) in the CTT mode, and TTL
In the case of the mode, the potential becomes V _{CC. Therefore} , these potentials are classified into respective regions, and two mode designation signals GTLM,
It can be displayed by a combination of CTTM. FIG. 27 is a block diagram of a semiconductor memory to which the present invention is applied.
0. In this figure, 700 and 701 are clock generators, 702 is a mode control, 703 is an address buffer and an address predecoder, 704
Is a column decoder, 705 is a sense amplifier and I / O
A gate, 706 a row decoder, 707 a refresh address counter, 708 a substrate bias generator, 709 a memory cell array, 710 a write clock generator, 711 a data input buffer, 712
Is a data output buffer. Incidentally, RAS is a row address strobe signal, CAS is a column address strobe signal, A ₀ to A ₉ are address signals, WE is a write enable signal, OE is an output enable signal, DQ
₁ to DQ ₄ are input and output data, V _REF is the reference voltage.

The data input buffer 711 and the data output buffer 712 constitute a CTT / GTL / TTL transceiver, and the data input buffer 711 includes:
The mode specifying signal automatic generation circuit 600 outputs the reference voltage INR
EF is given, and the data output buffer 712 is given two types of mode designation signals CTTM and GTLM.

FIG. 28 is a configuration diagram of a transceiver (where 1
FIG. Data input buffer 711
_Are the five PMOS transistors Q _711A , Q _711B , Q
_712C, Q _711D, and Q _711e, 4 pieces of the NMOS transistors _{Q 711F, Q 711G, Q 711H} , and Q _{71 1I,} and a one inverter gate 713, the potential of the data input-output terminal 714 and the reference voltage INREF Are compared, and when INREF is lower, its output (output of inverter gate 713;
(Hereinafter referred to as A) to a high level.

The data output buffer 712 has a first PMOS transistor 715 and a first NMOS transistor 716 connected in series between the high potential power supply V _CC and the low potential power supply V _SS, and similarly, the second PMOS transistor 715 and the second PMOS transistor 716. A transistor 717 and a second NMOS transistor 718 are connected in series, and the first NMOS transistor 7
16 (or the second NMOS transistor 718)
Output transistor group 720 configured by connecting the NMOS transistors 719 in parallel.

First and second PMOS transistors 71
5, 716 and first to third NMOS transistors 7
17 to 719 are NAND gates 722 to 727, NOR gates 728 to 731 and inverter gates 732 to 7
The on / off operation is controlled by a control circuit 721 including 35. Hereinafter, each operation mode will be described. In the following description, it is assumed that both the tri-state control signal TSC and the operation permission signal Enable are at a high level. [GTL] First, when the signal CTTM and the signal GTLM are at the low level (GTL mode), the output of the NAND gate 725 is fixed at the high level, the output of the NOR gate 731 is fixed at the low level, and the output of the NAND gate 724 is fixed at the high level. Then, the feedback of the logic of the signal B to the output buffer side is prohibited. At the same time, the inverter gate 7
34 becomes high level, the NOR gate 728
Becomes low level, and the NAND gates 722, 7
23 is fixed at a high level, the first and second PMOS transistors 715 and 717 are fixed at off, and the output transistor group 720 performs an open drain operation of only these NMOS transistors. That is, if the logic of the data Din from the internal circuit is, for example, low level, the outputs of the NOR gates 729 and 730 both go high, and the output of the inverter gate 735 also goes high at the same time. Second
NMOS transistors 716 and 718 are turned on, and the third NMOS transistor 7
19 is also turned on, and the input / output terminal 714 is efficiently driven by these three NMOS transistors.
Therefore, an output transistor having a large driving force required for the GTL mode can be realized. [CTT] Next, the signal CTTM is at the low level and the signal GT
When LM is at the high level (CTT mode), the outputs of the NAND gate 725 and the inverter gate 734 are both at the low level, so that the logic of the signal B is fed back to the output buffer side, and each transistor constituting the output transistor group 720 is output. Is turned on / off according to the logic of both the signal B and the data Din from the internal circuit.

That is, immediately after the logic of the data Din from the internal circuit transitions from the low level to the high level, for example, the logic of the signal B is also at the low level, so that the outputs of the AND gates 722 and 723 are at the low level. The first and second PMOS transistors 715 and 717 are turned on, and the output terminal 714 is driven by these two PMOS transistors. When the potential of the output terminal 714 exceeds the reference voltage INREF and the signal B goes high after a predetermined time, the output of the AND gate 724 goes low, the output of the AND gate 723 goes high, and the second The PMOS transistor 717 is turned off. As a result, the subsequent output terminal 714 is driven only by the first PMOS transistor 715, and the waveform distortion of the data DQ is avoided. [TTL] Next, when the signal CTTM and the signal GTLM are at the high level (TTL mode), the output of the NAND gate 725 is fixed at the high level, the output of the NOR gate 731 is at the low level, and the output of the NAND gate 724 is at the high level. , The transistors constituting the output transistor group 720 operate in parallel according to the logic of the data Din from the internal circuit regardless of the logic of the signal B, and
14 is efficiently driven.

As described above, according to this embodiment,
When the potential of the reference voltage terminal 607 is V _CC or an open state, switch elements 603 and 604 (FIG. 24) for shutting off the power supply current of the comparators 601 and 602 (see FIG. 24) for determining the level of the reference voltage V _REF . ), Power consumption when operating in the TTL mode can be reduced.

A third NMOS transistor 719 is connected in parallel to the first and second NMOS transistors 716 and 718 (see FIG. 28), and the operation of the third NMOS transistor 709 is performed in a predetermined operation mode (for example, T
(TL mode and GTL mode), so that the driving capability of the transistor on the pull-down side in the predetermined operation mode can be increased.

The data input buffer 711 (FIG. 28)
The reference voltage INREF used in reference), V _REF and V
Since the mode is selectively switched to any one of _CTT, the operation of the data input buffer 711 can be stabilized by optimizing the reference voltage INREF for each operation mode.

[0106]

According to the present invention, it is possible to provide an input circuit applicable to both high-speed transfer (emphasis on transfer speed) and low-speed transfer (emphasis on power consumption) and a data transfer circuit including the input circuit. Further, in the present invention, since the determination of the level of the input signal is determined based on the reference voltage _VREF , the operating condition is not affected as long as this reference voltage is stabilized. Further, there is a manufacturing variation (for example, a P-channel type MOS-FET and an N-type
Such as the difference in gm of the channel type MOS-FET).

Further, according to the present invention, two sets of output transistors having optimized internal resistances are selectively used for a signal interface of a small amplitude level (CTT or GTL) and a signal interface of a large amplitude (CMOS or TTL).
A semiconductor integrated circuit that can exhibit performance suitable for each mode and has excellent compatibility (compatibility) can be provided.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention (No. 2).

FIG. 2 is an operation explanatory view of the present invention (part 2).

FIG. 3 is a principle configuration diagram of an embodiment of the present invention (part 1).

FIG. 4 is a configuration diagram of an input circuit according to one embodiment of the present invention (part 1);

FIG. 5 is a diagram showing a preferred example of a transistor size of the input circuit according to one embodiment of the present invention (part 1);

FIG. 6 is a waveform diagram of each part of the input circuit according to the first embodiment of the present invention when a small amplitude signal is input.

FIG. 7 is a waveform diagram of each part when a large amplitude signal is input to the input circuit of one embodiment of the present invention (part 1).

FIG. 8 is a diagram showing correspondence _between threshold values V _th305 and V _th306 with respect to a logical amplitude of an input signal according to the first embodiment of the present invention;

FIG. 9 is a configuration diagram of an input / output circuit including an input circuit according to one embodiment of the present invention (part 1).

10 is an operation waveform diagram of the input / output circuit of FIG.

11 is an operation waveform diagram of an input circuit included in the input / output circuit of FIG.

FIG. 12 is a configuration diagram showing a preferred improved example of the input / output circuit of FIG. 9;

FIG. 13 is another configuration diagram of the differential amplifier circuit included in the input / output circuit of FIG. 9 or 12;

FIG. 14 is a configuration diagram showing another preferable modified example of the input / output circuit of FIG. 9;

FIG. 15 is a configuration diagram of a data transfer circuit including an input circuit according to one embodiment of the present invention (part 1);

FIG. 16 is a configuration diagram of a first embodiment of the present invention (No. 2).

FIG. 17 is a time chart of the first embodiment of the present invention (No. 2).

FIG. 18 shows a mode designation signal CMOS of the present invention (part 2).
3 is an automatic generation circuit diagram of FIG.

FIG. 19 is a configuration diagram of a second embodiment of the present invention (No. 2).

FIG. 20 is a time chart of a second example of the present invention (No. 2).

FIG. 21 is a configuration diagram of a third embodiment of the present invention (No. 2).

FIG. 22 is a time chart of a third embodiment of the present invention (No. 2).

FIG. 23 is a diagram illustrating the principle of the present invention (part 3).

FIG. 24 is an example configuration diagram of a mode determination circuit.

FIG. 25 is a diagram illustrating an example of a configuration of a constant voltage generation circuit.

FIG. 26 is an output signal waveform diagram of the mode determination circuit.

FIG. 27 is an overall configuration diagram of a semiconductor memory showing one embodiment of the present invention (part 3).

FIG. 28 is an example configuration diagram of an input / output circuit of the present invention (part 3).

FIG. 29 is a configuration diagram of an input / output circuit of a first conventional example.

FIG. 30 is a configuration diagram of a CTT circuit of a second conventional example.

FIG. 31 is a conventional configuration diagram of a CTT / GTL circuit of a second conventional example.

FIG. 32 is a configuration diagram of a NOR gate located at the first stage of the input chip of FIG. 29;

[Explanation of symbols]

CMOS: Mode designation signal P ₂₀₀ , P ₂₀₁ , P ₄₄₃ , P ₄₄₄ : Connection point Q ₃₀₁ , Q ₃₀₂ : Differential transistor Q ₃₀₃ , Q ₃₀₄ : Transistor (active load) Q ₃₀₅ : Low-potential side transistor Q ₃₀₆ , Q ₃₀₇ : High potential side transistor V _CC : High potential side power supply V _IN : Input signal V _REF : Reference voltage V _SS : Low potential side power supply V _TT : Termination voltage (constant voltage) V _CTT , V _GTL : Constant voltage 230a, 443a , 715: first PMOS transistors 230b, 443b, 716: first NMOS transistors 231a, 444a, 717: second PMOS transistors 231b, 444b, 718: second NMOS transistors 232, 445: chip internal circuit 233, 446, 491, 491A: ON / OFF control means 234, 453: Signal line 235, 454: Terminating resistor 23 6, 449, 497, 501: mode control means 363, 364: control circuit (first and second control voltage generating means) 493: data line (transmission line) 494, 495: CMOS switch (switching means) 496, 497 : Terminating resistor 498: Decoder (ON / OFF control means) 607: Reference voltage terminal 601, 602: Comparator 603, 604: Switch means 719: Third NMOS transistor

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Yoshioka 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Makoto Koga 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-4-3618 (JP, A) JP-A-4-258020 (JP, A) Fully open Showa 56-142119 (JP, U) Fully open Showa 61-121033 (JP, U) Really open Hei 2-147933 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 19/00-19/23 H03K 17/687

Claims (20)

(57) [Claims] A differential circuit provided between the first and second power supply lines for determining a logic level of an input signal having a first frequency or a second frequency lower than the first frequency; A first power supply line provided between the first power supply line and the differential circuit;
Switch means, and a second switch provided between the second power supply line and the differential circuit.
And switch means for conducting one of the first switch means or the second switch means in response to a logic level of the input signal when the input signal is at the second frequency. A semiconductor integrated circuit comprising: 2. The method according to claim 1, wherein the first and second switch means are transistors, and the control means includes a resistance element having a value larger than an impedance matching load resistance of a bus line outside the semiconductor integrated circuit. The signal of claim 1, wherein the signal is coupled to the gate of the transistor through the resistor.
A semiconductor integrated circuit as described in the above. 3. An input signal that changes at a first frequency or a second frequency lower than the first frequency is applied to one of the control electrodes, and corresponds to a substantially intermediate value of the logical amplitude of the input signal. A pair of differential transistors for applying a reference voltage to the other control electrode, a low-potential-side transistor interposed between the pair of differential transistors and the low-potential-side power supply, A high-potential-side transistor interposed between the low-potential-side transistor and the high-potential-side transistor when the frequency of the input signal is near the first frequency, regardless of the logic state of the input signal Is generated, and when the frequency of the input signal is near the second frequency, the low-potential-side transistor is generated in accordance with the logic state of the input signal. Or semiconductor integrated circuit, characterized in that it and a control voltage generating means for generating a control voltage to one of the ON state of the high side transistor. 4. A comparator circuit for detecting the level of a voltage of an input signal with respect to a reference voltage, between a first power supply and the comparator circuit, and between a second power supply and the comparator circuit. First
And a second transistor, coupled to the control electrodes of the first and second transistors, wherein when the input signal is at a first frequency, the first and second transistors are both conducting and the input signal An input circuit including control means for selectively turning on one of the first and second transistors in response to a logic level of the input signal when is a second frequency lower than the first frequency; And a semiconductor integrated circuit. 5. An input signal having a first logical amplitude or a second logical amplitude larger than the first logical amplitude is applied to one control electrode, and corresponds to a substantially intermediate value of the logical amplitude of the input signal. A pair of differential transistors having a reference voltage applied to the other control electrode; a low-potential-side transistor interposed between the pair of transistors and the low-potential-side power supply; a pair of differential transistors and a high-potential-side power supply And a high-potential-side transistor interposed between the high-potential-side transistor and the low-potential-side transistor, wherein the high-potential-side transistor and the low-potential-side transistor are coupled when the input signal has the first logic amplitude. Side transistors are turned on, and the input signal is
Control means for selectively turning on one of the high-potential side transistor and the low-potential side transistor in response to the logical level of the input signal. 6. A transmission line for transmitting a signal, a voltage source for generating a voltage corresponding to a substantially intermediate value of the first amplitude when the logical amplitude of the signal is the first amplitude, A terminating resistor connected between the transmission line and the voltage source via a predetermined switching means; and a first mode in which the frequency of the signal is a first frequency or the logical amplitude of the signal is the first amplitude. At this time, the switching means is turned on, and the frequency of the signal is set to a second frequency lower than the first frequency or the logical amplitude of the signal is set to a second logical amplitude larger than the first amplitude. An on / off control means for turning off the switching means in the second mode. 7. A first PMOS transistor and a first NM connected in series between a high-potential power supply and a low-potential power supply.
An OS transistor; a second PMOS transistor and a second NMOS transistor, which are also connected in series between the high-potential power supply and the low-potential power supply; On / off control means for turning on / off, the first PMOS transistor and the first NMOS
Both the connection point of the transistor and the connection point of the second PMOS transistor and the second NMOS transistor are connected to the signal line, and the signal line is driven by the selective on / off operation of the four transistors. In the semiconductor integrated circuit, when a mode designating signal indicates a first transfer mode in which a terminating resistor is connected between the signal line and a predetermined constant voltage, the first PMOS transistor or While controlling the signal line to be driven by a first NMOS transistor, while the mode designation signal indicates a second transfer mode in which the signal line is used without being connected to the terminating resistor, The second PMOS transistor or the second N
A semiconductor integrated circuit, comprising: mode control means for controlling the signal line to be driven by a MOS transistor. 8. The mode control means according to claim 1, wherein said mode designation signal indicates a second transfer mode when said first P mode is selected.
8. The semiconductor integrated circuit according to claim 7, wherein the signal line is controlled to be driven by a MOS transistor and a second PMOS transistor or a first NMOS transistor and a second NMOS transistor. 9. A comparator for comparing a potential of a reference voltage terminal of a chip with a predetermined constant voltage and generating the mode designation signal having a logic state according to the comparison result, and a power supply current of the comparator can be cut off. 8. The semiconductor integrated circuit according to claim 7, further comprising switch means, wherein the switch means is turned off when the potential of the reference voltage terminal of the chip is at a predetermined high potential or in an open state. 10. When the mode designating signal indicates the first transfer mode, the potential of the reference terminal of the chip at that time is used as the reference voltage of the input buffer circuit. 8. The semiconductor integrated circuit according to claim 7, wherein when the second transfer mode is displayed, an intermediate potential of the power supply voltage is used as a reference voltage of the input buffer circuit. 11. When a third NMOS transistor is connected in parallel with said first NMOS transistor, and a mode designation signal indicates said first transfer mode,
And when the first NMOS transistor is turned on,
8. The semiconductor integrated circuit according to claim 7, wherein said third NMOS transistors are turned on simultaneously. 12. An input circuit for determining a logic level of an input signal based on a reference voltage; a mode determination circuit for generating a mode designating signal based on a voltage value of a reference voltage terminal; Means for selecting one of a voltage applied to the reference voltage terminal and an internally generated internal reference voltage, and supplying the selected voltage as the reference voltage to the input circuit. Semiconductor integrated circuit. 13. The semiconductor integrated circuit according to claim 1, wherein the amplitude of the input signal having the first frequency is smaller than the amplitude of the input signal having the second frequency. 14. The input circuit receives the internal reference voltage as the reference voltage when the mode determination circuit detects that no voltage is applied to the reference voltage terminal. 13. The semiconductor integrated circuit according to claim 12, wherein when detecting that a voltage is applied to the reference voltage terminal, receiving the voltage applied to the reference voltage terminal as the reference voltage. 15. The semiconductor integrated circuit according to claim 12, further comprising an output circuit for switching a driving force based on said mode designation signal. 16. An input circuit for determining a logic level of an input signal based on a reference voltage, a mode determination circuit for generating a mode designation signal based on a voltage value of a reference voltage terminal, and a voltage generator for generating an internal reference voltage A circuit for selecting one of an external reference voltage applied to the reference voltage terminal and the internal reference voltage in response to the mode designation signal, and supplying the selected voltage as the reference voltage to the input circuit; And an output circuit for switching a driving force based on the mode designation signal. 17. A comparator for judging a voltage value of the external reference voltage, wherein the mode judging circuit conducts when the external reference voltage is supplied to the reference voltage terminal, and supplies the power supply voltage to the comparator. 17. A semiconductor integrated circuit according to claim 16, further comprising: power supply control means for supplying power to said comparator and shutting off a power supply voltage to said comparator when said reference voltage terminal is open. 18. The first PMOS transistor and a first PMOS transistor
The on-resistance of the NMOS transistor is set based on the signal amplitude on the signal line in the first transfer mode and the value of the terminating resistance, and the on-resistance of the second PMOS transistor and the second NMOS transistor is set. 8. The semiconductor integrated circuit according to claim 7, wherein the setting is performed based on a signal amplitude on a signal line in the second transfer mode. 19. A first CMOS connected in parallel with each other
An output buffer circuit and a second CMOS output buffer circuit; control means for controlling the first CMOS output buffer circuit and the second CMOS output buffer circuit in response to an operation mode signal; and the first CMOS output buffer The output of the circuit and the second
A semiconductor integrated circuit having a signal line connected to an output of a CMOS output buffer circuit, wherein the operation mode signal is used by connecting a terminating resistor between the signal line and a predetermined constant voltage. In the transfer mode, the control means supplies a control signal to the first CMOS output buffer circuit to drive the signal line, and the operation mode signal is used without connecting the signal line to the terminating resistor. A second transfer mode, wherein the control means supplies a control signal to the second CMOS output buffer circuit to drive the signal line. 20. The semiconductor integrated circuit according to claim 19, wherein a driving force of said first CMOS output buffer circuit is smaller than a driving force of said second CMOS output buffer circuit.