JP2806166B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a clock signal wiring.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, as shown in FIG. 2, a clock signal is supplied from a clock driver 9 to an internal circuit block 6 which requires a clock signal by using a wiring dedicated to the clock signal. Was. As a countermeasure against a clock skew problem caused by an increase in aluminum wiring delay due to recent miniaturization of a semiconductor integrated circuit, a clock driver is formed by forming clock signal wiring in an H-shaped tree as shown in FIG. The wiring lengths from 9 to each internal circuit block 6 can be made substantially the same, thereby reducing clock skew.

[0003]

In the above-described first example of the conventional semiconductor integrated circuit, the wiring lengths from the clock driver to the internal circuit block are different from each other. There is a disadvantage that the clock skew increases and in the worst case, the circuit malfunctions.

In order to compensate for the above drawback, there is a method of reducing the clock skew by increasing the width of the wiring for transmitting the clock signal so as to reduce the wiring delay. In contrast to this, a considerably large wiring area is required. Further, the second example of the conventional semiconductor integrated circuit which takes measures against clock skew requires a wide wiring area, and furthermore, this method cannot be used in a standard cell in which macros are arranged on a chip. is there.

[0005]

A semiconductor integrated circuit according to the present invention includes a main power supply line provided on a semiconductor substrate for supplying a combined signal obtained by combining a DC voltage and a clock signal, and a main power supply line connected to the main power supply line. A low-pass filter that separates a DC voltage from the synthesized signal and supplies it to an internal power supply wiring; and a comparator that is connected to the main power supply wiring and separates a clock signal from the synthesized signal and supplies it to an internal circuit block.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram for explaining an embodiment of the present invention.

As shown in FIG. 1, a main power supply line 2 is provided on a semiconductor chip 10 for supplying a combined signal obtained by combining a DC voltage V _DD and a clock signal 8. A low-pass filter 5 that separates a DC voltage and supplies it to an internal power supply wiring 3; and an internal circuit block 6 that is connected to the main power supply wiring 2 to separate and shape a clock signal from a synthesized signal.
And a comparator 4 that supplies the data to the comparator 4.

Here, the composite signal is obtained by superimposing a clock sine wave 8 having a clock frequency having an amplitude of ± 0.5 V on the DC voltage V _DD = 5 V in consideration of the threshold voltage of the transistor and the like. Circuit block 6 that supplies
, The arrangement of the comparator 4 is selected so that the length of the signal wiring is shortened.

[0010]

As described above, according to the present invention, the clock skew caused by the wiring delay can be reduced by placing the clock signal on the main power supply wiring to reduce the wiring resistance by using a power supply wiring thicker than the signal wiring. Can be reduced.

Further, by using many comparators for shaping a clock frequency wave into a digital clock signal or by effectively arranging the comparators, the clock skew can be controlled to be considerably small.

In addition, since a dedicated wiring for supplying a clock signal is not required, there is an effect that the degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a first example of a conventional semiconductor integrated circuit.

FIG. 3 is a schematic diagram for explaining a second example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 2 Main power supply wiring 3 Internal power supply wiring 4 Comparator 5 Low-pass filter 6 Internal circuit block 8 Clock sine wave 9 Clock driver 10 Semiconductor chip

Claims (1)

(57) [Claims] A main power supply line provided on a semiconductor substrate for supplying a combined signal obtained by combining a DC voltage and a clock signal; and a DC voltage separated from the combined signal connected to the main power supply line and connected to an internal power supply line. A semiconductor integrated circuit comprising: a low-pass filter to be supplied; and a comparator connected to the main power supply line, separating a clock signal from the synthesized signal and supplying the separated clock signal to an internal circuit block.