JP2803616B2 - I / O bus interface control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input / output bus (also referred to as an "I / O bus") interface control method in an information processing apparatus (also referred to as a "multiprocessor system") using a plurality of microprocessors.

[0002]

2. Description of the Related Art In a multiprocessor system,
Generally, a multiprocessor bus hierarchy in which a plurality of arithmetic processing unit (EPU) modules and a main storage module are bus-connected, and a plurality of input / output devices (also referred to as “I / O devices”)
Are often composed of an I / O bus layer connected to the bus and an I / O bus interface control mechanism connecting these two layers.

FIG. 7 is a diagram showing a typical configuration of a multiprocessor system.

Referring to FIG. 7, an EPU module 65-1 comprises a microprocessor (MPU) 63-1 and a multiprocessor bus interface controller (BIC) 64-1.
The other EPU modules 65-2 to 65-n have the same configuration,
The plurality of EPU modules 65-1 to 65-n are connected to a multiprocessor bus 68. Main memory (MM)
Main memory module (MM) consisting of 66-1 and controller 66-2
C) 67 is connected to the multiprocessor bus 68, while a plurality of I / O devices 69-1,..., 69-n are connected to the I / O bus 70 in parallel, and bus
70 is an I / O bus interface controller (I / O
C) Connected via 71.

FIG. 8 shows an example of the configuration of a conventional I / O bus interface control device 71. A multiprocessor bus control unit 72 is connected to a multiprocessor bus 68 of a split control system and has a transmission destination. It has a function of storing four commands consisting of an address, command information (read / write type, data length, etc.) and transmission data (in the case of a write command) in the order in which they are issued on the multiprocessor bus 68. Type (First In First Ou
t; “FIFO”) is connected to the I / O bus 70 via an I / O bus control unit 74 via a transmission buffer 73 consisting of a register.

The I / O bus control unit 74 further includes a reception buffer 75 comprising a four-stage first-in first-out (FIFO) register having a function of storing four commands in the order of issuance on the I / O bus 70. Multiprocessor bus control unit 72
And is connected to a multiprocessor bus 68.

Each stage of the transmission buffer 73 and the reception buffer 75 is naturally occupied until the written command is read from the control unit on the reading side, and writing is disabled.

The operation of the conventional I / O bus interface controller 71 shown in FIG. 8 is as follows.

(1) Read (read) access from the EPU to the I / O device The multiprocessor bus control unit 72
When a read command from 68 to the I / O bus 70 is received,
If all stages of the transmission buffer 73 are not in the occupied state, a read command is written to the transmission buffer 73.

Since the multiprocessor bus 68 is a split control system, after writing a read command to the transmission buffer 73, the multiprocessor bus control unit 72 releases the multiprocessor bus 68.

On the other hand, if all stages of the transmission buffer 73 are occupied and a command cannot be written, a command instructing retry and a command to the multiprocessor bus 68 are transmitted to release the bus.

An I / O bus control unit 74 reads a read command from the transmission buffer 73 in a first-in first-out manner, and
A read command is transmitted to the bus 70.

When receiving a response from the I / O device to the read command as read data from the I / O bus 70, the I / O bus control unit 74 writes an answer command including the read data in the reception buffer 75, I / O bus
Release 70.

The multiprocessor bus control unit 72 reads an answer command from the reception buffer 75, returns read data to the multiprocessor bus 68, and releases the bus.

(2) Write (Write) Access from EPU to I / O Upon receiving a write command from the multiprocessor bus 68 to the I / O bus 70, the multiprocessor bus control unit 72 If the stage is not occupied, a command is written to release the multiprocessor bus 68.

If all the stages of the transmission buffer 73 are occupied and a command cannot be written, a command instructing retry is returned to the multiprocessor bus 68 to release the bus.

The I / O bus controller 74 reads a write command from the transmission buffer 73 and transfers it to the I / O bus 70.
Release the bus after transfer.

[0018]

The above-mentioned conventional I / O
The first problem in the bus interface control device is as follows.
When an operation unique to a multiprocessor system, “simultaneous access from a plurality of MPUs to each other I / O on an I / O bus” occurs, the operation to one I / O becomes a bottleneck, Other I / O operations that can be performed simultaneously with this I / O operation are hindered, and as a result, the MPU performing those I / O operations enters a wait state and a plurality of MPs
This means that the advantage inherent in the multiprocessor system, that is, the parallel operation of U, is diminished, and the performance of the system is reduced. The reason will be described below.

That is, the I / O bus interface control device according to the prior art described above performs first-in first-out (FI-FI) upon command buffering from the MPU to the I / O bus.
Since the basic function of the register having the (FO) structure is used as it is as a buffer unit, this buffer unit has a serial matrix structure, and if the processing of the previously buffered command is not completed on the I / O bus, this buffer unit is used. This is because there is no need to preserve the order between the command and the subsequent command, and therefore, even if simultaneous execution is possible, the subsequent command cannot be executed.

With reference to FIGS. 7 and 8, problems in the case where the conventional I / O bus interface control mechanism is used will be described in detail below using an operation example.

Now, a series of write commands WT11-1... 4 from the MPU 63-1 to the I / O device 69-1 and a series of write commands WT22-1. Has been issued. These commands are sent to the WT on the transmission buffer 73 by the bus arbitration of the multiprocessor bus 68 and the buffer control of the I / O bus interface controller 71.
11-1, WT22-1, WT11-2, and WT22-2 are serially buffered, and subsequent commands receive a retry response from the I / O bus interface control unit 71 once, and the EPU modules 65-1, 65-n Can be put on hold.

At this time, the I / O bus controller 74 reads the first write command WT11-1 from the transmission buffer 73 and transfers it to the I / O device 69-1. After the reception completion response, the I / O bus 70 is released to start the operation.

Next, the I / O bus control unit 74 reads the write command WT22-1, transmits the read command to the I / O device 69-2,
Upon receiving the reception completion response, the I / O device 69-2 releases the I / O bus 70, starts the operation, and ends immediately.

Next, the I / O bus control unit 74 issues a command WT
11-2 is read out and is to be transferred to the I / O device 69-1, but the I / O device 69-1 has not received the write command WT11-2 because the operation by the previous command WT11-1 has not been completed. No, and as a result, a response is
Release the O bus 70.

For this reason, the write command WT11-2 is held in the transmission buffer 73.

The transmission buffer 73 is a register having a FIFO structure. Since the I / O bus control unit 74 has no overtaking means, it cannot perform the overtaking transfer, and the operation after the command WT 22-2 which can be executed simultaneously can be prevented ( The EPU 63-2 which is blocked and does not need to be stopped logically falls into a stopped state due to the low-speed I / O device 69-1.

Accordingly, the present invention has been made in view of the above-mentioned problems of the related art, and is intended to be applied to a case where a plurality of MPUs simultaneously access different I / Os in a multiprocessor system. Since access to other I / O devices is suppressed by a low-speed I / O device (refer to the above-described related art), access to the I / O device which does not need to be logically stopped is originally performed. Doing, MP
I / O bus interface control system for improving the performance of a multi-processor system by improving the parallel operation rate of a plurality of MPUs that are impaired when simultaneous I / O access occurs by enabling the U to operate The purpose is to provide.

[0028]

In order to achieve the above object, the present invention provides a multiprocessor bus in which a plurality of microprocessors are connected in parallel, and an input / output bus in which one or more input / output devices are connected. And a transmission buffer for sequentially storing commands for the input / output device issued from the microprocessor, and a transmission buffer before the transmission destination based on the address information of the command stored in the transmission buffer. Means for specifying the channel information of the entry / output device, determining the possibility of overtaking among the plurality of commands stored in the transmission buffer based on the channel information, and saving the command to be overtaken by the subsequent command An input / output bus interface control method is provided.

An outline of the present invention will be described with reference to FIG. 1 showing a preferred embodiment.

The input / output bus interface control system according to the present invention is preferably arranged such that the multiprocessor bus control unit (3, see FIG. 1), the multiprocessor bus (1) to the I
A transmission buffer (4) for storing a transmission command to the / O bus (10), a transmission hold buffer (5) for storing a retry command, an I / O bus control unit (6), a channel information determination unit (7), The overtaking execution determining means (8) comprises a receiving buffer (9) for storing received commands to the multiprocessor bus (1).

The channel information judging means (7) is an address space unit (referred to as a "channel") for preserving the order on the multiprocessor bus (1) between commands stored in the transmission buffer (4). A register for holding information, which can be set by executing a predetermined instruction of software or the like, is provided. Based on the channel information and the destination address information of the command stored in the transmission buffer (4), the overtaking execution determining means (8) In step ()), a command that can be overtaken is determined.

When the I / O bus control unit (6) receives a response instructing retry in response to the command transmitted to the I / O bus (3), it is determined that the succeeding transmission command can be overtaken. If this is the case, it has a function of executing the overtaking, and a function of executing the command which has received the retry response stored in the transmission hold buffer (5) after the overtaking.

[0033]

According to the present invention, (a) it is possible to buffer a plurality of commands in a transmission buffer;
(B) the address information of the command buffered in the transmission buffer can be read ahead, and (c)
Since the information of the address range in which the order of input to the buffer needs to be preserved between commands is stored in the register, it is possible to determine the possibility of overtaking between the buffered commands.

Further, according to the present invention, since there is a mechanism for saving the command to be overtaken and a function for executing the saved command again, there is no need to preserve the order, and the first-in first-out type is used. The execution order of the commands buffered adjacent to the buffer having the (FIFO) structure can be exchanged.

With this function, when the command located at the first stage of the transmission buffer receives a retry response from the I / O bus and is suspended, the command located at the next stage of the buffer becomes the suspended command. When the execution order can be exchanged, the next command can be overtaken. When the exchange cannot be executed, the execution of the first command can be waited.

[0036]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an input / output bus interface control device (also referred to as an I / O bus interface unit) according to an embodiment of the present invention. FIG.
FIG. 3 is a diagram showing the configuration shown in FIG. 1 in more detail. In the case where the transmission buffer 4 of FIG. 1 has a two-stage structure, the transmission buffer 4, the channel information determination unit 7, and the overtaking execution determination unit 8 It is a figure showing a detailed composition.

In general, in the transmission of a command to an I / O device, the transmission order itself is related to the control of the I / O device. Therefore, the transmission order must be stored from the MPU to the I / O device. There is.

An I / O operation that occurs when a program on one MPU is executed consists of a plurality of I / O commands.
During the I / O operation, the address space in which the above-mentioned transmission order, which can be accessed by a command, should be preserved, is limited, and this address space is usually occupied by one I / O device. The address space is a whole or a part of the address space, and this address space is called a “channel”.

In a multiprocessor system, due to its operation characteristics, I / O commands transmitted on the multiprocessor bus 1 can be transmitted simultaneously to different channels. It is not always necessary to preserve the command issuing order on the multiprocessor bus 1 between each other.

Therefore, the I / O bus interface control unit 2 holds, as channel identification information, address space information occupied by each channel, that is, the base address (base address) of the channel and its size (size). By determining the channel from the address of
Since it is known whether or not it is necessary to preserve the order input from the multiprocessor bus 1 among a plurality of commands buffered in the I / O bus interface control unit 2, the overtaking execution between the commands is performed. Can be determined.

In the system according to the present embodiment, this channel identification information is stored in the I / O bus when the system is initialized.
The values are set in the channel information registers 11-1 to 11-n (see FIG. 2) in the channel information determination unit 7 for each channel on the channel 10.

In FIG. 2, the channel information determination unit 7
Channel information registers provided for each channel
11-1 to 11-n and a transmission channel determination unit 12-1-1 to 12-2-n, and the transmission channel determination unit
A transmission channel determination unit 12-1-1 to 12-1-n which receives the address of the command of the stage 4-1 and a transmission buffer second stage 4-2
Channel determination unit that receives the address of the command
12-2-1 to 12-2-n.

The channel information registers 11-1 to 11-n include channel n base address registers 13-1 to 13-n and channel n size registers 14-1 to 14-n, respectively.

In each case, reading and writing can be performed from an MPU (not shown) of an EPU (not shown) connected to the multiprocessor bus 1 via the multiprocessor bus control unit 3, and the bytes of the address space occupied by the channel n by software. An address and its size (for example, "byte size-1") are set for each.

The transmission channel determination units 12-1-n to 12-2-n receive the data in the multiprocessor bus control unit 3,
The destination address of the transmission command including the command type information (read / write), transmission destination address, and data (only in the case of the write command) written in the channel n information registers 11-1 to 11-n. By comparing (base address and size) with a circuit as shown in FIG. 2, the destination channel of the command can be determined, and the result is transmitted to the overtaking execution determination unit 8.

More specifically, assuming that the address space of channel 1 is, for example, a 32-bit space and is 256 KBytes with "E0000000"(HEX; hexadecimal notation) as a base address, the channel 1 base address register 13-1
The content BAD (0:31) is "E0000000" and the content SIZ (0:31) of the channel 1 size register 14-1 is the space size (256K-1)
Is set. Of the command input to the transmission buffer 4
Assuming that the 32-bit address is AD (0:31), the signal output from the transmission channel determining unit 12-1-1 (the High level when the channel 1 is determined) is ([AD (0:31) .XNOR. BAD (0: 3
1)]. OR.SIZ (0:31)) for each bit. An exclusive NOR (XN) of the command address (AD (0:31)) and the base address (BAD (0:31))
OR), the unmatched bit is set to “0”, but in this case, by performing an OR operation with “1” of SIZ (0:31), if the bit is within the space size, it is present in the channel. And the address of the command is channel 1
, The High level output is input from the transmission channel determination unit 12-1-1 to the overtaking execution determination unit 8.

If the destination channel of the valid transmission command stored in the transmission buffer 4 is different between the currently executed command and the next command, the overtaking execution determining unit 8 determines whether the passing command can be executed, and passes the PASS signal. 22 is transmitted to the I / O bus control unit 6.

As shown in FIG. 2, the overtaking execution determination unit 8
The output of the transmission channel determination units 12-1-1 to 12-1-n which receive the address of the command of the first stage 4-1 of the transmission buffer and the signal from the transmission buffer 4-1 (RQ1: valid to be transferred) Is activated when there is a unique command).
And a transmission channel determination unit 12-2-1 which receives the address of the command of the second stage 4-2 of the transmission buffer as an input.
~ 12-2-n output and signal from transmission buffer 4-2 (RQ
2: Activated when there is a valid command to be transferred). The outputs of the second group of AND gates having the input 16 and the outputs of the first group and the second group of the AND gates are input as input for each channel. The n exclusive NOR circuits (XNOR) to be detected and the n exclusive NOR circuits (XN
OR) outputs a high-level signal as a PASS signal 22 when both outputs are at the non-coincidence (Low) level.

The transmission buffer 4 and the reception buffer 7 are both constituted by first-in first-out (FIFO) registers.

The transmission buffer 4 stores a transmission command from the multiprocessor bus 1 to the I / O bus 10, and is used for both read and write commands. The reception buffer 7 is used for storing a reception command as read data from the I / O bus 3 to the multiprocessor bus 1.

Next, the operation of this embodiment shown in FIGS. 1 and 2 will be described with reference to the time charts of FIGS. 3 and 4 and the flowchart of FIG.

The STAT shown on line 28 in FIGS.
E (state) indicates the state of the I / O bus control unit 6 in FIG.

In the multiprocessor bus control unit 3, I / O
Upon detecting the transmission command C ₁ to the bus 10, the transmit buffer 4 made it from first-in-first-out (FIFO) register
Write to.

At this time, the first stage 4-1 of the transmission buffer (FIG. 2)
(See FIG. 3, FIG. 3).
The RQ1 signal 15 (see FIG. 2) shown in FIG. 4) is asserted (in this case, the active state is the High level). This is a transmission request signal to the I / O bus control unit 6.

When the writing is completed, the write pointer 16 of the transmission buffer 4 (see FIG. 2) becomes
Connect the stage 4-2 side to the input line.

Next, the multiprocessor bus control unit 3
In, upon detecting the transmission command C ₂ to the next I / O bus 10 is written to the transmit similar buffer second stage 4-2 (see FIG. 2), indicated by the line 30 (see FIGS. 3 and 4) The RQ2 signal 17 (see FIG. 2) is asserted. Write pointer
16 moves to the transmission buffer first stage 4-1 side.

The address information of the command written in the transmission buffer 4 is compared with the channel identification information set at the time of system initialization in the channel information registers 11-1 to 11-n via the address signal lines AD1, AD218 and 19. Are performed by the transmission channel determination units 12-1-1 to 12-2-n, and the results are the destination channel identification signal lines 20-1 to 20-n and 211-1 to 21-n (see FIG. 2). CD1, CD2 of 31, 32 (see FIGS. 3 and 4)
The signal is notified to the overtaking execution determining unit 8 via a signal line, and as shown in FIG. 2, a line 33 (FIGS. 3 and 4) which is an overtaking executable determination signal.
The PASS signal 22 of the I / O bus controller 6 is generated.
Will be notified.

In FIGS. 3 and 4, it is determined that CD = 1 can be overtaken by channel 2 and CD2 can be overtaken by channel 1 (PASS signal is at High level).

[0060] I / O bus control unit 6, when RQ1 signal line 28 (see FIGS. 3 and 4) is asserted at a timing 34, detects the transmission request of the transmission command C _1. The following operation differs depending on whether the command is a read access or a write access.

(1) In case of write access (refer to the time chart of FIG. 3) The I / O bus control unit 6 sends the I / O bus 10 (see FIG.
The transmitted reference) command C _1, the AS signal destination address / command type (read / write) line 36 indicating a signal transmission timing asserted at the timing 37, the destination address / command type A _1, the data D ₁ Send in order.

At the same time, the transmission command C ₁ is sent to line 38.
(See FIG. 3), and is stored in the transmission hold buffer 5 (see FIG. 2). I / O bus control unit 6, I / O sent from the bus 10 command C ₁ to line 39, upon receiving a READY signal indicating the completion of reception of the timing 40, the next transfer request, the operation by RQ2 line 30 (See FIG. 3A).

On the other hand, in response to the transmission command C ₁ , when the RETRY signal on the line 41 indicating that reception is not possible and requesting a retry is received at the timing 42 (see FIG. 3B), When the assertion of the PASS signal is detected at the timing 43, the command based on the transmission request RQ2 of the subsequent line 30 and the timing 44 is overtaken.

[0064] That is, with respect to I / O bus 10 of the line 35, and transmits the destination address / command type A ₂ at the timing 45 with AS signal on line 36 indicating the timing.

After the passing, the transmission hold buffer 5 (FIG. 3)
In (B), the transmission operation of the command written in the line 38 is started.

On the other hand, in FIG.
If ASS signal has not been asserted at the timing 43, ignoring the subsequent request RQ2 transmission of the transmission suspension command C ₁ stored in the buffer 5 line 30 to RE
Perform until the reception of the ADY signal.

(2) In case of read access (refer to the time chart of FIG. 4) The I / O bus control unit 6 sends the transmission command C ₁ to the I / O bus 10 of the line 35 and the transmission destination address / command type A ₁ At the timing 46 together with the AS signal on the line 36 indicating the timing.

At the same time, the transmission command C ₁ is
(See FIG. 4A). The I / O bus controller 6 controls the I / O bus 10 of the line 35
To transmit command C ₁ on (see FIG. 1), the timing 4
READ indicating the completion of reception of the response data D ₁ and the line 39 with 7
When detecting the assertion of the Y signal is written to the receive buffer 9 the response data D ₁ as the answer command.

The multiprocessor bus control unit 3 reads an answer command in response to a request from the reception buffer 9 and
The read data is transmitted to the multiprocessor bus 1.

On the other hand, when the RETRY signal on the line 41 which indicates that the transmission command C1 cannot be received and requests retrying is received at the timing 48 (see FIG. 4B), and the PASS signal on the line 33 is received. When detected at the timing 49, the transmission request R at the timing 50 indicated by the subsequent line 30
The command by Q2 is overtaken.

[0071] That is, with respect to I / O bus 10 of the line 35, and transmits the destination address / command type A ₂ at the timing 51 with AS signal on line 36 indicating the timing.

After the overtaking, the operation for transmitting the command written in the transmission hold buffer 5 (see FIG. 2; see line 38 in FIG. 4B) is started (see timing 52 in FIG. 4B).

If the PASS signal on the line 33 is not asserted at the timing 49, the subsequent request signal RQ2 on the line 30 is ignored and the transmission hold buffer 5 (see FIG. 2; see FIG. 4 (B), see the line 38). transmits the stored command C ₁ to READY signal reception (optional time chart).

Next, referring to the flowchart of FIG.
This embodiment will be further described. This is the I / O bus controller 6
FIG. 4 is a diagram (state transition diagram) showing transition of the operation state of FIG.

The IDLE 53 is a state in which a transmission request has not been input to the I / O bus control unit 6, and the initial state is always this state.

REQ 54 is a step for determining whether any of the transmission request signals RQ 1 and RQ 2 (18, 19) is asserted from the transmission buffer 4. When there is a transmission request, the process proceeds to the next state AD55, and when there is no transmission request, the process returns to IDLE53.

The AD 55 is a state for transmitting the address / command type on the I / O bus, and unconditionally proceeds to a state DT 56 for transmitting / receiving (write / read) data on the next I / O bus.

This state is a READY signal indicating completion of reception from the I / O bus or a RETR requesting retry.
(Retry) The process ends when any of the Y signals is asserted, and transitions to the next state as shown in FIG.

In particular, RETRY is asserted and NRE
In Q57, if it is determined that there is a transfer request other than the transfer request currently being transferred, the process proceeds to PASS58, and if the PASS signal 22 indicating that the succeeding transfer request indicates that overtaking transfer is permitted, the overtaking execution state is determined. To PAD59 and PAD60.

Transmission of the address / command type and transmission of data are performed. When the overtaking execution state ends, the process proceeds to retry transfer states RAD61 and RDT62. In this state, the I / O bus output selector 24 (see FIG. 2) outputs from the transfer hold buffer 5 side, and the operation of the I / O bus is the same as that of the PAD59 and RAD60, respectively.

FIG. 6 is a diagram for explaining the second embodiment of the present invention. FIG. 6 (A) shows an example in which the transmission hold buffer 5 shown in FIG. FIG. 3 is a diagram showing a configuration in which the structure and control of FIG.

The read pointer 23 operates in response to the RD control signal from the I / O bus control unit 6 to indicate the buffer stage to be read, as in the first embodiment. The output line 77 has a structure capable of outputting the stage of "pointer indicated value -1", and the output selector 78 determines which of the normal instruction output line 76 and the indicated mesher 1 output line 77 is to be output. / O bus controller 6
Control.

FIG. 6B is a timing chart for explaining the operation when this embodiment is incorporated in the first embodiment, and is a time chart corresponding to FIG. 3B.

The present embodiment is different from the first embodiment in that, at the timing 88 of the read pointer indicating value of the line 82, the state transition point of the I / O bus controller 6 in the first embodiment is different. AD → DT, PAD → PDT, RA
Although the RD signal for moving the pointer is issued from D to RDT, in the present embodiment, the pointer is not moved from PAD to PDT.

The newly provided output selector 78 (FIG. 6)
(See line 83 in (B)).
"Instruction minus 1 output line" is indicated in the states PDT and RAD of the I / O bus control unit 6 of FIG. With this structure, the same effect as in the first embodiment can be obtained.

[0086]

As described above, according to the present invention, since the command overtaking can be executed, which has not been realized by the conventional I / O bus interface control mechanism, the execution of the preceding command is suspended. However, since the subsequent command is not suppressed, and the wait time of the MPU that issues the subsequent command is reduced, a plurality of PMUs can be provided in the multiprocessor system.
From each other, when access to different I / Os occurs,
It is possible to improve the I / O performance and the parallel operation rate of the MPU in the system, and it is possible to improve the system performance.

Further, according to the present invention, information on an address range in which the order between buffered commands needs to be preserved is held in an internal register, and the possibility of command overtaking is determined using this information. With this configuration, the execution order can be preserved while the command can be overtaken, and the single I / O access from the same MPU, in which the execution order should be preserved, retains this order as before. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail configurations of a transmission buffer, a channel information determination unit, and an overtaking execution determination unit, which are main components of one embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of the embodiment of the present invention. FIG. 9A is a timing chart when a write operation is completed normally. (B) is a timing chart in a case where overtaking occurs due to a retry response.

FIG. 4 is a time chart when the write operation in FIG. 3 is a read operation;

FIG. 5 is a flowchart illustrating a state transition of an I / O bus control unit according to an embodiment of the present invention.

FIG. 6A is a diagram illustrating a configuration of a transmission buffer according to another embodiment of the present invention. (B) A time chart for explaining the operation of another embodiment of the present invention.

FIG. 7 is a block diagram showing a general configuration of a multiprocessor system.

FIG. 8 is a diagram schematically showing a configuration of an I / O bus interface control device according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiprocessor bus 2 I / O bus interface control device 3 Multiprocessor bus control unit 4 Transmission buffer 5 I / O bus control unit 6 Transmission hold buffer 7 Channel information judgment unit 8 Passing execution judgment unit 9 Reception buffer

Claims (4)

(57) [Claims] 1. A method for controlling an input / output interface between a multiprocessor bus to which a plurality of microprocessors are connected in parallel and an input / output bus to which one or more input / output devices are connected, wherein A transmission buffer for sequentially storing commands for the input / output device issued from a processor, and specifying channel information of the destination input / output device from address information of the command stored in the transmission buffer,
Means for determining the possibility of overtaking among a plurality of commands stored in the transmission buffer based on the channel information; and means for evacuating commands overtaken by a subsequent command. I / O bus interface control method. 2. The method according to claim 1, wherein when the channel information of the transmission destinations of the plurality of commands stored in the transmission buffer is the same, it is determined that overtaking between the commands is impossible. 1. The input / output bus interface control method according to 1. 3. A method for controlling an input / output interface of a multiprocessor bus to which a plurality of microprocessors are connected in parallel and an I / O bus to which one or more input / output devices are connected, A plurality of commands from the multiprocessor bus are stored in the order of writing, and are composed of a register array that can be read in that order. Information on any of the stored commands is read from the outside regardless of the read row position. An enabled transmission buffer, a space information register that holds an address serving as a starting point, and a size from the starting point to the ending point or an address serving as an ending point, and defines an address space; and reading from a predetermined line of the transmitting buffer. Address to which the address of the issued command information and the address input from the value of the space information register belong. And a match / mismatch of the address space information of the command stored in the adjacent row of the transmission buffer generated by the channel decision unit. And a transmission suspension buffer that stores the command read from the transmission buffer and enables the same command to be read again. The command is read from the transmission buffer, transmitted to the input / output bus, and transmitted to the input / output bus. Is stored in the transmission hold buffer, and when the transmitted command receives a response from the input / output bus requesting that reception be impossible or a retry be performed, and when the command is suspended, the subsequent command to be transmitted further includes the transmission buffer. And the succeeding command is in the execution If it is determined that the overtaking is possible, the subsequent command is transmitted first, and after completion of the subsequent command, the command stored in the transmission suspension buffer and the When re-transmitting to the entry output bus, the succeeding command is determined to be unexecutable by the overtaking execution determination unit with respect to the command whose execution has been suspended, or a subsequent command to be transmitted. An input / output bus interface, comprising: an input / output bus control unit for retransmitting the command held in the transmission hold buffer when the command is not present in the transmission buffer and reserving the execution pending command. control method. 4. A plurality of commands from the multiprocessor bus are stored in the order of writing, and are constituted by a register array readable in the order, and a pointer indicated by a pointer counter for indicating a read line or a pointer indicated by the pointer indicated by a pointer. A transmission buffer in which any one of the buffer rows of the subtracted value can be read by an external designation, and information of any of the stored commands can be externally read regardless of the position of the read row. Read a command from the transmission buffer, transmit the command to the input / output bus, receive a response from the input / output bus requesting that the command be unreceivable or retrying, and, when the command is put on hold, A command is in the transmission buffer, and the command is When the line determination unit determines that passing is possible, the subsequent command is transmitted, and after the completion of the command, the read line of the transmission buffer is read, and a value obtained by subtracting 1 from the pointer indicated value is selected. Retransmitting the command whose execution has been suspended, there is a subsequent command to be transmitted, and the command whose execution is suspended is determined by the overtaking execution determination unit. If it is determined that passing is not possible, or if there is no subsequent command to be transmitted in the transmission buffer, the read line of the transmission buffer is read and the value of the pointer minus one is selected. 4. The input / output bus interface according to claim 3, further comprising an input / output bus control unit that retransmits the command whose execution is suspended. To control system.