JP2800884B2 - Semiconductor device having lateral DSA power MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a unit cell structure of a lateral DSA (double diffusion self-alignment type) power MOSFET (insulated gate field effect transistor).

[0002]

2. Description of the Related Art A lateral DSA power MOSFET defines a channel length in a self-aligned manner by double diffusion of impurities on the surface of a semiconductor substrate using an insulating gate as a mask. As shown in the cross-sectional views taken along the line II-II ′ of FIG.
Japanese Patent Application Laid-Open No. 2 (hereinafter referred to as Conventional Example 1) discloses an arrangement arranged in a deformed stripe shape. As shown in the plan view of FIG. 7 and the cross-sectional view taken along the line IV-IV ′ of FIG. 8 in FIG. Are formed so as to alternately surround square source and drain contact holes 25 and 27 arranged at predetermined intervals, and have a layout in which these are arranged in a rectangular wave shape. An MO having such a modified striped arrangement of insulated gates
The SFET can be formed with a longer gate width per unit area than that of the conventional mesh arrangement, and accordingly, the ON resistance is small and the loss is small, so
The efficiency as T is good.

[0003]

In this conventional power MOSFET having a modified striped gate electrode, a source contact is regularly arranged at an equal pitch, and a drain contact is arranged on a diagonal intersection thereof. Since the square pattern has the same shape as the contacts, the distance between the source contacts cannot be reduced, and the ratio of the gate width to the unit area cannot be said to be sufficiently large. Further, since the deformed striped gate electrode is formed in a rectangular wave shape, a power MOSF having a large cell area is formed.
In ET, uniform operation of each unit cell is difficult due to the influence of gate resistance. For these reasons, there is a problem that the on-resistance cannot be reduced in the power MOSFET having the above structure.

It is an object of the present invention to provide a lateral DSA power MOSFET having a structure that maximizes the effect of reducing the on-resistance by reducing the gate resistance and reducing the distance between the source contacts. To provide a semiconductor device.

[0005]

In order to solve the above technical problem, a lateral DSA power MOSFET according to the present invention is provided.
In the obtained semiconductor device, the first conductivity type Si substrate and the Si-based
A plurality of octagonal channel regions formed on a plate
These channel regions are vertically and horizontally aligned at equal pitch intervals.
A second conductivity type base layer formed in a direction orthogonal to
At the center of the square consisting of the four base layers
And the short sides of the octagon of the four base layers
So as to face the short sides closest to the center position in
A first-conductivity-type drain layer having a rhombus shape having four sides;
Formed in the insulating film on the center of the
Includes squares with four sides along the diagonal of the square
A drain contact hole formed in a diamond shape;
A gap is formed between the base layer and the drain layer on the Si substrate.
Field oxide film and an octagonal frame in the base layer
A first conductivity type source layer formed in
A source contact hole formed in the insulating film above the core
Between the outside of the source layer and the field oxide film
The insulating portion of the base layer and part of the field oxide film
A gate oxide film formed so as to cover the edge of the source layer;
Is covered in an octagonal frame shape through the gate oxide film,
Source contact hole and drain contact hole
Are formed in a bent mesh shape surrounding the insulating film.
And a gate electrode .

[0006]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG.
FIG. 6 is a cross-sectional view along the line VI ′.

Referring to FIGS. 1 and 2, an N-type Si substrate 11 composed of an N-type epitaxial layer or an N-type well layer is provided with a P-type base layer having a square with no corners, that is, an octagonal channel region. 13 are formed in the directions orthogonal to each other at equal pitch intervals, and four adjacent P-type base layers 1 are formed.
3 are arranged at the vertices of a square. At the center position of the square, a diamond-shaped N having four sides so as to be in contact with the short sides inside the region of the octagonal P-type base layer 13 respectively.
^{The +} type drain layer 15 is formed via the field oxide film 17. In the P-type base layer 13, an N ⁺ -type source layer 19 is formed in a square frame shape without corners. A gate oxide film 21 is formed between an outer end of the N ⁺ type source layer 19 and the field oxide film 17 so as to cover an edge of the P-type base layer 13 and a part of the field oxide film 17. A gate electrode 23 made of poly-Si or the like is formed in a square having no corners, that is, an octagon in a plan view. The gate electrode 23 is a square source contact hole 2 formed on the center of the N ⁺ type source layer 19 on the semiconductor substrate plane.
5 and the drain contact hole 27 formed on the center of the N ⁺ type drain layer 15 is formed in a bent mesh shape. The source contact hole 25 on the surface of the portion surrounded by the N ⁺ -type source layer 19 at the center of the P-type base layer 13 and on the surface of the center of the N ⁺ -type drain layer 15 at the center of the P-type base layer 13. A first interlayer insulating film 29 is provided except for the drain contact hole 27. Reference numeral 33a denotes a gate electrode opening for forming an N ⁺ type drain lead region. In addition, code 1
5a is an N ⁺ -type drain lead-out layer. The gate electrode opening 33a is provided for forming the N ⁺ -type drain lead-out region 15a by self-alignment. Here, the field oxide film 17 reduces the electric field at the end of the gate electrode 23 to obtain the target breakdown voltage. On the source contact hole 25 and the drain contact hole 27,
First metal electrodes 31 each having a T-shaped side cross section are provided. These first metal electrodes 31 are provided with a second interlayer insulating film 33 except for the first metal portions on the drain contact holes 27, and the second metal electrodes 3 are further formed thereon.
5 are provided. The first metal electrode 31 and the second metal electrode 35 are electrically connected via a contact hole 37 located on the N ⁺ type drain layer 15.

In the above-described first embodiment, the shape of the drain contact disposed on the diagonal intersection with respect to the source contact regularly disposed at the same pitch is a diamond including a square having four sides along the diagonal. It is formed in a shape. In other words, the rhombus reduces the distance between the source contacts and the on-resistance.

Further, as described above, the gate electrode 23 forming an insulating gate together with the gate oxide film 21 formed on the P-type base layer surrounds the source contact hole 25 and the drain contact hole 27 and has a bent mesh shape. have. By doing so, the gate resistance is reduced, and uniform MOS operation of each unit cell becomes possible.

The N ⁺ -type source layer 19 and the P-type base layer 13 have a DSA structure in which the gate electrode 23 is used as a mask, and the channel length and the threshold voltage are controlled in a self-aligned manner. The N ⁺ -type source layer 19 and the N ⁺ -type drain layer 15 may be formed in the same step or in separate steps.

Although not shown, the source electrode and the drain electrode may be formed separately from the first metal layer.

FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention, and portions equivalent to those in FIG. 1 are denoted by the same reference numerals. FIG. 4 is a cross-sectional view taken along the line VIII-VIII 'in FIG. 3, and portions equivalent to those in FIG. 2 are denoted by the same reference numerals as in FIG. Referring to FIGS. 3 and 4, the gate electrode 23 is not provided with an opening for forming an N ⁺ -type drain extraction layer. In the plan view, the N ⁺ -type drain layer 15 surrounded by the octagonal gate electrode is formed in an octagonal shape obtained by cutting off four corners of a rhombus including a square.
The long side of the octagon is formed so as to circumscribe the short side of the octagonal gate electrode region. The N ⁺ -type drain extraction layer 15a is formed on the Si surface below the gate electrode 23 by performing high-energy ion implantation of several hundred keV of phosphorus using a photoresist as a mask. This is the first
This is a cell pattern having the same effect as that of the embodiment.
4, the N ⁺ -type drain layer 15 is a deep diffusion layer because it is formed by high-energy ion implantation as compared with FIG.

[0014]

As described above, according to the present invention, in the lateral DSA power MOSFET, the distance between the source contacts can be reduced, the channel width per unit area increases, and the on-resistance can be reduced.

In the present invention, a uniform MOS of a unit cell is formed by forming an insulating gate in a mesh shape.
The operation is enabled, and the on-resistance can be further reduced.

Further, in the present invention, a quadrangle having two sides parallel to at least one of a quadrangular diagonal line formed by a line segment connecting the centers of four adjacent source contacts, for example, Since the diamond-shaped drain contacts are arranged so as to have sides parallel to the diagonal line between the source contacts and the distance between the source contacts is reduced, the on-resistance is reduced.

Further, in the present invention, since the insulating gates are continuous with the entire chip in a deformed mesh structure, uniform MOS operation of each unit cell is possible even in a particularly large chip area, and switches and the like can be used. Stable characteristics can be obtained.

As described above, the lateral DSA power MOS of the present invention
A semiconductor device having an FET has an effect that stable device characteristics are obtained and the on-resistance is reduced by about 30%.

[Brief description of the drawings]

FIG. 1 is a power MOS showing a first embodiment of the present invention.
FIG. 3 is a partial plan view of the FET.

FIG. 2 is a sectional view taken along line VI-VI of FIG.

FIG. 3 shows a power MOS showing a second embodiment of the present invention.
FIG. 3 is a partial plan view of the FET.

FIG. 4 is a sectional view taken along the line VIII-VIII ′ of FIG.

FIG. 5 is a partial plan view showing an example of a conventional power MOSFET.

FIG. 6 is a sectional view taken along the line II-II ′ of FIG.

FIG. 7 is a partial plan view showing another example of a conventional power MOSFET.

FIG. 8 is a sectional view taken along line IV-IV ′ of FIG. 7;

[Explanation of symbols]

Reference Signs List 11 N-type Si substrate (N-type epitaxial layer N-type well layer) 13 P-type base layer 15 N ⁺ -type drain layer 15 a N ⁺ -type drain extraction layer 17 Field oxide film 19 N ⁺ -type source layer 21 Gate oxide film 23 Gate electrode 33a Gate electrode opening 25 Source contact hole 27 Drain contact hole 29 First interlayer insulating film 31 First metal electrode 33 Second interlayer insulating film 35 Second metal electrode 37 Contact hole

Claims (1)

(57) [Claims] A first conductivity type Si substrate and a first conductivity type Si substrate on the Si substrate;
A plurality of octagonal channel areas formed
The channel regions are vertically and horizontally orthogonal to each other at equal pitch intervals.
And a second conductive type base layer formed in
Formed at the center of a square consisting of the base layers.
Of the short sides of the octagon of the four base layers
4 sides so as to face the short sides closest to the center position, respectively
Diamond-shaped first conductivity type drain layer having
Formed in the insulating film on the center of the layer,
Including a square with four sides along the diagonal of the square
A drain contact hole formed in the shape of
A substrate between the base layer and the drain layer on the substrate;
Field oxide film and an octagonal frame in the base layer.
A source layer of the first conductivity type formed on the center of the source layer;
A source contact hole formed in said insulating film;
Between the outside of the source layer and the field oxide
Cover the insulating portion of the base layer and a part of the field oxide film.
The edge of the source oxide layer and the gate oxide film
The gate is covered with an octagonal frame through a gate oxide film.
Contact hole and drain contact hole
It is formed in a bent mesh shape surrounding the insulating film
Horizontal D, characterized in that a gate electrode are
A semiconductor device including an SA power MOSFET .