JP2899313B2 - Programmable element - Google Patents
Programmable elementInfo
- Publication number
- JP2899313B2 JP2899313B2 JP1153468A JP15346889A JP2899313B2 JP 2899313 B2 JP2899313 B2 JP 2899313B2 JP 1153468 A JP1153468 A JP 1153468A JP 15346889 A JP15346889 A JP 15346889A JP 2899313 B2 JP2899313 B2 JP 2899313B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- diffusion layer
- isolation oxide
- insulating film
- end portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、集積回路に組み込まれた電気的にプログラ
ム可能なプログラマブル素子に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrically programmable devices incorporated in integrated circuits.
従来の技術 半導体集積回路のうち、使用者が購入した後に内容を
電気的に書き込むことのできるいわゆるPROM(Programm
able ROM)は望む内容のROM(Read Only Memory)がた
だちに得られるために広く用いられている。2. Description of the Related Art Among semiconductor integrated circuits, a so-called PROM (Programmable Programmable Read Only Memory) that allows a user to electrically write the contents after purchase.
Able ROM is widely used because a ROM (Read Only Memory) with desired contents can be obtained immediately.
また論理回路の分野においても、やはり使用者が購入
した後に内容を電気的に書き込むことのできるいわゆる
PLD(Programmable Logic Device)が類似の目的のため
用いられている。PROMやPLDを構成するためには外部か
ら記憶内容が電気的に書き込め、かつ電源を切ってもそ
の記憶内容が保持されるようなプログラマブル素子を用
いる必要が有る。Also, in the field of logic circuits, the contents can be electrically written after the user has purchased the so-called so-called logic circuit.
PLDs (Programmable Logic Devices) are used for similar purposes. In order to configure a PROM or PLD, it is necessary to use a programmable element that can electrically write stored contents from outside and retain the stored contents even when the power is turned off.
従来このようなプログラマブル素子に好適な構造は例
えば以下に示すようなものであった。Conventionally, a structure suitable for such a programmable element has been described below, for example.
第2図は従来例のプログラマブル素子の構造を示す断
面図であり、これを参照して説明する。FIG. 2 is a sectional view showing the structure of a conventional programmable element, which will be described with reference to FIG.
図示するように、P型半導体基板1がフィールド酸化
膜2により分離されており、分離された一領域中に下部
電極となる高不純物濃度の拡散層3が形成されている。As shown, a P-type semiconductor substrate 1 is separated by a field oxide film 2, and a diffusion layer 3 having a high impurity concentration serving as a lower electrode is formed in one separated region.
拡散層3上には酸化物層4と上部電極5とが順次積層
されて形成されており、プログラミングは上部電極5と
拡散層3との間に適当な電圧を印加し、酸化物層4の絶
縁を破壊することにより行われる。On the diffusion layer 3, an oxide layer 4 and an upper electrode 5 are sequentially laminated and formed. For programming, an appropriate voltage is applied between the upper electrode 5 and the diffusion layer 3, and This is done by breaking the insulation.
発明が解決しようとする課題 上記のような従来例のプログラマブル素子では、酸化
物層4を高品質、すなわちピンホールと呼ばれる穴が少
なく、かつ耐圧が高い状態にするには下地である拡散層
3を熱的に酸化して形成しなければならない。一般に高
濃度の不純物を含む拡散層を熱的に酸化すると、不純物
濃度に応じて形成される酸化膜厚は異なり、不純物濃度
が高いほど厚い酸化膜が形成される。Problems to be Solved by the Invention In the above-mentioned conventional programmable element, in order to make the oxide layer 4 of high quality, that is, with few holes called pinholes and high withstand voltage, the diffusion layer 3 which is the base layer is required. Must be formed by thermal oxidation. Generally, when a diffusion layer containing a high-concentration impurity is thermally oxidized, the thickness of the oxide film formed varies depending on the impurity concentration, and a thicker oxide film is formed as the impurity concentration increases.
第2図に示したような構造においては、酸化物層4が
フィールド酸化膜2に接している。一般に拡散層3はフ
ィールド酸化膜2をマスクとして形成されるため、フィ
ールド酸化膜2の端部6においては横方向拡散やフィー
ルド酸化膜2のエッチングによる後退などによりやや不
純物濃度の低い領域7が露出している。前述したような
理由によりこの領域上では酸化物層4の厚さが他の部分
に比して薄くなりまた膜厚の制御も難しい。そのためプ
ログラマブル素子としての耐圧が低くなりまたそのばら
つきも大きくなって書き込み特性が安定しないという課
題が有る。In the structure as shown in FIG. 2, the oxide layer 4 is in contact with the field oxide film 2. Generally, the diffusion layer 3 is formed using the field oxide film 2 as a mask. Therefore, at the end 6 of the field oxide film 2, a region 7 having a slightly lower impurity concentration is exposed due to lateral diffusion or receding due to etching of the field oxide film 2. doing. For the reasons described above, the thickness of the oxide layer 4 becomes thinner in this region than in other portions, and it is difficult to control the film thickness. For this reason, there is a problem that the withstand voltage of the programmable element is reduced and the variation thereof is increased, so that the writing characteristics are not stable.
さらに、第2図に示すように上部電極5が酸化物層4
の全体を覆っていない構造では、上部電極5をドライ・
エッチングにより加工する際に露出した酸化物層4、さ
らには拡散層3が損傷を受けて結果として接合の漏れ電
流が発生しやすいという課題も有る。Further, as shown in FIG.
In a structure that does not cover the entire area of the
There is also a problem that the oxide layer 4 exposed at the time of processing by etching and the diffusion layer 3 are damaged, and as a result, leakage current at the junction is likely to occur.
課題を解決するための手段 上記のような課題を解決するための本発明のプログラ
マブル素子は、半導体基板中にほぼ下半が埋没し、且
つ、端部が上面及び下面とも傾斜面を持ちその先端部に
向かって膜厚の薄くなっている厚い分離酸化膜と、前記
分離酸化膜に接して前記半導体基板領域中に形成された
高不純物濃度の拡散層からなる下部電極と、前記分離酸
化膜の端部から離間した前記下部電極の平坦な表面上に
形成されたプログラム用絶縁膜と、前記プログラム用絶
縁膜と前記分離酸化膜との間の前記下部電極上に熱酸化
により形成された酸化膜と、少なくとも前記プログラム
用絶縁膜の全表面を覆うように形成され、前記酸化膜上
を介して前記分離酸化膜上に引き出された上部電極とを
備え、前記下部電極となる拡散層の端部は該端部以外に
比して不純物濃度が低くかつ前記分離酸化膜の端部下面
の傾斜面に前記拡散層の両端が接しており、少なくとも
前記不純物濃度の低い拡散層の端部上には前記プログラ
ム用絶縁膜より膜厚が厚くプログラム電圧以上の耐圧を
有する前記酸化膜が前記分離酸化膜に連なって形成され
ていることを特徴とするものである。Means for Solving the Problems A programmable element according to the present invention for solving the above-mentioned problems has a lower half almost buried in a semiconductor substrate, and an end having inclined surfaces on both the upper surface and the lower surface. A lower isolation electrode formed of a high impurity concentration diffusion layer formed in the semiconductor substrate region in contact with the isolation oxide film; A program insulating film formed on a flat surface of the lower electrode separated from an end portion, and an oxide film formed by thermal oxidation on the lower electrode between the program insulating film and the isolation oxide film And an upper electrode formed so as to cover at least the entire surface of the program insulating film and drawn out onto the isolation oxide film via the oxide film, and an end portion of the diffusion layer serving as the lower electrode. Is from the end Both ends of the diffusion layer have a lower impurity concentration than the outside, and both ends of the diffusion layer are in contact with an inclined surface of a lower surface of an end portion of the isolation oxide film. The oxide film having a thickness greater than that of the film and having a breakdown voltage equal to or higher than a program voltage is formed so as to be continuous with the isolation oxide film.
作 用 本発明のプログラマブル素子では、プログラムされる
絶縁膜の膜厚がほぼ一定であるため絶縁破壊に要する電
圧も一定となり安定した書き込み特性が得られる。また
局所的に耐圧の低い領域が存在しないので未書き込み素
子の信頼性も高い。In the programmable element of the present invention, the thickness of the insulating film to be programmed is substantially constant, so that the voltage required for dielectric breakdown is constant and stable writing characteristics can be obtained. Also, since there is no locally low withstand voltage region, the reliability of the unwritten element is high.
実 施 例 本発明のプログラマブル素子の実施例を第1図に示
し、これを参照して説明する。Embodiment An embodiment of the programmable element of the present invention is shown in FIG. 1 and will be described with reference to FIG.
図示するように、P型シリコン基板11が選択酸化によ
るフィールド酸化膜(以後分離酸化膜と記す)12により
複数の領域に分離されており、分離された一領域中に下
部電極となるN+型拡散層13が形成されている。As shown in the figure, a P-type silicon substrate 11 is separated into a plurality of regions by a field oxide film (hereinafter referred to as an isolation oxide film) 12 by selective oxidation, and an N + -type electrode serving as a lower electrode is formed in one of the separated regions. A diffusion layer 13 is formed.
N+型拡散層13はその上部が熱的に形成された酸化膜14
により覆われている。この酸化膜14の膜厚は分離酸化膜
12の膜厚に比して1/3〜1/10程度で、かつ通常プログラ
ミング電圧として用いられる10〜20Vの電圧に十分耐え
る厚さ、すなわち50〜150nmであればよい。The N + -type diffusion layer 13 has an oxide film 14 having an upper portion formed thermally.
Covered by The thickness of the oxide film 14 is the thickness of the isolation oxide film.
The thickness may be about 1/3 to 1/10 of the thickness of 12 and sufficiently withstand a voltage of 10 to 20 V used as a normal programming voltage, that is, 50 to 150 nm.
酸化膜14の一部分は選択的に除去されており、除去さ
れた領域の拡散層13上にプログラム用絶縁膜15が形成さ
れている。プログラム用絶縁膜15は、酸化膜14に連な
り、さらに分離酸化膜12に連なっている。このためプロ
グラム用絶縁膜15は分離酸化膜12に接しない構造となっ
ている。なお、この絶縁膜15は、例えば下層をシリコン
酸化膜、上層をシリコン窒化膜として全体で厚さを8〜
9nmとすれば、20V程度の電圧で1ms程度で絶縁を破壊さ
せることができる。A part of the oxide film 14 is selectively removed, and a programming insulating film 15 is formed on the diffusion layer 13 in the removed region. The program insulating film 15 is connected to the oxide film 14 and further connected to the isolation oxide film 12. Therefore, the program insulating film 15 has a structure not in contact with the isolation oxide film 12. The insulating film 15 has a total thickness of 8 to 10 with the lower layer being a silicon oxide film and the upper layer being a silicon nitride film, for example.
If the thickness is 9 nm, the insulation can be broken in about 1 ms at a voltage of about 20 V.
絶縁膜15を有る領域は分離酸化膜12と接しておらずま
た拡散層13の不純物濃度がほぼ一定な領域であるため絶
縁膜15の膜厚もほぼ一定である。これにより安定した書
き込み特性が得られる。Since the region having the insulating film 15 is not in contact with the isolation oxide film 12, and the impurity concentration of the diffusion layer 13 is substantially constant, the thickness of the insulating film 15 is also substantially constant. Thereby, stable writing characteristics can be obtained.
絶縁膜15の上には上部電極16が形成されており、上部
電極16の端は酸化膜14上に有る。このため上部電極16の
加工時に多少の過剰なエッチングを行っても絶縁膜15や
拡散層13が損傷を受けることは無い。An upper electrode 16 is formed on the insulating film 15, and an end of the upper electrode 16 is on the oxide film 14. For this reason, the insulating film 15 and the diffusion layer 13 are not damaged even if a slight excessive etching is performed during the processing of the upper electrode 16.
なお上記の実施例では説明の都合上プログラム用絶縁
膜15を多層膜としたが、これは実施例の構成に従う必要
はなく、拡散層13を熱的に酸化した単層膜であってもよ
い。In the above embodiment, the program insulating film 15 is a multilayer film for convenience of explanation, but it is not necessary to follow the configuration of the embodiment, and it may be a single layer film in which the diffusion layer 13 is thermally oxidized. .
発明の効果 本発明をプログラマブル素子では、プログラムされる
絶縁膜の厚さが一定であり局所的に薄いということが無
いため書き込み特性および信頼性が安定している。その
結果として高性能、高信頼性のプログラマブル集積回路
が得られる。Effect of the Invention In the programmable element according to the present invention, the thickness of the programmed insulating film is constant and is not locally thin, so that the writing characteristics and reliability are stable. As a result, a high-performance and high-reliability programmable integrated circuit is obtained.
【図面の簡単な説明】 第1図は本発明のプログラマブル素子の実施例を示す断
面図、第2図は従来例のプログラマブル素子の構造を示
す断面図である。 11……基板、12……分離酸化膜、13……N+型拡散層、14
……酸化膜、15……プログラム用絶縁膜、16……上部電
極。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an embodiment of a programmable element of the present invention, and FIG. 2 is a sectional view showing a structure of a conventional programmable element. 11 ... substrate, 12 ... isolated oxide film, 13 ... N + type diffusion layer, 14
... oxide film, 15 ... insulating film for programming, 16 ... upper electrode.
Claims (1)
端部が上面及び下面とも傾斜面を持ちその先端部に向か
って膜厚の薄くなっている厚い分離酸化膜と、前記分離
酸化膜に接して前記半導体基板領域中に形成された高不
純物濃度の拡散層からなる下部電極と、前記分離酸化膜
の端部から離間した前記下部電極の平坦な表面上に形成
されたプログラム用絶縁膜と、前記プログラム用絶縁膜
と前記分離酸化膜との間の前記下部電極上に熱酸化によ
り形成された酸化膜と、少なくとも前記プログラム用絶
縁膜の全表面を覆うように形成され、前記酸化膜上を介
して前記分離酸化膜上に引き出された上部電極とを備
え、 前記下部電極となる拡散層の端部は該端部以外に比して
不純物濃度が低くかつ前記分離酸化膜の端部下面の傾斜
面に前記拡散層の両端が接しており、少なくとも前記不
純物濃度の低い拡散層の端部上には前記プログラム用絶
縁膜より膜厚が厚くプログラム電圧以上の耐圧を有する
前記酸化膜が前記分離酸化膜に連なって形成されている
ことを特徴とするプログラマブル素子。A semiconductor device according to claim 1, wherein the lower half is substantially buried in the semiconductor substrate, and
A thick isolation oxide film whose end portion has an inclined surface on both the upper surface and the lower surface and has a thinner thickness toward the tip portion; and a high impurity concentration formed in the semiconductor substrate region in contact with the isolation oxide film. A lower electrode formed of a diffusion layer, a program insulating film formed on a flat surface of the lower electrode separated from an end of the isolation oxide film, and a gap between the program insulating film and the isolation oxide film. An oxide film formed by thermal oxidation on the lower electrode, and an upper electrode formed so as to cover at least the entire surface of the program insulating film and drawn out on the isolation oxide film via the oxide film; An end portion of the diffusion layer serving as the lower electrode has a lower impurity concentration than the end portion, and both ends of the diffusion layer are in contact with an inclined surface of an end lower surface of the isolation oxide film. Low impurity concentration A programmable element, wherein the oxide film having a thickness larger than that of the program insulating film and having a breakdown voltage equal to or higher than a program voltage is formed on an end portion of the diffusion layer so as to be continuous with the isolation oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1153468A JP2899313B2 (en) | 1989-06-15 | 1989-06-15 | Programmable element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1153468A JP2899313B2 (en) | 1989-06-15 | 1989-06-15 | Programmable element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0319279A JPH0319279A (en) | 1991-01-28 |
JP2899313B2 true JP2899313B2 (en) | 1999-06-02 |
Family
ID=15563227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1153468A Expired - Fee Related JP2899313B2 (en) | 1989-06-15 | 1989-06-15 | Programmable element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2899313B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004158206A (en) | 2002-11-01 | 2004-06-03 | Fci Asia Technology Pte Ltd | Electric connector for flat type flexible cable |
JP4783081B2 (en) * | 2005-07-21 | 2011-09-28 | 株式会社アイペックス | Electrical connector |
DE602007009728D1 (en) * | 2006-12-22 | 2010-11-18 | Sidense Corp | MASK PROGRAMMABLE ANTI-MIX CONNECTION ARCHITECTURE |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60158661A (en) * | 1984-01-28 | 1985-08-20 | Seiko Epson Corp | Semiconductor memory storage |
-
1989
- 1989-06-15 JP JP1153468A patent/JP2899313B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0319279A (en) | 1991-01-28 |
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LAPS | Cancellation because of no payment of annual fees |