JP2898482B2 - Computer game equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a background screen
Means to display images by combining with the sprite screen
And the background screen is displayed on an external block.
Sequential, external dot sequential and internal
Multiple types of images in the dot sequential image mode
For computer game devices that can handle image data
Related.

[0002]

2. Description of the Related Art Conventionally, in a computer device used for a game or the like for performing image processing of many animations and the like, a background (B
G) and two types of screens called sprites are superimposed.

[0003] In such a system, the background screen is constituted by a pattern called a "character", and the sprite screen is constituted by a pattern called a "sprite". Usually, in image display, the virtual screen on the memory is larger than the CRT screen (real screen). By shifting the data of the virtual screen vertically or horizontally, scrolling can be realized on the real screen.

The background is defined by display position, color, and pattern information for each background character in units of raster and character pitch on the CRT screen. The display position of the character indicates the coordinates on the screen.

The background screen is managed in a memory in the computer in a data format of a background attribute table (BAT) and a character generator (CG).

The BAT is a table set in the RAM for designating what character is displayed in each character position on the virtual screen in what color.

As the character code, a character number defined by a CG in the RAM is specified, and an actual character pattern is registered in the CG corresponding to the number. The CG is composed of several surfaces corresponding to the color modes.

In an actual television screen, as shown in FIG.
An image is displayed by running a scan line from left to right. When the scan line reaches the right end, it is then moved back to the left end again. During this time, no image is displayed. For this reason, this interval is referred to as an H blank (HSYNC).

The scanning line moves from the top to the bottom of the screen while repeating the above operation. Upon reaching the bottom, the scan line again moves to the top. During this time,
Do not display images. For this reason, this interval is referred to as a V blank (VSYNC).

For the H blank, the horizontal synchronizing period (HS
YNC) signal, and a vertical synchronizing period (VHYNC) signal is generated for V blank. An interrupt is generated based on this signal. Since the V blank is longer than the H blank, most of the processing in the game is handled during this period.

The conventional access to the BG has to be performed during the period of the H blank and the V blank. For this reason, the timing of access to the BG is fixed, and access processing by software is restricted.

For example, when the scanning line moves to the right end, a horizontal synchronization signal is generated, and a horizontal synchronization period (HSYNC) interrupt occurs. Therefore, it is necessary to complete the access of the BG by the interrupt processing during the H blank. The same applies to the V blank, but in any case, the BG access timing must be performed under such restrictions.

[0013]

The problem to be solved by the present invention will be described below with reference to a computer game machine according to the present invention.

FIG. 2 is a block diagram of an example of a computer game apparatus having many types of RAMs. In addition to the M-RAM dedicated to the CPU, a V-RAM for a video display processor (VDP), a K-RAM for a controller chip including a SCSI controller, a graphic controller, a sound controller, and the like, an image decompression for decoding a compressed image signal And various RAMs such as an R-RAM for use.

FIG. 3 is a more detailed view of the inside of the controller chip including the SCSI controller, graphic controller, sound controller and the like in FIG.

In this device, the controller chip is a CD
-Read data from external storage such as ROM K-
Store in RAM. Various data such as image data is temporarily stored in the K-RAM, and includes various types of data such as 8 bits forming one record and 16 bits forming one record. .

The BG data in the K-RAM is read again, processed by the controller chip, and sent to the video encoder. The video encoder has a function of displaying image data sent from a controller chip or other devices on a television screen.

At this time, the video encoder uses VSYNC, HSYNC, DCK (dot) as display image control signals.
Clock) and SCK (system clock) from these signals to generate timing necessary for the operation of the controller chip.

In accordance with the interlace display mode, a system clock corresponding to the even / odd field discrimination signal (OD / -EV) sent from the video encoder is generated.

In this example, the background virtual screen is as shown in FIG. 4, and the coordinate system of this plane is called an image plane coordinate system. The image plane coordinate system is -512 to +512
It has a dot value and is secured in a range of 1024 × 1024 dots.

The real screen display area is 256 × 240 dots, and scrolling of the BG screen is realized by moving this display area up, down, left and right on a 1024 × 1024 image plane coordinate system.

The background screen is "character",
The sprite screen is configured with a pattern called “sprite” as a unit. Hereinafter, one unit of the character is 8 × 8 dots, and one unit of the sprite is 16 × 1
It is managed with 6 dots.

The background is defined by display position, color, and pattern information for each background character in units of raster and character pitch on the CRT screen. The character display position indicates the coordinates on the screen. A raster scanning position on the CRT screen is detected, character information corresponding to the position is converted into a video signal, and output to the screen.

The background screen is managed in a memory in the computer as shown in FIG. The background attribute table (BAT) is a table set in the RAM in order to specify what character is displayed in each character position on the virtual screen in what color.

As the character code, a character number defined by a character generator (CG) in the RAM is designated, and an actual character pattern is registered in the CG corresponding to this number. The CG is composed of several surfaces corresponding to the color modes. For example, the four-color mode has two surfaces, and the sixteen-color mode has four surfaces. The faces are named from the front as CH0 to CH3.

A color can be represented as a sum of corresponding bits of CH0 to CH3. FIG. 6 shows an example. The figure shows the case of the 16-color mode, where the corresponding bit values of CH0 to CH3 are b0,
Assuming that b1, b2 and b3, the color number c is obtained as c = b0 × 2 ⁰ + B1 × 2 ¹ + B2 × 2 ² + B3 × 2 ³ .

Although this may be handled directly as a color number, 16 colors are fixed. Therefore, the concept of a color palette is introduced, and the actual color numbers are determined by this palette. That is, CG
The color number obtained from is used to point to the position of the color palette.

The character code of the BAT indicates the address of the CG, and the CG to be used is determined only by changing the character code. Here, the CG for the dot
Changes the memory arrangement depending on the color mode. 4 colors, 1
FIG. 7 shows a memory arrangement in the case of the 6-color and 256-color mode.

On the other hand, the BG image data handled by the controller chip in the apparatus of this example has more types than before,
There are three types of data as follows. (1) External block sequential (2) External dot sequential (3) Internal dot sequential

In most cases, a conventional computer game apparatus has only external block sequential BG data in which 8 × 8 dots constitute one block. However, in the device of this example, an external dot sequential and an internal dot sequential that handle BG data in dot units are added. This is the future of computer games
In this case, BG is handled in block units as in the past.
BG is handled in dot units like a normal computer.
It is quite possible that there will be demands. this
In order to change these modes for each BG screen,
What you can do is effective.

Here, the image data mode named "external" is image data managed by BAT and CG, and the image data mode named "internal" is bitmap data. Natural image data read by an image scanner or the like is managed by internal dot sequential.

The first internal dot sequential is a CG of a bitmap image and is a data format for displaying a natural image read by an image scanner or the like as it is.
For this reason, BAT is not held.

On the other hand, the latter two are image data managed by BAT and CG. The BAT is a table that specifies which character is displayed at which position on the virtual screen. In the external block sequential format, CG
Represents a character pattern, and basically follows the conventional concept. In the external dot sequential format, CG is handled in units of one dot, and is used when the same effect as a color palette is obtained.

BG image data generated from these three types of data is sent to a video encoder and displayed on a television screen. FIG. 8 shows this state.

Hereinafter, the external block sequential, external dot sequential, and internal dot sequential of the BG image data format used in the computer device of the present invention will be described in detail.

(1) External Block Sequential The BAT in this case is composed of a pallet bank and a character code as shown in FIG. Fig. 4
CG COLOR, and indicates a bank in the video encoder unit. Thereby, a group of 16 colors in the 256 colors of the color palette is determined.

However, the palette bank is valid only in the 4-color mode and the 16-color mode, and is ignored in other modes. The character code points to the CG, and the actual CG address can be obtained from this code and the CG address register.

CG determines a character pattern in an 8 × 8 dot configuration. The length for determining the display color of one dot differs depending on the color mode. Assuming that the number of colors used at the same time is m, the number n of bits required for one-dot display can be obtained by n = Log ₂ m.

If m is 4, 16, 256, 64K, 16M color mode, n is 2, 4, 8, 16, 24 bits. However, since the RAM is arranged with 16 bits (= 1 word), if m = 16M, 3
Two bits represent two dots.

(I, j) of p _{i, j in} FIG. 10 represents the dot position (row, column) of the character, and p represents the pallet number.

FIG. 11 is a diagram showing the bit configuration on the RAM for four colors, FIG. 12 is 16 colors, and FIG. 13 is for the 256 color mode. In the m = 4 to 256 color mode, the position (color) of the color palette is designated. Since the color palette has a size corresponding to 256 colors, the entire color palette can be directly pointed in the 256 color mode.

Therefore, in the 256-color mode, there is no need to select the range of colors to be used in the BAT palette bank, so the pallet bank becomes unnecessary in the 256-color mode (ignored in the internal processing of the system).

FIG. 14 is a diagram showing the bit configuration on the RAM for the 64K color mode, and FIG. 15 is a diagram showing the bit configuration on the RAM for the 16M color mode. 64
In the K color and 16M color modes, the color palette is not used and the color data is directly specified. In the 64K color mode, YUV (Y
(8 bits, U4 bits, V4 bits) specifies color data for one dot.

In the 16M color mode, color data for two dots is designated by YYUV (Y8 bits, Y8 bits, U8 bits, V8 bits). The first Y represents the luminance of the first dot, and the second Y represents the luminance of the second dot. U and V are 1
Represents a common color difference between the dot and the second dot.

This is because, in a natural image, colors adjacent to each other are not extremely different, so that it is possible to sufficiently cope with only the luminance. Thus, the definition size of the character can be reduced, and as a result, the character pattern can be defined in the same size (64 words) as the 64K color. As described above, in the external block sequential, the conventional BG image data can be used as it is.

(2) External Dot Sequential The external dot sequential is basically the same as the external block sequential. However, in the case of external dot sequential, data handling is not performed in units of blocks (= characters) but in units of dots. Therefore, FIGS. 10, 11, 12, 13, 14, 1
Only one row of the table No. 5 is the CG definition of the external dot sequential. However, in the 16M color mode, two rows and two dots are defined.

In the external dot sequential, the efficiency of the memory can be improved for image data displaying the same color.

The reason for introducing such a data format will be described. Let us consider a case where a picture as shown in FIG. 16 is displayed on a screen. At this time, suppose the sky was one color. Since the color of the sky changes with time, the 64K color mode is used to express this change as naturally as possible. To represent the sky color, either external block sequential or external dot sequential is possible.

When external block sequential is used, CG is defined as 8 × 8 dots.
Four words (= 1024 bytes) are required. On the other hand, in the case of external dot sequential, the definition for one dot is sufficient, so the size is one word (= 16 bytes)
No problem.

Suppose that the sky changes like blue-white, light red, red, dark red, magenta, dark blue, and black. To realize this, it is only necessary to prepare CGs for the number of colors to be changed and to sequentially change the character codes of the BAT.

For the CG size required for this, 64 × (number of CG) words are required for external block sequential, and 2 × (number of CG) words are required for internal dot sequential. Assuming that the number of CGs is 8, the former has 512 words and the latter has 16 words. That is, in such a case, the external dot sequential is a data format indispensable for effective use of the memory.

From another point of view, in external dot sequential, one CG represents one color itself, so that it is a substitute for a color palette.
The external dot sequential does not have a fixed color palette, and the user defines a color palette as needed. As a result, a large number of colors can be handled with a minimum memory.

(3) Internal Dot Sequential The internal dot sequential is a data format for defining colors in dot units, similarly to the external dot sequential. What is different from external dot sequential is B
Not having an AT. The reason is that the image data is not image data usually defined by the user, but is image data taken by a video or an image scanner.

Another feature of the internal dot sequential is that two words of YYUV define two dots in the 16M color mode. This has already been described. Thereby, a rich color of 16M colors can be defined with a small CG size.

Nevertheless, the reproducibility is not adversely affected. Of course, the 16M color mode can be used in the external dot sequential or the external block sequential, but the use value is particularly high in the internal dot sequential which handles natural images and needs to have color data in dot units. In the internal dot sequential, an image captured by an external video device can be uniquely handled, and processing can be simplified.

As described above, by using these BG video data formats for various videos, it is possible to flexibly deal with them. Conventionally, since only BG data in the external block sequential mode is used, it is sufficient to access and process block data during the synchronization period of HSYNC or VSYNC.

However, in a system like this example, BG
Under the situation where the types of data are increasing and the number of BG screens is also increasing to four, it is difficult to perform flexible and quick image processing in this synchronous period and with access in units of blocks.

In order to solve such a problem, an object of the present invention is to enable BG access timing to be set arbitrarily.

[0059]

[Means for Solving the Problems] In order to solve the above-mentioned problems
In addition, the present invention provides a background screen and a sprite screen.
Means for displaying an image by combining
Background screen display is external block sequencer
External dot sequential and internal dot sequence
Computer game device with an uncial image mode
, Access to the VRAM for screen display
Immerse in each image mode of the background screen
Set by the corresponding microprogram. Of the present invention
In the system, DCK (dot clock) is used as a control signal.
And access timing.
Can be specified for each dot clock cycle.

For example, let us consider a case where only the first three dots are processed in a natural image (in the internal dot sequential mode) and it is not necessary to touch other dots. In the conventional access, it is necessary to access the block unit during the interruption period and process the dots in the block.

In such a case, if only the necessary dots are accessed, it is sufficient to access only the three dots that need to be processed in a three-dot clock cycle, so that the processing time is short and the load on the CPU is reduced.

Actually, unless the processing is performed in such a short time, data in the internal dot sequential format cannot be processed. Therefore, it is necessary to change the access timing depending on the type of data and the form of processing.

However, these combinations are so many that it is impossible to cope with them by merely preparing a fixed circuit as in the prior art.

Further, if a circuit is formed, an enormous number of circuits are required. Therefore, the present invention solves this problem by providing a microprogram and allowing the user to flexibly respond by giving a macro instruction.

[0065]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the apparatus according to the present invention, arithmetic processing for accessing the K-RAM is incorporated in a controller chip as a microprogram so that a user can set the access timing with a register.

Although VSYNC and HSYNC have already been described, in the system of the present invention, DCK (dot clock) can be newly used as a control signal. FIG. 17 shows the relationship between HSYNC and DCK.
The SYNC period includes about 341 DCK cycles.

The DCK (dot clock) cycle is HS
The access timing is specified for each dot clock cycle in about 1/341 of the YNC cycle.

The setting of the microprogram to the controller chip is performed by the microprogram load address register and the microprogram data register. First, the address of the microprogram to be set is specified in the microprogram load address. However, at this time, MPSW of the microprogram control register is set to 0.
It is necessary to keep it.

Next, data is written to the microprogram data register. At this time, the microprogram address is incremented each time one data is written, so that it is not necessary to reset the microprogram load address register. After setting necessary data, MPSW
If = 1, the microprogram operates. The format of each register is shown in FIG.

FIG. 19 explains the contents of the description of the microprogram data register. This register specifies (1) the content of KRAM access address generation, (2) generation timing, and (3) the destination of read data.

For external block format and external dot format data, the first BAT data is read, and then the CG data is read. During this time, two dots are required. The description data is divided into two blocks (A bus and B bus), and the following contents are described.

(1) Processing / Non-processing (NOP / -NOP) (2) BG surface number (0 to 3) (3) Rotation / Non-rotation (4) BAT / CG (BAT / -CG) (5) BAT Indirect CG / Direct CG (between / -Direct CG) (6) CG offset

The controller chip converts the BG plane data to H
It is output for each dot in synchronization with DISP (horizontal display period). On the other hand, the microprogram is BGDISP (B
G display period), the operation starts, and BGDISP
Exit in synchronization with.

Since the amount of delay differs between the rotation process and the non-rotation process, the non-rotation surface performs a process synchronized with BGNDISP, and the rotation surface performs a process synchronized with BGRDISP. Therefore, as shown in FIG. It operates during the P period.

The graphic controller chip has 4 colors, 16 colors, 2 colors for each BG screen that can be displayed simultaneously.
Different image data among the 56 colors, 64K colors, and 16M colors can be simultaneously mixed and handled.
For this reason, a microprogram control method capable of programming all of the access timing is adopted.

There are two K-BUS microprograms
Describes the operation within the 8 dot clock cycle independently, and each bus independently executes one step at a time in the K-BUS cycle, and repeats the 8 dot clock cycle.

FIG. 21 is an example of the timing of address generation by the microprogram, and FIG. 22 is an example of the description of the microprogram. In this example, (1) BG0: external block sequential format 256
Color mode (2) BG1: 16-color mode in external block sequential format (3) BG2: 16-color mode in internal dot sequential format.

For example, in cycle 0, "CG (0) between BG0" is specified for B bus data. In cycle 0, BAT indirect CG0 is accessed for BRAM in the external block sequential format 256 color mode. . NOP, that is, no processing for the ARAM.

[0079]

As described above, in a computer game apparatus, a user has made a user program and accessed BG data as interrupt processing during an interrupt period of a video control signal. For this,
The BG data that can be accessed at one time is on a character basis, and processing on a character basis is inevitable.

Nevertheless, conventionally, only external block sequential format data managed by BAT and CG was used, so that this method was sufficient. But,
Future systems need to handle data in dot units, and have a wide variety of color modes (4, 16, 256, 64).
K, 16M), multiple BG planes (four planes), rotation / non-rotation, etc.
In addition, we have several types of controllers to realize these
That is, the number of parts constituting the device is increased, and the VRAM to be used is increased.
Causes an increase in capacity. Also required by the program
Mode is different, so prepare each controller
It is useless to do. Therefore, these modes are
There is a need for processing in the controller.

If such a variety of mode combinations are handled by a user program as in the past and during the HSYNC or VSYNC interrupt period, the program description and the execution speed can be improved. Many problems have arisen, some of which cannot be addressed.

In order to increase the processing speed, if hardware corresponding to various data formats is incorporated in the conventional system, the circuit becomes enormous.

On the other hand, if the method of the present invention is used, BG data can be accessed in a dot cycle, and the timing can be set by a user using a microprogram. Therefore, data can be accessed in a free format, and efficient access processing can be performed. Can be performed. That is, unnecessary access is enabled, and the load on the CPU can be reduced. Also, since the microprogram may be described in a predetermined data format, it can be described in a variety of data formats in a relatively simple manner.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of the concept of an H blank and a V blank in a CRT display.

FIG. 2 is a block diagram of an example of a computer game device.

FIG. 3 is an explanatory diagram inside a controller chip.

FIG. 4 is an explanatory diagram of a virtual screen and a real screen in the background.

FIG. 5 is an explanatory diagram of management of a background screen on a memory.

FIG. 6 is an explanatory diagram showing a relationship between a color palette and BAT / CG.

FIG. 7 shows four colors, 16 in a computer game device.
FIG. 6 is an explanatory diagram of a memory arrangement in a case of a 256-color mode.

FIG. 8 is an explanatory diagram until BG image data is displayed on a television screen.

FIG. 9 is an explanatory diagram of external block sequential data.

FIG. 10 is an explanatory diagram of a dot position and a pallet number of a character.

FIG. 11 is a diagram illustrating a bit configuration on a RAM in a four-color mode.

FIG. 12 is a diagram illustrating a bit configuration on a RAM in a 16-color mode.

FIG. 13 is a diagram illustrating a bit configuration on a RAM in a 256-color mode.

FIG. 14 is a diagram illustrating a bit configuration on a RAM in a 64K color mode.

FIG. 15 is a diagram illustrating a bit configuration on a RAM in a 16M color mode.

FIG. 16 is an explanatory diagram of memory efficiency improvement for image data displaying the same color.

FIG. 17 shows DCK and HSYNC in the embodiment of the present invention.
FIG.

FIG. 18 is an explanatory diagram of a register related to a microprogram in the embodiment of the present invention.

FIG. 19 is an explanatory diagram of the contents of a microprogram data register in the embodiment of the present invention.

FIG. 20 is an explanatory diagram of a relationship between an operation period of a microprogram and each display period in the embodiment of the present invention.

FIG. 21 is an explanatory diagram of a timing of generating an address by a microprogram in the embodiment of the present invention.

FIG. 22 is a description example of a microprogram in the embodiment of the present invention.

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Claims (1)

(57) [Claims] 1. A background screen and a sprite screen.
Means for displaying images in combination with each other, and
Background screen display is external block sequential,
External dot sequential and internal dot sequential
Computer game device with
And the timing of accessing the VRAM for screen display
Marks corresponding to each image mode of the background screen
It is specially equipped with means for setting by micro program.
Computer game device.