JP2893700B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for transmitting an image signal for forming a hard copy image, and more particularly, to prevention of image deterioration due to gradation reproduction.

[Conventional technology]

Like a digital copier or facsimile machine, a hard copy system device combining a computer or a word processor with various printer devices, image information for each pixel of a subdivided original image is quantized and handled as digital image data. In a so-called digital image forming apparatus, a binary image for reproducing an original image is formed by an arrangement of dots including display dots and non-display dots.

In order to reproduce halftones (halftones) in the formation of such a binary image, an image processing apparatus incorporated in an image forming apparatus sets a threshold value of image data according to an area gradation method represented by a density pattern method or a dither method. The data is binarized in comparison with the data, and a tone reproduction process for determining the number of display dots per unit area according to the density of the original image is performed.

Since the tone reproduction process is not necessary for a character or line drawing portion which is originally a binary image, it is conceivable to apply this process only to a halftone image portion such as a printed image of a photograph. It is extremely difficult to reliably separate a binary image area and a halftone image area. Therefore, in general, 2
The same tone reproduction processing as in the halftone image area is performed on the image data in the value image area.

When the tone reproduction process is performed as described above, on the other hand, in a halftone image portion of the original image, a periodicity called a moire fringe is generated due to a peat phenomenon related to a repetition cycle of a threshold matrix used for binarization and a halftone cycle. Striped pattern appears,
In the edge portion of a binary image such as a line drawing or a character, the display dots are sparse, and the edge is cut off (the state of the image is cut off).

Therefore, in order to prevent such image quality deterioration, it is necessary to perform processing for correcting image data in advance before the tone reproduction processing.

In order to prevent the occurrence of moiré fringes, a smoothing (smoothing) process known as a noise countermeasure, that is, a process of weighting and averaging the image data of a plurality of pixels using a smoothing matrix corresponding to a local region is effective. Also, it is known that an edge enhancement process using a secondary fine powder filter (Laplacian filter) called unsharp masking for sharpening an image is effective for edge cut.

Therefore, conventionally, image processing apparatuses include, for example,
As described in Japanese Patent Application Laid-Open No. 61-157165, edge enhancement means, smoothing means, mixing means for mixing the output of the edge enhancement means and output of the smoothing means, and edge detection means for controlling the mixing ratio are provided. Have been.

[Problems to be solved by the invention]

By appropriately mixing the output of the edge emphasizing means and the output of the smoothing means, it is possible to eliminate edges and moire fringes and to form a high quality image in which the character image portion and the halftone dot image portion are smoothly connected.

However, in the conventional image processing apparatus, apart from the edge emphasizing and smoothing means, an edge detecting means for controlling the mixing ratio of the outputs of these means is provided, so that the configuration is complicated and expensive. There was a problem.

The present invention has been made in view of the above problems, and has as its object to provide an image processing apparatus that can prevent edge cuts and moire fringes with a simple configuration.

[Means for solving the problem]

SUMMARY OF THE INVENTION In order to solve the above-described problems, the present invention provides an image processing apparatus that reads a document image using an image sensor in which a plurality of reading elements are arranged and outputs an image signal corresponding to each read pixel. Storage means for storing a plurality of lines of image signals; edge enhancement means for inputting the image signals of the plurality of lines stored in the storage means to a filter circuit and performing edge enhancement based on an output from the filter circuit; A smoothing means for inputting image signals of a plurality of lines stored in the means and performing smoothing; a mixing means for mixing an output from the edge enhancing means with an output from the smoothing means; Mixing efficiency changing means for changing a mixing ratio between an output and an output from the smoothing means; That the output of the filter circuit and an input means for inputting to the mixing ratio changing means, and changing the mixing ratio based on the output of the filter circuit in said edge enhancement means.

(Operation)

The image signal read and output by the image sensor is stored in the storage unit. The edge enhancement means performs edge enhancement processing on the stored image signal, and the smoothing means performs smoothing processing. In accordance with the output of the edge enhancement means, the mixing ratio changing means determines the mixing ratio between the output from the edge enhancement means and the output from the smoothing means, and the mixing means determines the mixing ratio between the output from the edge enhancement means and the output from the edge enhancement means. The output from the smoothing means is mixed.

〔Example〕

Hereinafter, an image processing apparatus B incorporated in a digital copying machine
An embodiment of the present invention will be described with reference to the drawings.

The digital copying machine includes an image reader as an image reading device, and a laser printer for forming a color image by electrophotography based on an image signal sent from the image reader. The image processing apparatus B is incorporated in the image reader unit, performs various signal processing on pixel signals obtained by reading an image of a document, and outputs the processed signal as an image signal.

FIG. 13 is a perspective view showing the optical system of the image reader unit, and FIG.
FIG. 14 is a plan view of the image sensor 11, and FIG.
FIG. 3 is an enlarged view schematically showing light receiving sections of CCD sensor chips 11a and 11b.

A document D placed on a platen glass (not shown) is line-scanned in a vertical direction (sub-scanning direction) by a slider 14 having an image sensor 11, and an exposure lamp 17, a rod lens array 15, and an image sensor 11 are provided. R (red), G (green), B
The image is read after being separated into three (blue) additive primary colors.

As shown in FIG. 14, the image sensor 11 is provided with five contact-type CCD sensor chips 11a to 11e so as to be continuous in the horizontal direction (main scanning direction) and alternately constant in the sub-scanning direction. They are arranged in a zigzag pattern with a gap. Because there is a constant pitch in the sub-scanning direction,
A delay occurs in the output signals from the CCD sensor chips 11a, 11c, 11e.This is because the timing of the pulse signal to be applied to the line shift gate of each of the CCD sensor chips 11a to 11e is set, and the above-mentioned CCD sensor chips 11b, 11d are set. Is compensated by delaying the output signal from.

Each CCD sensor chip 11a to 11e has its end
As shown enlarged in the figure, one size is 62.5 μm (d
.. Are arranged in one row.

Each element 12 is divided into three, and one divided area has three primary colors RGB.
A spectral filter is provided so as to receive one color of light.

Such one element 12 corresponds to one pixel obtained by subdividing the original image, and the photoelectric conversion output of one element 12 represents the reflected light intensity of one color of one pixel.

 FIG. 16 is a block diagram of the image processing apparatus B.

In the image sensor 11, in order to increase the reading speed in the main scanning direction, five CCD sensor chips 11a to 11e are simultaneously driven, and valid reading pixel signals for a total of 2928 pixels in total of RGB are sequentially output from each of them.

Simultaneous (parallel) from five CCD sensor chips 11a to 11e
Each of the five systems of photoelectric conversion outputs serially output to a line memory 111, a CPU (central processing unit) 112, and a ROM 11
Each of the following image processing circuits 101 to 110 constituting the image processing apparatus B together with 3 receives signal processing.

First, the data is quantized by a digitization processing circuit 101 having a sample hold circuit and an A / D converter, converted into 8-bit (256 gradation) digital data, and separated into image data of each color by a latch circuit. The signal is input to the channel synthesis circuit 102.

The five-channel synthesizing circuit 102 temporarily stores two lines of image data in a total of 15 (3 × 5) first-in first-out memories for each chip and each color, and adjusts one line to match the image forming process in the laser printer unit. The image data from each chip is sequentially selected and read in a cycle, and
A serial image signal is generated in which the image data for the line is continuous in the pixel arrangement order (reading scanning order). Subsequent signal transmission between each of the image processing circuits 102 to 110 and the laser printer unit is performed by the image clock signal SY serving as a timing reference.
Performed according to NCK.

The image data of each color transmitted simultaneously as a serial image signal is normalized by adjusting the relative ratio between the colors by a white balance correction circuit 103 so that an image of a correct color tone can be formed in the laser printer unit.

Next, the shading correction circuit 104 controls the exposure lamp 17
The light distribution in the main scanning direction (light quantity unevenness) and the sensitivity difference between the elements 12 are corrected, and the data signal proportional to the reflected light intensity is changed in consideration of the reading range of the original D. Then, the data is logarithmically converted in accordance with the visual characteristics and converted into a density data signal proportional to the density of the document D.

As described above, the color correction circuit 105 generates masking processing for generating density data corresponding to the three primary colors Y, M, and C of the printing toner from image data for each of the RGB colors, and generates image data corresponding to Bk (black). BP processing (black plate generation) and UCR processing (under color removal) are performed, and the gamma correction circuit 106 uses a background removal processing for forming a clear image with enhanced overall contrast and operation keys (not shown). Density adjustment processing for forming an image with the specified density is performed.

The color editing circuit 107 performs three types of color image editing processes: negative / positive inversion, color change (color change), and paint (filling).

In addition, the scaling / movement processing circuit 108 uses a thinning method, an arithmetic method, an interpolation method, or the like to form a scaled image that is enlarged or reduced, and an edit image such as movement or mirror inversion.
Processing for changing the output timing and output order of the image data signal or the scanning speed in the sub-scanning direction is performed.

The image data D87-80 subjected to these various signal processings
Is a spatial filter process for preventing the occurrence of edge loss and moiré fringes due to the binarization process performed in the subsequent stage tone reproduction circuit 110 in the MTF correction circuit 109, that is, the edge enhancement process using a second-order differential filter. And a smoothing filter.

Image data D97 to D90 whose values have been corrected by the MTF correction circuit 109.
Is a tone reproduction circuit 11 provided with two types of threshold matrices.
In the area gradation method, an L × n dot matrix in which five dots are assigned to one pixel at 0 is used as a gradation unit section.
The image data is subjected to a binarization process and sent to the laser printer unit as binary image signals VIDEO4-0.

The CPU 112 controls each image processing and the operation of the slider 14, and receives various keys on an operation panel provided on the upper surface of the digital copying machine A, an editor (not shown) for specifying an area for color editing, or a sensor from each unit. Serial communication is performed with a host CPU (not shown) that controls signal input and operation of the laser printer unit. The line memory 111 is used for temporarily storing image data at a specific processing stage, and programs and various data are read from the ROM 113.

 FIG. 1 is a block diagram of the MTF correction circuit 109.

The MTF correction circuit 109 includes a memory unit 701 that delays the image data serially input from the scaling / movement processing circuit 108 by four lines, and a high-frequency image data output from the memory unit 701 using a secondary differential filter. An edge enhancement processing unit 702 that performs enhancement processing, a smoothing processing unit 703 that performs a smoothing process in parallel with the high-frequency enhancement processing of the edge enhancement processing unit 702, an output of the edge enhancement processing unit 702, and an output of the smoothing processing unit 703. And a mixing processing unit 704 for mixing.

The memory unit 701 is provided in common to the edge enhancement processing unit 702 and the smoothing processing unit 703, and the spatial filter processing performed by both units 702 and 703, that is, one pixel (pixel of interest)
The image data D8 serially input is performed in accordance with the pipeline processing of sequentially performing an arithmetic operation for correcting the image data corresponding to the pixel based on the image data of the surrounding pixels for all the pixels.
7 to 80 for four lines, and five lines [(n−2) to (n +) together with newly input image data D87 to D80.
2)] is output in parallel for each pixel in accordance with the signal SYNCK for each line. For this reason,
The memory unit 701 includes four line memories 7 of a first-in first-out method.
11 to 714, and image data D87 to 80 input from the previous stage
Are stored in the line memory 714 first, and then read out in the pixel arrangement order.
Serially transferred to 2,711. That is, when the image data D87 to D80 of the (n + 2) th line is written to the line memory 714, the line of the pixel of interest, that is, the image data D87 to D80 of the nth line is read from the second line memory 713.
Is read from the line memory 711 at the final stage of the transfer.
Image data of the (n-2) th line input before the line
D87 to D87 are read.

The edge enhancement processing unit 702 is configured to output the second derivative image data ED08-0
Second derivative filter unit 720 for generating 0, emphasis control ROM 721 for increasing or decreasing the value of second derivative image data ED08 to 00, emphasis control RO
Image data ED27-20 output from M721 and memory unit 701
And an adder 722 for adding the image data D87-80 of the n-th line input from the
Is output.

In the secondary differential filter unit 720, the signal SY is output from the memory unit 701.
Simultaneously input one pixel at a time in synchronization with NCK (n-
2) second-order differential spatial filter processing for generating second-order differential image data ED08 to 00 corresponding to the second-order differential image (Laplacian image) of the original image based on the image data D87 to 80 of the n, (n + 2) th lines Is performed. In this filter processing, the directionality of the filter processing is switched by the selection signal SHARP / MODE according to a threshold matrix used in the binarization processing described later.

FIGS. 2A and 2B are diagrams showing the directionality of the second-order differential spatial filter processing.

In the spatial filter processing represented graphically by the weight matrix (mask) M1, the pixel of interest corresponding to the center of the matrix and the four peripheral pixels located one pixel apart in both the main and sub scanning directions are processed. By applying a weighting factor (weighting) of “1” to the target pixel and “−1/4” to each peripheral pixel, and calculating the sum of the image data D87 to D80 of these five pixels, A Laplacian image for enhancing the edge of is generated. In the spatial filter processing indicated by the matrix M2, data processing is performed on a target pixel and four peripheral pixels located one pixel apart in an oblique direction having a 45-degree inclination with respect to both scanning directions. Thus, a Laplacian image for preventing edge loss in the oblique direction is generated. A specific circuit configuration for implementing such a filtering process will be described later. The 9-bit secondary differential image data ED08 to ED00 output from the secondary differential filter unit 720 are added to the enhancement control ROM 721, and are used as a mixed control signal of the output of the edge enhancement processing unit 702 and the output of the smoothing processing unit 703. Output to mixing processing section 704.

In the emphasis control ROM 721, the CPU 112
Sharp data provided by SHARP ・ DATA (3 bits)
, The image data ED27 to ED20 obtained by multiplying the secondary differential image data ED08 to ED08 input as the lower address by a predetermined number are read out.

FIG. 3 is a graph showing the relationship between the input and output of the emphasis control ROM 721, and FIG. 4 is the sharpening data SHARP • DATA and the slope t in FIG.
It is a figure showing the relation with anθ. FIG. 4 also shows the matching relationship between the sharpened data SHARP.DATA and the smoothing matrix size selected by the smoothing processing unit 703.

As shown in FIG. 3, the secondary differential image data ED08 to 00 of "-E" to "E" are truncated to prevent the noise component from increasing, and the secondary differential image data having an absolute value equal to or larger than a constant value "E" The doubling correction is applied only to the image data ED08 to ED00.

Referring to FIG. 4, for example, when standard sharpness (sharpness) is designated by an operation key outside the figure,
The sharpened data SHARP • DATA becomes “3” (011B), and tan θ representing the inclination of the straight line on the graph, that is, the value of the enhancement coefficient is “1”. At this time, image data ED27 to ED20 having the same value as the input second differential image data ED08 to ED00 are read from the emphasis control ROM 721. When SHARP.DATA is "6", image data ED27 to ED20 obtained by multiplying second differential image data ED08 to ED00 by 1.75 are read. As described above, the secondary differential image data ED08 to ED00 are linearly converted in accordance with the magnification determined by the specified sharpness.

The adder 722 performs an operation corresponding to an operation of subtracting a Laplacian image of a predetermined size from the original image, and the arithmetic sum thereof is used as image data EGD37 to 30 emphasizing a high frequency in a spatial frequency.
Is output as

On the other hand, in parallel with the high-frequency emphasis processing performed by the edge emphasis processing section 702, the smoothing processing section 703 receives (n−2), (n−1), n, (n +) input from the memory section 701.
A spatial filter process is performed as a smoothing process for averaging the weights of the image data D87 to D80 of the 1) and (n + 2) lines in the sub-scanning direction and the main scanning direction. In this filter processing, as described above, the selection signal SMOOTH • MODE1,2 and the selection signal The size of the smoothing matrix is selected by the selection signals SMOOTH · LVL1,2 (see FIG. 4).

FIGS. 5A and 5B are diagrams showing a smoothing matrix.

Each of the matrices M3 and M4 has a matrix size of 5
× 5, 3 × 3, and in both cases, a larger load coefficient is given closer to the center.

By the smoothing processing shown by these matrices M3 and M4, the image data D87 to 80 of the pixel of interest is replaced with a weighted average value of 5 × 5 or 3 × 3 data by weighting shown in FIG. Output as data SMD27-20. The image data SMD27 to SMD20 are standardized by a predetermined coefficient operation so as not to exceed the maximum value "255" of the 8-bit data.

A specific circuit configuration for implementing such a filtering process will be described later.

Image data SMD output from smoothing processing unit 703
27 to 20 are output image data EGD37 of the edge enhancement processing unit 702.
30 is added to the mixing processing unit 704 in synchronization with.

The mixing processing unit 704 outputs the secondary differential image data ED08 to ED08-0 output from the secondary differential filter unit 720 of the edge enhancement processing unit 702.
0 is converted to absolute value data ED17 to ED10, the absolute value calculation circuit 741 which outputs the upper 3 bits as mixed control data MIX7 to MIX5, and image data EG which is the output of the edge enhancement processing unit 702.
A mixed standard ROM 742, 743, in which a lower address is specified by D37-30 and image data SMD27-20 output from the smoothing processing unit 703, respectively, and an upper address is specified by commonly provided mixing control data MIX7-5, The outputs of the standard ROMs 742 and 743 are added, and the arithmetic sum data thereof is converted into image data D97 to D90.
And an adder 744 that outputs the result to the adder 744.

The secondary differential image data ED08 to ED00 have a value of "-255 to 255" with the most significant bit of 9 bits as a sign bit, and a negative number represented by a two's complement by the absolute value calculation circuit 741 corresponds to the absolute value. Is converted to a positive number. Therefore, the absolute value data ED17 to ED10 have a value of “0 to 255”, and the mixing control data MIX7 to MIX5 represent each stage of “0 to 255” divided into eight stages in “32” steps.

FIG. 6 shows mixing control data MIX7 to MIX5 and image data EGD37.
30 is a diagram showing a relationship between the image data SMD and the mixed amount of image data SMDs 27 to 20. FIG.

From the mixed standard ROMs 742 and 743, according to the mixed control data MIX7 to MIX5 from the data stored in advance,
Data of a value obtained by multiplying the image data EGD37 to 30 or the image data SMD27 to 20 by the coefficient shown in FIG. As this coefficient, a value is set such that the edge emphasis processing is prioritized over the smoothing processing as the mixing control data MIX7 to MIX5 increases, and the arithmetic sum in the adder 744 does not exceed "255". I have.

For example, when the mixed control data MIX7 to MIX5 is "2" (010B), the data of the value obtained by multiplying the image data EGD37 to 30 by 2/7 from the mixed standard ROM742 is the image data SM from the mixed standard ROM743.
Data of a value obtained by multiplying D27 to D27 by 5/7 is read out and added to the adder 744, respectively.

As described above, in the present embodiment, the image data EG is generated by the second differential image data ED08 to ED08 generated for the edge enhancement processing.
Since the mixing of D37 to D30 and the image data SMD27 to SMD20 is controlled, there is no need to separately provide a means for generating a mixing control signal, and the circuit configuration is simplified.

FIG. 7 is a block diagram of the secondary differential filter unit 720 of FIG.

(N−2), n, (n +) input from the memory unit 701
2) The image data D87 to D80 of the line are delay circuits 751 to 755 and 756 to 76, respectively, which constitute the matrix register 750.
0, 761 to 765, sequentially delayed in synchronization with the signal SYNCK.

Delay circuits 755, 753, 751, 760, 758, 756, 765, 763,
If the outputs of 761 are respectively,..., At the timing of the filter processing,
Others are associated with peripheral pixels. Is the adder 770
Others are selectors 76 for selecting the direction of processing.
Entered in 6. When the selection signal SHARP MODE is "H",
The selector 766 selects, as processing in the scanning direction, and when “L”, processing in the oblique direction is performed.
Select,. The four peripheral pixel data selected by the selector 766 are added by an adder 767, and the arithmetic sum data is multiplied by a weighting factor, that is, "-1/4" by a multiplier 768 and a two's complement circuit 769. After that, it is input to the adder 770. In the adder 770, the data of the target pixel and the data of the peripheral pixels are added to generate a digital Laplacian image by a two-dimensional secondary spatial differentiation operation.

FIG. 8 is a block diagram of the smoothing processing unit 703 of FIG.

The smoothing processing unit 703 includes the above-described matrices M3 and M4
Calculation unit for calculating the average load in the sub-scanning direction at
771a and a calculation unit for calculating the average load in the main scanning direction
771b, and by using the same circuit configuration for both arithmetic units 771a and 771b, the layout pattern is simplified with the gate array. That is, each operation unit 771
Reference numerals a and 771b denote delay circuits 772a to 781a and 772b to 781b for shifting input data in synchronization with the signal SYNCK, input selectors 795a to 798a and 795b to 798b, and a multiplier 782a to which a predetermined weighting factor is given as a multiplier. ~ 788a, 782b ~ 788b, adder
789a to 793a, 789b to 793b, and output selectors 794a and 794b for selecting a matrix size are provided. However,
The input selectors 795a to 798a of the arithmetic unit 771a always output the delay circuits 773a to 776a by the "L" signal SMOOTH MODE1.
, And the input selectors 795b to 798b of the arithmetic unit 771b are fixed to always select the outputs of the delay circuits 777b to 780b by the signal SMOOTH MODE2 of "H".

The output selectors 794a and 794b each have a choice of inputs, outputs Fa and Fb of the weighted average of five pixels, outputs Fa and Fb, outputs Ha and Hb of the weighted average of three pixels, and an output S which is a through value of the pixel of interest.
a, Sb are added.

When outputs Fa and Fb are selected, smoothing processing by matrix M3 is performed. When outputs Ha and Hb are selected, processing by matrix M4 is performed. By selecting the combination of SMOOTH · LVL1,2, the smoothing matrix can be a deformation load matrix having different numbers of target pixels in the main and sub-scanning directions as shown in FIG.

The image data D97 to D90 pre-processed by the MTF correction circuit 109 as described above are subjected to a binarization process by the next-stage tone reproduction circuit 110.

 FIG. 10 is a block diagram of the tone reproduction circuit 110.

The tone reproduction circuit 110 compares the image data D97 to D90 (8 bits) from the MTF correction circuit 109 with the threshold data SD (8 bits) read from the ROM 113, and calculates five 2 It outputs value data, and a gradation pattern generation RAM (hereinafter referred to as “RA”) for temporarily storing threshold data SD.
M ") 201-205, latch circuits 211-215 for latching threshold data SD read from RAMs 201-205 to synchronize with image data D97-90, threshold data SD from latch circuits 211-215 and image Five comparators 221-225 for comparing the data D97-90 with the data D97-90 and outputting an image signal obtained by binarizing the image data D97-90, and an address counter 23 for generating an address for reading the threshold data SD from the RAM 201-205.
2, 234, and an address selector 236 for selecting the read address buses XA and YA from the address counters 232 and 234 and the write address bus MA from the CPU 112.

The RAMs 201 to 205 store two types of data sets corresponding to image formation of 8 gradations suitable for a character image and 29 gradations suitable for a halftone image, that is, one of a gradation pattern F and a gradation pattern G described later. It stores the threshold data SD group to which it belongs,
The threshold data SD is transferred from the ROM 113 and stored so as to form the gradation pattern F or G according to the selected image forming mode.

When transferring data from the ROM 113, the address selector 236
Address bus MA is selected, and RAMs 201-205 are
Specifies the write address, and the CPU data bus MD7
Threshold data SD is written from ０0. Threshold data SD
When reading from RAM 201-205, address selector 2
36 selects the read address buses XA and YA from the address counters 232 and 234, allocates them to the upper bits and the lower bits, and outputs them to the address terminals of the RAMs 201 to 205.

One of the address counters 232 is a signal SYN which serves as a reference for the transfer timing of the image data D97 to D90 for one pixel.
The counter is incremented by the input of CK, and the other address counter 234 is a horizontal synchronization signal TG which is a reference of one line cycle.
To count up.

Further, the threshold data SD of the gradation pattern F is stored in the RAM 201 to 205.
Is stored, the address counter 232 is set to “0”.
To "6", the address counter 234 holds the clear state, and when the threshold data SD of the gradation pattern G is stored in the RAM 201 to 205, the address counter 234
2 counts from "0" to "13", and the address counter 234
Is initialized by the CPU 112 to count “0” to “1”.

Therefore, the RAMs 201 to 205 perform binarization processing for every seven pixels when the threshold data SD of the gradation pattern F is stored, and for one line when the threshold data SD for the gradation pattern G is stored. At this time, the same address is specified for every 14 pixels.

By such addressing, the threshold data SD stored in the RAMs 201 to 205 is read one by one, and the read five threshold data SD are read by the latch circuit 211, respectively.
Latched to ~ 215.

A total of five threshold data SD output from the latch circuits 211 to 215 after the transfer timing is adjusted are image data for one pixel which are commonly provided to the comparators 221 to 225, respectively.
It is compared with D97-90 at the same time.

As a result, the image data D97 to D90 are binarized based on the threshold data SD, and five binary data for one pixel are simultaneously output from the comparators 221 to 225. These binary signals are inverted by the inverters 230, 230,... And then sent to the laser printer unit as gradation-reproduced image signals VIDEO4-0.

FIG. 11 is a diagram showing an image formed by the gradation pattern F, and FIG. 12 is a diagram showing an image formed by the gradation pattern G. In these figures, the magnitude of the numbers is the threshold data SD
It corresponds to large and small.

In the case of the gradation pattern F, each of the RAMs 201 to 205 has threshold data SD including seven threshold data SD of “1” to “7”, which are thresholds of each step obtained by dividing “0” to “255”. The groups are stored one by one as described above. In this case, the gradation unit section H1 in the formed image is a 7 × 1 dot matrix, and a gradation reproduction image of 8 (= 7 × 1 + 1) gradations is obtained. The formation can take place.

Each of the comparators 221 to 225 outputs an “H” level signal when the value of the image data D97 to D90 commonly applied to each input terminal Q is larger than the value of the threshold data SD applied to each input terminal P. That is, image data D97 to 90 of each pixel j, (j + 1),... (J + 7) in lines 1 to 5
Are all “4”, the threshold data
When the value of SD is equal to or less than “3”, the output of each of the comparators 221 to 225 becomes “H”.

In FIG. 11, hatched portions indicate display dots to which a color material is attached during image formation, and white portions indicate non-display dots where the base of the image forming paper appears as it is. In the example shown in the figure, the dots corresponding to the threshold data SD of “1” to “3” are display dots, but if the image data D97 to D90 is “5”, “4” on the right side of “2” is displayed. Is also a display dot, and if the image data D97 to D97 are "6", the dot corresponding to "5" on the left of "3" is also a display dot. That is, a section area equal to the gradation unit section H1
Within h1, display dots increase one by one alternately to the left and right of the dot (growth nucleus) corresponding to "1". In the case of this gradation pattern F, the growth nuclei are arranged in a line in the sub-scanning direction. Edge breaks in the main scanning direction easily occur in the character image portion.

Therefore, in this case, the edge enhancement processing unit 70 described above is used.
In step 2, the secondary differential image data ED08 to ED00 in the scanning direction is generated by the load matrix M1 for filtering (see FIG. 2).

In the case of the gradation pattern G, as shown in FIG. 12, the gradation unit section H2 is a section area h2a formed on an odd line.
14 × consisting of the divided area h2b formed on the even-numbered line
2 dot matrices, which can form an image of 29 gradations.

In this case, looking at one of the divided areas h2a or h2b, as in the case of the gradation pattern F, as the document D becomes darker, the left and right growth nuclei corresponding to “1” or “2” are alternately left and right. Although the number of display dots increases one by one, edge breaks in a direction inclined at 45 degrees to the scanning direction are likely to occur. Therefore, the edge enhancement processing unit 702 generates the second derivative image data ED08 to 00 in the oblique direction using the matrix M2. Generation occurs.

In the above-described embodiment, the smoothing processing unit 703 of the MTF correction circuit 109 includes two arithmetic units 771a and 771 having the same circuit configuration.
b, the number of pixels in the main scanning direction to be smoothed can be increased and the smoothing process can be diversified by connecting a further similar calculation unit at the subsequent stage of the calculation unit 771b. it can.

In the above-described embodiment, the output of the edge enhancement unit 702 and the smoothing processing unit 703 in the mixing processing unit 704 of the MTF correction circuit 109 is obtained by the mixing standard ROMs 742 and 743, the adders 744, and the mixing control data MIX7 to MIX5. Image data EGD37-30,
Although mixing adjustment of SMDs 27 to 20 is performed, in order to simplify the configuration, the mixing standard ROMs 742 and 743 and the adder 744 are omitted, and a signal selecting means is provided instead, and the mixing control data MIX7
5, one of the image data EGD37 to EGD30 and SMD27 to 20 may be selected as the output image data D97 to D90.

〔The invention's effect〕

According to the present invention, the output of the secondary differential filter of the edge enhancement means controls the mixing ratio of the outputs of the edge enhancement means and the smoothing means or the selection of one of the two outputs.
There is no need to provide a separate means for generating a mixing control signal,
The structure can be simplified and the cost can be reduced.

[Brief description of the drawings]

1 shows an embodiment of the present invention, FIG. 1 is a block diagram of an MTF correction circuit, FIGS. 2 (a) and 2 (b) show directions of second-order differential spatial filtering, and FIG. 4 is a graph showing the relationship between the input and output of the control ROM, FIG. 4 is a diagram showing the relationship between the sharpened data and the inclination in FIG. 3, FIG. 5 is a diagram showing a smoothing matrix, and FIG. FIG. 7 is a block diagram of a secondary differential filter unit in FIG. 1, FIG. 8 is a block diagram of a smoothing processing unit in FIG. 1, and FIG. 9 is an output selector. FIG. 9 is a diagram showing a relationship between a combination of selection signals to be added and a matrix size.
10 is a block diagram of a tone reproduction circuit, FIGS. 11 and 12 are plan views showing formed images, FIG. 13 is a perspective view showing an optical system of an image reader unit, and FIG. 14 is a plan view of a image sensor. ,
FIG. 15 is an enlarged view schematically showing a light receiving section of the CCD sensor chip of FIG. 14, and FIG. 16 is a block diagram of the image processing device. 701: memory unit (memory means), 702: edge enhancement processing unit (edge enhancement means), 703: smoothing processing unit (smoothing means), 704: mixing processing unit (output adjustment means), 720 ... 2 Next differential filter unit, B: image processing device, M3, M4: smoothing matrix, VIDEO4-0: image signal.

Continuation of the front page (56) References JP-A-62-185466 (JP, A) JP-A-61-157169 (JP, A) JP-A-61-66473 (JP, A) JP-A-2-186876 (JP) , A) JP-A-1-123569 (JP, A) JP-A-1-151878 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60

Claims (1)

(57) [Claims] An image processing apparatus for reading a document image by an image sensor having a plurality of reading elements arranged and outputting an image signal corresponding to each read pixel, wherein a plurality of lines of image signals obtained by reading are stored. Storage means for inputting image signals of a plurality of lines stored in the storage means to a filter circuit and performing edge enhancement based on an output from the filter circuit; and Smoothing means for inputting image signals of a plurality of lines to perform smoothing, mixing means for mixing the output from the edge enhancement means and the output from the smoothing means, and the output from the edge enhancement means and the smoothing means Mixing efficiency changing means for changing the mixing ratio with the output from the filter, and a filter circuit in the edge enhancement means And an input means for inputting the output to the mixing ratio changing means for changing the mixing ratio based on the output of the filter circuit in said edge enhancement means, an image processing apparatus characterized by.