JP2892958B2 - Wafer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer, and more particularly, to a semiconductor wafer capable of preventing defects such as chipping at a joint between a contour of a wafer and a notch. It is. 2. Description of the Related Art Generally, transistors and integrated circuits (I
C) and in the manufacture of semiconductor devices such as large-scale integrated circuits (LSI), a wafer made of a semiconductor material such as silicon (Si) is diffused, coated with resist, etched,
When performing processing such as vapor deposition, if foreign matter such as minute dust and chipping pieces adhere to the surface of the wafer, it may cause scratches on the surface of the wafer, cause unevenness in film thickness, or cause defects such as defective conveyance. Would. There are various causes for the generation of such foreign matter. One of the causes is that, for example, when the outer peripheral portion of the wafer collides with some transport mechanism or the wafers come into contact with each other when the wafer is transported. It is known that a part of the outer peripheral portion of the wafer itself is deficient, and chipping pieces resulting from the deficiency adhere to the surface of the wafer as foreign matters and cause various defects. Therefore, conventionally, in order to prevent such a defect in the outer peripheral portion of the wafer, it has been proposed to chamfer both main surfaces of the outer peripheral portion of the wafer by mechanical or chemical means. However, chipping of the wafer cannot be completely prevented by only chamfering both main surfaces of the outer peripheral portion of the wafer. The inventors of the present invention have conducted intensive studies to investigate the cause of such chipping, and as a result, the following important facts have been found. That is, in general, a flat portion called an orientation flat (main flat) is formed on a wafer by cutting a part of the wafer straight to indicate its crystal axis direction and perform positioning. However, due to the formation of such a flat portion, an acute-angled bent portion is formed at a junction between the flat portion and the outline of the wafer. As a result, the bonded portion is liable to cause chipping, and when the wafer is transferred, the bonded portion collides with the guide of the air bearing or comes into contact with another wafer, so that the bonded portion is lost and the chipping piece is lost. Is what will happen. [0006] In addition to the linear cutting as described above for positioning the wafer, a curved notch may be provided in a part of the wafer. A sharp bend is formed in the portion, causing the same problem as described above. [0007] In particular, the present invention is directed to a wafer using a curved notch, and accordingly, an object of the present invention is to provide chipping at a joint between a wafer outline and a curved notch. It is an object of the present invention to provide a wafer capable of preventing generation of foreign matter and other various defects due to the above. [0008] The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the joint between the outer shape line of the wafer and the curved notch is chamfered in a planar shape and in a thickness direction, and the joint is formed with respect to the main surface and the main surface of the semiconductor wafer. The semiconductor wafer has a curved shape in a parallel plane. According to the above-mentioned means, since the joint between the outer shape line of the wafer and the curved notch is chamfered in a planar shape and in a thickness direction, the joint of the above-mentioned joint is formed. There are no sharp corners or bends not only in the planar shape but also in the thickness direction, and the above-mentioned joint does not cause chipping. Therefore, it is possible to prevent the generation of foreign matter and other various defects due to chipping. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. FIGS. 1 and 2 show an embodiment of a wafer according to the present invention. FIG. 1 is a plan view thereof, and FIG. 2 is an enlarged sectional view. The wafer 1 of this embodiment has a circular shape formed by, for example, slicing a single crystal of silicon (Si), a part of which shows the direction of the crystal axis and positions the wafer 1 in various processes. A main flat, that is, an orientation flat (OF) 2 is cut and formed in a straight line as a positioning removing section for the positioning. The outer peripheral portion 3 of the wafer 1 is chamfered, for example, in an arc shape as can be seen from FIG. This chamfering prevents the outer peripheral portion of the wafer from being damaged, and prevents chipping at the outer peripheral portion of the wafer. Further, the wafer 1 in this embodiment is chamfered into an arc shape shown by a solid line at the joint 4 between the both ends of the orientation flat 2 and the outline of the wafer 1 and shown by a solid line. The corner area of the joint 4 is configured to prevent chipping during various processes of the wafer 1 and to prevent defects such as generation of foreign matter as chipping pieces due to chipping. That is, the chamfered region 5 of the joint 4 in the embodiment of FIG. 1 is a region surrounded by a two-dot chain line, and the inner edge of the chamfered region 5 has a common inner shape inscribed in the outer shape of the wafer 1 and the orientation flat 2. It is defined by the arc of the tangent circle. When performing the arc-shaped chamfering of the joint portion 4, a preferable chamfering range of the chamfered area 5 is determined as follows, which will be described in detail with reference to FIG. In FIG. 3, the radius of the wafer 1 is R and its center is O ₁ . When the distance from the center O ₁ to the orientation flat 2 is y, and a perpendicular line is dropped from the O ₁ to the orientation flat 2, the intersection P is an intermediate point of the orientation flat 2, and the total length of the orientation flat 2 before chamfering is performed. From the point P, the orientation flat 2
The distance between the bonding portion 4 and the outer line of the wafer 1 is b. The relationship between the length of the orientation flat 2 and the thickness of the wafer 1 and the diameter of the wafer is as shown in Table 1 in a mirror wafer (mirror wafer) state.
It is defined in the EMI standard. [Table 1] On the other hand, since it is necessary to align the wafer 1 using the orientation flat 2, the orientation flat 2 has a minimum length of a flat portion that must be provided for accurate alignment. Assuming that a half of the length is a, the length a is the distance from the point P to the inner contact point i ₁ between the common inscribed circle and the orientation flat 2. Reference numeral 6 denotes a roller for alignment,
Alternatively, a photoelectric conversion element or the like may be used as the positioning means. If the inner contact point between the common inscribed circle and the outline of the wafer 1 is i ₂ , the center O ₂ of the common inscribed circle is the wafer 1
Located straight line connecting the center O ₁ and the inner contact i ₂ of the angle between the straight line and the straight line O ₁ P is represented by theta. Accordingly, the radius r of the common inscribed circle inscribed in both the outline of the wafer 1 and the orientation flat 2 is obtained as follows. First, the minimum length required for alignment by the roller 6, that is, the length a (a = Pi ₂ ) of the flat portion of the orientation flat 2 that is not chamfered is represented by the following equation. 1) Next, the length y of the vertical O ₁ P from the center O _{1 of the} wafer 1 to the orientation flat 2 is given by: From the right triangle O ₁ P4, y ² = R ²
Since −b ² , By substituting equation (3) into equation (2), the following equation is obtained. From the equation (1), the following equation is obtained. From sin ² θ + cos ² θ = 1, from the equations (4) and (5), the following equation is obtained. When the equation (6) is rearranged, the following equation is obtained. Therefore, in the present embodiment, the chamfered area 5 in the joining area between the outline of the wafer 1 and the orientation flat 2 is, as shown in FIG.
The chamfering may be performed along an arc of any radius as long as it is within the arc of the common inscribed circle having the radius r in the equation (7) or a region outside the arc. That is, the radius r of a common inscribed circle with both the outline of the wafer 1 and the orientation flat 2
May be within the range shown by the following equation, and the chamfering may be performed in an arc shape within the range of the radius r. (Equation 8) As a result, according to this embodiment, no sharp corners or bends are present in the joining region between the outer shape of the wafer 1 and the orientation flat 2, so that
For example, it is possible to prevent the bonding area from colliding with, for example, a guide of an air bearing or coming into contact with another wafer when the wafer 1 is transferred, thereby preventing chipping pieces from being lost. Also, in addition to the foreign matter defect due to the generation of such chipping pieces, the conveyance failure due to the sharp corner portion being caught by the guide of the air bearing at the time of conveyance, and further, the air flow is disturbed at the sharp corner portion at the time of resist coating. It is possible to remarkably reduce defects such as poor resist film thickness due to partial variation in resist film thickness, which is particularly suitable for large-diameter wafers. FIG. 4 is a plan view showing another embodiment of the wafer according to the present invention. In this embodiment, the joining area between the outline of the wafer 1 and the orientation flat 2 is straightly chamfered within a chamfered area 5 indicated by oblique lines.
In this case, the maximum chamfered area of the chamfered area 5 is, as described above with reference to FIG. 3, the inner contact point i of the common inscribed circle with both the outline of the wafer 1 and the orientation flat 2.
Defined by a straight line connecting the ₁ and i _2. The radius r of the common inscribed circle can be selected within the same range as shown in the above equation (8). Also in this embodiment, since there are no sharp corners or bent portions at the joint 4 between the outline of the wafer 1 and the orientation flat 2, foreign matter defects due to the generation of chipping pieces, defective conveyance, and resist film. Thickness defects can be greatly reduced. The chamfering according to the present invention is not limited to the arc-shaped or straight-line shape of the above-described embodiment, but may be any curve-shaped or polygon-shaped chamfered shape as long as it can eliminate sharp corners. It can also be shaped. Further, the present invention can be applied to a case where a sub-flat, that is, a second flat is provided in addition to the main flat, that is, the orientation flat. That is, in this case, as shown in FIG. 5, the chamfering region 5 of the joining region between the both ends of the orientation flat 2 and the outline of the wafer 1 is chamfered, and both ends of the second flat 7 and the outline of the wafer 1 are formed. Is also in the second region as in the range indicated by 5a.
Chamfering is performed along an arc of a common inscribed circle that inscribes both the flat 7 and the outline of the wafer 1 or a straight line connecting the internal contacts or in a region outside the same. Further, in addition to the flat portions such as the orientation flat 2 and the second flat 7, the present invention can be applied to a case where a curved positioning notch is formed in the wafer 1 as exemplified by reference numeral 8 in FIG. can do. That is, in this case, the joint area between the both ends of the positioning notch 8 and the outline of the wafer 1 is set to a common area inscribed in both the positioning notch 8 and the outline of the wafer 1 as shown by a range 5b. The chamfering may be performed along the arc of the tangent circle or in an area outside the arc. The chamfering of the present invention may be performed simultaneously with the formation of the orientation flat 2 or the chamfering in the thickness direction of the outer peripheral portion 3. The simultaneous chamfering may be performed at the same time, and such simultaneous chamfering is very good in work efficiency, but may be chamfered separately. Of course, the present invention does not necessarily require chamfering in the thickness direction of the outer peripheral portion 3 of the wafer 1. Various apparatuses can be used for chamfering according to the present invention. FIGS. 6 to 8 show examples. The chamfering apparatus shown in FIG. 6 is of a so-called shape-following type, in which a grindstone 8 having a straight groove 9 is rotated and moved in the horizontal and vertical directions to perform chamfering. Chamfering in the thickness direction can also be performed. The chamfering apparatus shown in FIG. 7 is of a so-called shape transfer type, in which a grindstone 10 having a curved groove 11 conforming to the chamfered shape in the thickness direction of the outer peripheral portion 3 of the wafer 1 is horizontally moved while rotating. Accordingly, in addition to chamfering the outer peripheral portion 3 of the wafer 1 as shown in FIG. 2, the chamfering regions 5, 5a and 5b shown in FIGS. 3 to 5 can also be chamfered. As described above, the chamfering apparatus shown in FIGS. 6 and 7 can perform both the chamfering of the chamfered areas 5, 5a and 5b and the chamfering of the outer peripheral portion 3 of the wafer 1. The processing may be performed separately, but it is efficient to perform the processing simultaneously. The chamfering apparatus shown in FIG. 8 is for performing chamfering chemically.
The wafer 1 is immersed in an etching solution 14 in an etching bath 13, and the outer periphery of the wafer 1 is etched with the etching solution 14 while rotating together with the rotating finger support 12. In this case, in order to perform the chamfering processing only on the chamfered regions 5, 5a, 5b, the other outer peripheral portion of the wafer 1 is etched with an etching solution 1
It is necessary to mask so as not to touch 4, but after chamfering the chamfered areas 5, 5a, 5b by mechanical grinding in advance,
The entire outer corner may be chemically chamfered in the thickness direction with an etchant. In the case of FIG. 8, the mechanical impact on the wafer 1 can be reduced. The present invention can be applied not only to a wafer made of silicon (Si) but also to a wafer made of various compound semiconductor materials such as germanium (Ge) or gallium arsenide (GaAs) or gallium garnet. As described above, according to the present invention,
Since there are no sharp corners or bends at the junction between the wafer positioning notch and the outer shape of the wafer, sharp corners such as foreign matter failure, transport failure, and resist film thickness failure due to wafer chipping. Alternatively, defects caused by the presence of the bent portion can be significantly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of an embodiment of a wafer according to the present invention. FIG. 2 is an enlarged sectional view of the wafer of FIG. FIG. 3 is a plan view for explaining determination of a chamfer region in the wafer of FIG. 1; FIG. 4 is a plan view of another embodiment of the wafer according to the present invention. FIG. 5 is a plan view showing still another embodiment of the present invention. FIG. 6 is a diagram showing an example of a chamfering apparatus that can be used to carry out the wafer processing method according to the present invention. FIG. 7 is a diagram showing an example of a chamfering apparatus that can be used to carry out the wafer processing method according to the present invention. FIG. 8 is a diagram showing an example of a chamfering apparatus that can be used to carry out the wafer processing method according to the present invention. [Description of Signs] 1 ... Wafer, 2 ... Orientation flat, 3 ... Outer periphery, 4 ... Joint portion between outer shape line of wafer before chamfering and orientation flat, 5,5a, 5b ... Chamfer area, 6 ... Positioning Roller, 7 ... 2nd flat, 8
… Notches for positioning.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Susumu Komoriya               1450 Josui Honcho, Kodaira City, Tokyo Stock Association               Inside the Musashi Plant of Hitachi, Ltd. (72) Inventor Eshiro Egashira               Nishi-Hachiman, Ryuo-cho, Nakakoma-gun, Yamanashi (No address)               Hitachi, Ltd. Musashi Plant Kofu Branch Plant               Inside                (56) References JP-A-58-23430 (JP, A)                 JP-A-53-111277 (JP, A)                 JP-A-56-13728 (JP, A)

Claims (1)

(57) [Claims] Song for outline and contour of the wafer of semiconductor wafers
The joint with the linear cutout is chamfered in a planar shape and in the thickness direction, and the joint is curved in a plane parallel to the main surface and the main surface of the semiconductor wafer. A semiconductor wafer. 2. The chamfering is performed by using the outline of the wafer and the curve.
2. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is formed in a curved shape along a common inscribed circle of the cutout portion or in a region outside the common inscribed circle.