JP2888187B2 - Information detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information detecting device for detecting information recorded on a disk medium such as an optical disk at high density without errors.

[0002]

2. Description of the Related Art As computers have become more sophisticated, it has become possible to process large amounts of data. Along with this,
Large-capacity file devices such as optical disks and magnetic disks have become widespread. The cost reduction of computers and the increase in the capacity of various software have also spurred this, and further high-density file devices have become necessary. The detection reliability of information in a file device that stores a code file is required to be extremely high, such as an error rate of 10 ⁻⁵ or less for an optical disk and 10 ⁻⁹ or less for a magnetic disk. In order to maintain such high-performance information for higher density, advanced signal processing technology is indispensable. For these reasons, in recent years, PRML (Partial Response Maximum Likelihood) described in detail later will be described.
) File devices using signal processing technology are being commercialized one after another.

[0003] The information detection method used in the first generation optical disk is called a peak detection method. In this method, a recording pit position is detected by using a first derivative differential output of a reproduction signal. For this reason, in this method, even if a slight DC fluctuation is superimposed on the reproduction signal, detection can be performed without any problem. However, in order to perform peak detection, it is necessary to use mark position recording, and the S / N (signal-to-noise) ratio of a reproduced signal during high-density recording is greatly reduced as compared with mark edge recording.
There is a problem that it is difficult to increase the density.

The above-described PRML signal processing technique is effective for detecting information from a reproduced waveform of high density without error. The name of this PRML signal processing technology is P
Maximum likelihood detection of R (Partial Response) equalized channel (Maxi
mum Likelihood detection).
However, a Vidabi detector is often used as the maximum likelihood detector. The PRML system has a very good detection performance in the case of a linear input signal, but has a drawback that the margin for the fluctuation in the level of the reproduced signal is very narrow as compared with the above-mentioned peak detection system. In particular, in the case of an optical disk, some measure needs to be taken because the DC fluctuation component in the reproduced signal cannot be ignored.

[0005] The DC fluctuation superimposed on the reproduction signal of the optical disk is mainly caused by the following three factors. (1) Due to birefringence of a material such as a polycarbonate substrate In the circumferential direction of the disk, a DC fluctuation from DC (direct current) to about 10 kHz is observed. (2) What occurs at the beginning of a sector In a sector-divided code file, a preformat area is provided at the beginning of a sector to enable random access. The preformat information stored in the preformat area has a large DC component.
Therefore, it affects data immediately after preformatting. (3) Modulation code The modulation code adopted in the first generation optical disc is a run length limited code (2, 7) RLL code (run length).
th limited code) and is not DC-free, and therefore has a DC fluctuation depending on the information pattern to be recorded. Here, DC-free means that the amplitude of a frequency component near DC in the frequency characteristic of the code itself is zero.

As described above, these causes are complicatedly intertwined,
There is a problem that the performance at the time of level detection or Viterbi detection is extremely deteriorated.

FIG. 10 shows a main part of an information detecting apparatus conventionally proposed for accurately detecting the level of a reproduced signal containing such a DC component. In this device, a reproduced signal 11 is input to a low-pass filter (LPF) 12 to extract a DC component. Then, the output 13 of the low-pass filter 12 is input to a comparator (Comp) 14 as a threshold value, and a detection signal 15 that detects the level of the reproduction signal 11 is obtained. As a result, the influence of the DC fluctuation can be eliminated.

However, the information detection device shown in FIG. 10 follows the DC component included in the code itself, and therefore, if a code that is not DC-free is used, the reliability of the detected data decreases. There is a problem of doing it.

FIG. 11 shows a main part of a conventional apparatus on the premise of Viterbi detection disclosed in JP-A-6-325504. Vidabi decoding circuit 2 of this information detecting device
0 indicates that the output data DRF of the analog-to-digital conversion circuit (not shown) is equalized through an equalizer circuit (not shown) and then input to the arithmetic circuit 21, where the data in the reference area is fetched and the predetermined arithmetic processing is executed. Thus, the center level CEN and the average amplitude S are detected.

Further, the Vidabi decoding circuit 20 inputs the output data DRF of the above-mentioned analog-to-digital conversion circuit to a subtraction circuit (SUB) 22, where it subtracts the center level CEN detected by the arithmetic circuit 21 to obtain a reproduced signal. detecting the RF amplitude value Y _K. On the other hand, the selector (SEL) 23 switches contacts based on the result of decoding one bit before detected by the pattern decoder (DEC) 24, and outputs the amplitude value Y _K or the amplitude value Y of the reproduction signal RF output from the subtraction circuit 22. The output data of the inverting circuit (-1) 25 is selectively output.

The register 24 holds and outputs the output data of the selector 23, and the inversion circuit 25 inverts the sign of the output data and outputs the inverted data. Thereby, the Viterbi decoding circuit 20 switches the contact point of the selector 23 based on the decoding result of the pattern decoder 24, thereby executing a predetermined arithmetic processing to generate the reference value Y _P-1 .

An adder circuit (not shown) provides the reference value Y _P-1
And by adding the amplitude value _{Y K, Y K + Y P} -1
Is detected. The selectors (SEL) 27 and 28 switch contacts based on the decoding result of one bit before detected by the pattern decoder 24, respectively.
Selectively output data of value 0 or S, value -S or 0, respectively, thereby setting a reference value B _K-1 based on the decoding result of one bit before, and obtaining a value S / 2 + B _K-1 , −
Set S / 2 + B _K-1 .

The comparison circuit (CMP) 29 includes a selector 27
By obtaining a comparison result between the output data of the adder 26 and the output data of the adder 26, it is determined whether or not a predetermined relational expression is established. By obtaining a result of comparison with the data, it is determined whether a predetermined relational expression holds.

The pattern decoder 24 includes a comparator 2
Based on the result of the comparison between 9 and 30, a determination is made as to whether or not any of the relational expressions is satisfied. This allows the Viterbi decoding circuit 20 to output the analog-to-digital conversion circuit output data in 1-bit units. Repeat the process to detect the decoding result sequentially,
The reference values Y _P and B _K are set based on the decoding result.

On the other hand, the dividers (1/2) 31 and 32 divide the amplitude values S and -S detected by the operation circuit 21 by 1/2, respectively, and output the result. 34, the output of the divider 31 and 32 from the output data Y _K respectively subtracting circuit 22 the data S / 2 and -S /
2 is subtracted, and the most significant bit of the result of the subtraction is output.
As a result, the subtraction circuits 33 and 34 perform a predetermined operation, and output the operation result to a bit decoder (BITDEC) 3.
5 is output.

On the other hand, the selector 36 outputs the output data of the inverting circuit 37, the dividers 31 and 3 based on the decoding result of one bit before detected by the pattern decoder 24.
2 selectively outputs the output data S / 2 and -S / 2, and the register 38 holds and outputs the selected output data. The inversion circuit 37 receives the output data of the register 38, inverts the sign, and outputs the inverted data. Thereby, in the Viterbi decoding circuit 20, the selector 36, the inverting circuit 37,
The register 38 sets the value of the reference value _BK-1 .

On the other hand, the subtraction circuit 39 includes a register 2
4 is subtracted from the output result of the register 38,
By outputting the most significant bit of the subtraction result, a predetermined operation result is obtained, and this result is output to the bit decoder 35. The bit decoder 35 selectively outputs the output data of the subtraction circuits 33, 34 and 39 to the register 40 based on the decoding result of the pattern decoder 24.

Here, the register 40 is constituted by a 20-bit shift register.
Are configured to sequentially hold and output the decoding result of 20 bits. Further, the Viterbi decoding circuit 20 includes the register 4
A shift register 41 of 20 bits in parallel with 0,
When outputting the decoding result to the register 40, the bit decoder 35 detects the second transition pattern for the decoding result stored in the register 40 and shifts the shift register 41.
To store the flag.

At this time, the Viterbi decoding circuit 20 correctly decodes the decoded data of the register 40 corresponding to the second transition pattern based on the first and third transition pattern detection results detected by the pattern decoder 24. Then, if a negative result is obtained here, the logic level of the data that has not been correctly decoded is corrected based on the flag of the shift register 41, whereby correct data is obtained based on the transition detection result. It can be decrypted.

The arithmetic circuit 21 includes a pattern decoder 2
At 4, the level of +1 to the level of -1 or -1
When the second pattern transitioning from level 0 to level +1 across level 0 is detected, the output data of the analog-to-digital converter (not shown) is captured and held, and when this data is accumulated by a predetermined number, The center level CEN is updated with the average value.

The apparatus shown in FIG. 11 detects a transition pattern in which the signal level of the reproduced signal crosses the center level. Then, the center level is corrected so that the difference between the input level and the center level at that time becomes zero, and Viterbi detection is performed. However, the proposed device has a drawback that the S / N ratio of the detected DC level is low because the DC component is detected only from a specific transition pattern. There is also a problem in that only the partial response channel of class “1” is mentioned.

FIG. 12 shows a main part of an information detecting device proposed in Japanese Patent Application Laid-Open No. 7-45009. The clock mark detection circuit 51 of this device detects a clock mark signal of a servo area. Clock recovery circuit 5
2 is a PLL which converts the clock signal from the detected clock mark.
To play. The A / D conversion circuits 53 and 54 convert the analog reproduction signal into a digital value. Waveform equalization circuit 5
Numeral 5 performs waveform equalization of the digital reproduction signal. The slice detection circuit 56 detects data of the reproduced signal after waveform equalization at a specific slice level. The system controller 57 controls the operation of the entire optical disk device. The ECC control circuit 58 adds an error detection code to the recorded data and corrects an error in the reproduced data.

The SCSI control circuit 59 controls data transfer to the outside of the optical disk device according to the SCSI protocol. The servo mark detection circuit 60 detects a servo mark signal in the servo area. The tracking error signal generation circuit 61 generates a tracking error signal from the detected servo mark signal. The D / A conversion circuit 62 converts the digital tracking error signal into an analog signal. The tracking control circuit 63 controls the tracking position of the optical disc. A reproduction signal input 64 based on pits from the reproduction area of the optical disk is input to the clock mark detection circuit 51 and the A / D conversion circuit 53, and a reproduction signal input 65 based on magneto-optical recording from the rewrite area is A / D.
The signal is input to the D conversion circuit 54. A recording output signal 66 to be recorded on the optical disk is output from the switching circuit 80.

The reproduction signal input 64 is input to the clock mark detection circuit 51, where a clock pit embedded in the servo area is detected, and a clock signal and various signals synchronized with the clock are generated by the clock reproduction circuit 52. Is output to The servo mark in the servo area is converted into a digital value by an A / D conversion circuit 53 and then detected by a servo mark detection circuit 60. From this servo mark, a tracking error signal generation circuit 61 outputs a digital tracking error signal. I do. This digital tracking error signal is supplied to a D / A conversion circuit 6
2 is converted into an analog signal by the tracking control circuit 6
At 3, the track control of the disk is performed.

The first of the data area of the optical disk (not shown)
The header is a prepitted reproduction signal. This is input as a reproduction signal input 64 similarly to the reproduction signal of the servo area, and is converted into a digital value by the A / D conversion circuit 53. Since the reproduced signal only needs to decode the data of the first header, the complex processing of Viterbi decoding is not performed.
The signal equalized by the waveform equalizing circuit 55 and the equalized signal is “0” by a slice detecting circuit 56 at a predetermined slice level.
Data "1" is detected, and the output is input to the system controller 57. The system controller 57 performs control processing for the entire disk device recorded in the first header.

When data is recorded on a disk, a series of data is input from the external input / output terminal 67,
The control circuit 59 controls data transfer divided into sectors. The data in sector units is input to the ECC control circuit 58, where an error correction code is added for each sector, and then input to the switching circuit 80. Pattern generation circuit 9
0 generates a 64-bit repeating pattern of “01” of the second header and a 64-bit random pattern of the third header, and this output is input to the switching circuit 80. The switching circuit 80 switches the test pattern and the transfer data to which the ECC is added between the header part and the data part, and outputs the NRZ recording output signal 66 which does not modulate the data as it is.

When reproducing data from a disc,
The recorded reproduction signal is input as a reproduction signal input 65, and is converted into a digital value by the A / D conversion circuit 54.
The reproduction signal of the “01” pattern in the header is switched by the switching circuit 70 to the prediction control circuit 69 side and input. The prediction control circuit 69 calculates an offset value indicating how much the DC level deviates from the prediction level of the reproduction signal, adds the offset value to a reference prediction amplitude value, and inputs the result to the Viterbi decoding circuit 68 as an initial prediction amplitude value. .

The random pattern of the third header and the reproduced signal of the data portion are input as the reproduced signal input 65 in the same manner as the reproduced signal of the second header, and are converted into digital values by the A / D conversion circuit 54, and then are switched by the switching circuit 70. The input is switched to the Viterbi decoding circuit 68 side. The Viterbi decoding circuit 68
Viterbi decoding is performed while adaptively controlling the predicted amplitude value input from the prediction control circuit 69. The decrypted data is E
The signal is input to the CC control circuit 58, where the error is corrected, and then the external input / output terminal 67
Output. Here, the switching of the switching circuit 70 to the Viterbi decoding circuit 68 side from the third header where random data is recorded starts one segment earlier than the adaptive control of the predicted amplitude value from the original data part. This is because the predicted amplitude value of Viterbi decoding in the original data portion should be more accurately controlled.

In the information detecting apparatus shown in FIG. 12, a test pattern is added to the head of the transmission data thus blocked, and the DC component of the transmission signal is calculated and corrected by the test pattern to detect Viterbi. Is going. However, this apparatus has a problem that the transmission efficiency is lowered because a test pattern needs to be added, and it is difficult to perform high-density recording. In addition, there is a disadvantage that DC fluctuations in one block of transmission data cannot be dealt with at all.

[0030]

Therefore, in order to reproduce high-density information with high quality using a detection method such as Viterbi detection, the following three problems must be solved. (1) Even if a modulation code that is not DC-free is used,
The ability to compensate for DC components during playback. (2) To detect a DC component having an S / N ratio as high as possible. (3) A DC component can be detected from a random reproduced signal.

Accordingly, an object of the present invention is to provide an information detecting device which has improved reliability by compensating for a DC fluctuation component included in a reproduced signal detected from a disk medium.

[0032]

According to the first aspect of the present invention, (a) an adder for adding an offset amount to a reproduction signal detected from a disk medium, and (b) an output of the adder is input. A pulsing circuit for outputting binary information
(C) a filter for inputting binary information output from the pulsing circuit and changing its frequency characteristic, (d) a phase correction circuit for correcting the phase of the reproduced signal to the same phase as the output of the filter, E) a subtractor for generating a difference between the output of the phase correction circuit and the output of the filter; (f) an integrator having a finite time constant to which the output of the subtractor is input; And a division circuit for dividing the output and feeding back the result as the offset amount to the adder.

According to the second aspect of the present invention, (a) an adder for adding an offset amount to a reproduction signal detected from a disk medium, and (b) an output of the adder is input to convert binary information. A pulsing circuit for output, (c) a filter for inputting binary information output from the pulsing circuit and changing its frequency characteristic, and (d) correcting the phase of the reproduced signal to the same phase as the output of the filter. Phase correction circuit and (e)
A subtractor for generating a difference between the output of the phase correction circuit and the output of the filter; (f) an integrator having the output of the subtractor as an input; and (g) a divider for dividing the output of the integrator. (H) a latch circuit that latches the output of the division circuit and feeds it back to the adder as an offset amount, and (l) inputs a regeneration clock to determine the clear timing of the integrator and the latch timing of the latch circuit. The information detection apparatus is provided with a timing generation circuit for generating the information.

Further, according to the third aspect of the present invention, (a) an adder for adding an offset amount to a reproduced signal detected from a disk medium, and (b) an output of the adder is input to convert binary information. A pulsing circuit for outputting, (c) a filter for inputting binary information output from the pulsing circuit and changing its frequency characteristic, and (d) a first latch for holding a level of a reproduced signal. Circuit; (e) a second latch circuit for holding the output of the filter; (f) a subtractor for generating a difference between the outputs of the first and second latch circuits; and (g) this subtractor. An integrator whose input is the output of
(H) a dividing circuit for dividing the output of the integrator;
A third latch circuit that latches the output of the division circuit and feeds it back to the adder as an offset amount;
(V) The information detection device is provided with a timing generation circuit that generates a clear timing of the integrator and a latch timing of the first, second, and third latch circuits by inputting the reproduced clock.

Further, according to the invention of claim 4, (a) an adder for adding an offset amount to a reproduced signal detected from a disk medium, and (b) an output of the adder is inputted and binary information is inputted. A pulsing circuit for outputting, (c) a filter for inputting binary information output from the pulsing circuit to change its frequency characteristic, and (d) a first integrator for inputting a reproduced signal. (E) a second integrator receiving the output of the filter, (f) a first latch circuit for holding the output of the first integrator, and (g) an output of the second integrator. A second latch circuit for holding the first and second latch circuits;
And a subtractor for generating a difference between the outputs of the second latch circuit and (i) a divider for dividing the output of the subtractor;
(V) a third latch circuit that latches the output of the division circuit and feeds it back to the adder as an offset amount, and (v) receives a recovered clock and inputs the first and second integrator latch circuits. The information detection device is provided with a clear timing and a timing generation circuit for generating the latch timings of the first, second, and third latch circuits, respectively.

According to a fifth aspect of the present invention, in the information detecting apparatus according to the first to fourth aspects, a Viterbi detector is used as a pulsating circuit.

By filtering the binary information after pulsing, it is possible to match the channel of the data string having intersymbol interference before pulsing. The output sequence after filtering and b _n, a comparison of sequence c _n obtained by the same phase with a suitable phase correction circuit pulsing circuit input sequence a _n, should both coincide in the absence DC fluctuation and noise . Conversely, the pulsed circuit input sequence a _n
, The same offset amount is added to all the sample values of the in-phase sequence c _n , but the filtered output sequence b _n has no offset. become a specific sequence, the offset amount average value of the difference between the output sequence b _n having the same phase of the sequence c _n is added to the pulsing circuit input sequence a _n.

The detected offset amount is fed back to the input stage of the pulsing circuit to perform offset correction, whereby DC fluctuation can be corrected. Output series b
_{Although the} offset amount can be detected only from the difference between the series c _n in phase with _n , the offset amount having a higher S / N ratio can be detected by averaging. .

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

First Embodiment

FIG. 1 shows the configuration of the information detecting device according to the first embodiment of the present invention. This information detecting device corresponds to the first aspect of the present invention. The reproduction signal 101 is input to an adder 102 and a phase correction circuit 103 of the information detection device. Here, the reproduction signal 101 is a signal obtained by converting a laser beam reflected from an optical disk (not shown) into an electric signal by a photodetector and then performing predetermined processing. In order to obtain such a reproduction signal 101, first, collimated light emitted from a laser diode (not shown) and passed through a collimator lens is focused on a minute spot using an optical lens, and information on an optical disk is written using a servo technique. Irradiate to follow the track exactly. Then, the reflected light obtained from the optical disk is converted into an electric signal. The converted reproduced signal is input to an AGC (automatic gain control) circuit where the amplitude fluctuation is corrected, passes through a band limiting filter, passes through a circuit such as a transversal filter for removing intersymbol interference, and is subjected to filtering processing. The reproduced signal 101 shown in FIG.
Becomes

Note that the reproduced signal 101 may be configured to use an analog signal as it is, but digitization is indispensable when a highly reliable signal processing algorithm is used as a pulse circuit. Therefore, in this embodiment,
The reproduced signal converted into the electric signal is digitized by a circuit such as an A / D converter, and then input to the information detecting device as the reproduced signal 101 shown in FIG.

The reproduced signal 101 input to the adder 102 has the offset amount 1 input from the divider 104.
05 is added. The addition result 106 is the pulse
7 and the binarized information 108 is output as detection information. The pulsing circuit 107 can be composed of, for example, a maximum likelihood detector. The binarized information 108 is input to a filter 109 represented by, for example, a transversal filter. The output 111 of the filter 109 has the same intersymbol interference as the reproduction channel. It is a well-known fact that any channel can be realized by a transversal filter if the reproduction channel is linear.

The output 111 of the filter is supplied to the phase correction circuit 1
03 is input to the subtractor 113 together with the phase-corrected reproduction signal 112 output from the difference signal 1 and the difference signal 1 representing the difference between the two.
14 is generated. Here, the phase correction circuit 103 is a circuit that adjusts the phase of the output 111 of the filter and the phase of the reproduction signal 101 to be the same. The phase correction circuit 103
For example, a time delay circuit or FIFO (first in first out)
It can be constituted by a memory. The difference signal 114 output from the subtractor 113 is input to an integrator 116.

The integrator 116 is a circuit for adding the difference signal 114 for each channel in order to reduce the influence of noise contained in the reproduced signal. However, the difference signal 1
If all 14 are added from the past to the present, it is impossible to cope with DC fluctuation. Therefore, the integrator 116 has a certain time constant, such as a transversal filter.

[0047] The latch circuit 117 ₁ ~117 _n-1 of the integrator 116 in this embodiment first to be sequentially output to the next stage a differential signal 114 (n-1), the first latch circuit 117 ₁ , And an adder circuit 118 for adding the output from the (n-1) th latch circuit 117 _n-1 .
An addition result 119 obtained by adding the n difference signals 114 at different times output from the integrator 116 is input to the divider 104. The divider 104 calculates an average value by dividing the addition number n of the integrator 116 by the numerical value n. Assuming that the offset amount superimposed on the reproduction signal 101 is x, the average value is an offset amount 1 representing -x whose sign is reversed.
05. The offset amount 105 is input to the adder 102, where feedback control is performed. by this,
The DC component superimposed on the reproduction signal 101 can be compensated for each discrete time, and accurate information detection becomes possible.

Second Embodiment

FIG. 2 shows an information detecting device according to a second embodiment of the present invention. This information detecting device corresponds to the invention described in claim 2. In the second embodiment, an adder 102, a phase correction circuit 103, a pulsing circuit 107, a filter 109, and a subtractor 113 are provided as in the first embodiment. The difference signal 114 generated by the subtractor 113 is input to the integrator 122 with a clear signal. In the integrator 122 with a clear signal, a synchronous clock pulse (PCL) extracted from the reproduced signal by a PLL (Phase Locked Loop) circuit (not shown) is provided.
K) The zero clear signal 125 is input at predetermined time intervals from the timing generation circuit 124 receiving the supply of 123.

The integrator 122 with the clear signal outputs the difference signal 1
Adder 1 for adding 14 to the addition result up to one clock before
27, and a latch circuit 128 for holding the addition result. The content latched by the latch circuit 128 is fed back to the adder 127 to add new difference signals 114 one after another. Further, the integration result thus far held in the latch circuit 128 is output to the external divider 129. The zero clear signal 125 is input to the latch circuit 128 to clear its contents to zero at the above-mentioned predetermined time interval.
This corresponds to the time constant in the information detection device of the embodiment.

The output 131 of the divider 129 is input to another latch circuit 132 and periodically latched by another latch timing signal 133 output from the timing generation circuit 124. The latched average value is used as the reproduction signal 1
The offset amount 105 is superimposed on 01. The offset amount 105 is input to the adder 102 and added to the reproduction signal 101 in the same manner as in the first embodiment.
06 is input to the pulsing circuit 107 and binarized information 1
08 is output as the detection information. Note that the information detecting device of the first embodiment can be configured as either an analog circuit or a digital circuit.
In this embodiment and the subsequent embodiments, the information detection device is configured as a digital circuit.

FIG. 3 shows how various signals are generated in the information detecting apparatus of the second embodiment. In this figure, the horizontal axis indicates the passage of time. FIG. 3A shows the reproduction signal 101. Playback signal 10
Since the DC fluctuation component is superimposed on 1, accurate level detection cannot be performed as it is.

FIG. 3B shows the latch timing of the latch circuit 132, and FIG. 3C shows the timing at which the integrator 122 with a clear signal is cleared. Since the latch timing signal 133 (FIG. 3B) is configured to be output earlier than the zero clear signal 125 by, for example, one-half clock of the clock pulse 123, the latch circuit 132 immediately before being cleared to zero is output to the latch circuit 132. The average value is held as the offset amount 105 (FIG. 3D), and the value is stored in the adder 102 shown in FIG. 1 until the next latch timing.
Will be entered. The adder 102 is arranged as shown in FIG.
As shown in (1), the offset amount 105 falling rightward is added to the reproduction signal 101 rising rightward. As a result, accurate level detection becomes possible.

Third Embodiment

FIG. 4 shows an information detecting device according to a third embodiment of the present invention. This information detecting device corresponds to the invention described in claim 3. In the third embodiment, an adder 10 is provided as in the first and second embodiments.
2. It includes a pulsing circuit 107 and a filter 109. The reproduction signal 101 is supplied to a latch circuit 141 instead of the phase correction circuit 103 of the first and second embodiments. The output 11 of the filter 109
1 is supplied to another latch circuit 142. A predetermined clock signal 145 is input to the latch circuit 142 from a timing generation circuit 144 that receives a supply of a clock pulse (PCLK) 123, and the output 111 is latched at these timings. This figure 4
In this example, the output 111 of the filter 109 is latched at a certain time t without using the phase correction circuit 103 of the previous embodiment, and the time delay τ from the input of the pulsating circuit 107 to the output of the filter circuit 109 elapses. At time (t + τ), the value of the reproduction signal 101 is latched. As a result, samples of two signals having the same phase are obtained. For this purpose, the timing generation circuit 144 generates the latch timing shifted in phase by τ.

Both latch circuits 14 after the phases are aligned
Outputs 146 and 147 of the integrators 1 and 142 are input to a subtractor 148, and a difference signal 149 of these outputs is output from the integrator 1
51 is input. The integrator 151 with a clear signal includes an adder 153 that adds the difference signal 149 to the addition result up to one clock before, and a latch circuit 154 that holds the addition result.
The content latched in 4 is fed back to the adder 153, and the difference signal 149 is added one after another, and the integration result is output to the external divider 155. The zero clear signal 156 is output from the timing generation circuit 144.
Is input to the latch circuit 154, and its contents are cleared to zero at predetermined time intervals.

The timing generation circuit 144 further generates two types of clock signals 157 and 158, of which the former clock signal 157 is supplied to another latch circuit 159, and the latter clock signal 158 generates the reproduced signal 101. The data is supplied to the input latch circuit 141. The latch circuit 159 outputs the output 16 from the divider 155.
The output 161 is sequentially latched at the timing when the clock signal 157 is supplied in response to the supply of the clock signal 157. The latched average value is supplied to the adder 102 as the offset amount 163. Also, the latch circuit 141
The reproduction signal 101 is latched at the timing when the clock signal 158 is supplied, and is input to the subtractor 148 as the output 146 described above.

The information detecting apparatus according to the third embodiment is designed so that the scale of the entire apparatus does not increase even when the phase difference between the input and output of the pulsating circuit 107 increases. For example, in the information detection devices of the first and second embodiments, since the phase difference between the input and output of the pulsing circuit 107 may be several tens of clocks, the phase difference shown in FIG. 1 or FIG. This is because a large number of memory circuits are required for the correction by the correction circuit 103, and the scale of the entire information detection device may be increased.

Therefore, in the third embodiment, a latch circuit 142 for latching the output 111 and another latch circuit 141 for latching the level of the reproduction signal 101 are used in place of the phase correction circuit 103 used in the previous embodiment. Output 146,
The phase difference of 147 is controlled by a timing generation circuit 144 for generating a timing at which the phase difference becomes zero. In this embodiment, the timing generation circuit 144 also generates a zero clear signal 156 and a clock signal 157.

FIG. 5 shows a state of generation of various signals centering on the output of the timing generation circuit in the information detecting device of the third embodiment. In this figure, the horizontal axis indicates the passage of time. FIG. 7A shows the latch timing of the latch circuit 141 by the clock signal 158, and FIG. 7B shows the latch timing of the latch circuit 142 by the clock signal 145. Also,
FIG. 9C shows the timing at which the clock signal 157 is output as the latch timing of the latch circuit 159, and FIG. 9D shows the output of the zero clear signal 156 as the clear timing of the integrator 151 with a clear signal. FIG. Thus, the latch circuit 15
Since the contents of the integrator 151 with a clear signal are cleared immediately after the latch circuit 9 has latched,
As shown in (e), the offset amount 163 is sequentially output, and this is the reproduction signal 101 and the adder 102 shown in FIG.
, And the resulting addition result 106 enables accurate level detection.

Fourth Embodiment

FIG. 6 shows the configuration of an information detecting device according to a fourth embodiment of the present invention. This information detection device corresponds to the invention described in claim 4. In the fourth embodiment, the adder 1 is used as in the first to third embodiments.
02, a pulsing circuit 107 and a filter 109. The reproduction signal 101 is also supplied to a first integrator 171. The output 111 of the filter 109 is supplied to a second integrator 172. The first integrator 171 includes an adder 173 that adds the reproduction signal 101 to the addition result up to one clock before, and a latch circuit 174 that latches the addition result.
The output of 74 is fed back to the adder 173 to perform addition. In the latch circuit 174,
A timing generation circuit 175 receiving the clock pulse (PCLK) 123 supplies a zero clear signal 176 for clearing the content at a predetermined timing.

A second integrator 172 is an adder 178 for adding the output 111 of the filter to the previous one.
And a latch circuit 179 for latching the addition result. The output of the latch circuit 179 is fed back to the adder 178 to be added. The latch circuit 179 is supplied with a zero clear signal 181 for clearing the contents from the timing generation circuit 175 at a predetermined timing.

The outputs 182 and 183 of the first and second integrators 171 and 172 are connected to the corresponding latch circuit 1 respectively.
84, 185 and the clock signals 186, 1
87. These latch circuits 18
The outputs 188 and 189 of 4, 185 are input to a subtractor 148, and the difference between them is obtained. Output 19 of subtractor 148
1 is input to the divider 192. Output 1 of divider 192
93 is input to another latch circuit 194 and is periodically latched by a clock signal 195 output from the timing generation circuit 175. The average value thus latched is the offset amount 197 superimposed on the reproduction signal 101. The offset amount 197 is input to the adder 102 and added to the reproduction signal 101. The addition result 106 is input to the pulse conversion circuit 107, and the binarized information 108 is output as detection information.

The information detecting apparatus according to the fourth embodiment has a third
In this embodiment, the responsiveness of the device according to the embodiment is improved.
That is, in the information detecting apparatus of the third embodiment shown in FIG. 4, since the difference signal can be used only discretely, the phase difference between the input and output of the pulsating circuit 107 is large and the DC fluctuation component Has a relatively high frequency component, the response is poor. Therefore, in the information detecting device of the fourth embodiment, before taking the difference, two signals 101,
The integration is performed separately for 111. That is, the reproduction signal 101 is integrated by the first integrator 171, and the integrated value is held by the latch circuit 184 at the latch timing determined by the clock signal 186. The output 111 of the filter 109 is integrated by the second integrator 17 and the integrated value is held by the latch circuit 185 at the latch timing determined by the clock signal 187.

The difference between the integrated values held by the two latch circuits 184 and 185 is obtained by the subtractor 148, thereby detecting the DC component, and holding the value by the latch circuit 194 at the latch timing determined by the clock signal 195. This is set as the offset amount 197 and the adder 1
At 02, the signal is added to the reproduction signal 101 and input to the pulsing circuit 107.

However, the first and second integrators 171,
172 and each clock signal 186, 1
The latch timings 87 and 195 are generated from the reproduced clock pulse 123 by using the timing generation circuit 175.

FIG. 7 shows changes in the latch timing, the clear timing, and the offset amount due to various signals output from the timing generation circuit of this embodiment. FIG. 7A shows the latch timing of the latch circuit 184 by the clock signal 186, and FIG. 7B shows the clear timing by the zero clear signal 176 input to the latch circuit 174 of the first integrator 171. ing. 7C shows the latch timing by the clock signal 187 input to the latch circuit 185, and FIG. 7D shows the zero clear signal input to the latch circuit 179 of the second integrator 172. 181 shows the clear timing. Further, FIG. 7E shows the latch timing by the clock signal 195 input to the latch circuit 194, and FIG.
The change in the offset amount 197 output from the signal 94 is shown. This is the reproduction signal 101 and the adder 1 shown in FIG.
02, and the resultant addition result 10
6 enables accurate level detection.

Fifth Embodiment

FIG. 8 shows the configuration of an information detecting device according to a fifth embodiment of the present invention. This information detecting device corresponds to the invention described in claim 5. In the fifth embodiment, the pulsing circuit 107 of the information detecting apparatus in the third embodiment is replaced with a Viterbi detector 201, and the other configuration is shown in FIG. 4 of the third embodiment. The circuit configuration is the same. Therefore, Viterbi detector 2
The description of the circuit parts other than 01 will be omitted as appropriate.

FIG. 9 specifically shows a Viterbi detector. The Viterbi detector 201 receives the addition result 106, calculates a square error (X _i −E _i ) ² from the value X _{i with} respect to the reference level E _i , a branch metric generation circuit 211, and Σ (X _i − E _i) and ² ACS circuit 213 for detecting the transition information of listen to calculate while state, selection information D of past transition paths stored in the path memory 215
₁ , D ₂ ,..., The path metric value (P
(M ₁ , PM ₂ ,...) Can be configured by a maximum likelihood determination circuit 217 that selects a transition path and outputs the binarized information 108 as detected binary information.

[0072]

As described above, claims 1 to 5 are provided.
According to the invention described above, even if the input information as the detection information from the disk medium includes a DC fluctuation component, the information can be reproduced well by compensating for the DC fluctuation component. For this reason, the reliability of the file device can be improved, which can greatly contribute to the spread of the file device. According to the third and fourth aspects of the present invention, since the latch circuit in the integrator is repeatedly cleared at a predetermined timing by using the timing circuit, a large-scale memory is used as the phase correction circuit. No need,
The size of the detector can be reduced accordingly.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information detection device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an information detection device according to a second embodiment of the present invention.

FIG. 3 is a waveform diagram showing how various signals are generated in the information detection device of the second embodiment.

FIG. 4 is a block diagram illustrating a configuration of an information detection device according to a third embodiment of the present invention.

FIG. 5 is a waveform diagram showing a state of generation of various signals centering on an output of a timing generation circuit in the information detection device of the third embodiment.

FIG. 6 is a block diagram illustrating a configuration of an information detection device according to a fourth embodiment of the present invention.

FIG. 7 is a waveform diagram showing changes in a latch timing, a clear timing, and an offset amount due to various signals output from a timing generation circuit according to a fourth embodiment.

FIG. 8 is a block diagram illustrating a configuration of an information detection device according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram specifically showing a Viterbi detector.

FIG. 10 is a block diagram showing a main part of an information detection device conventionally proposed to accurately detect the level of a reproduction signal including a DC component.

FIG. 11 is a block diagram showing a main part of another information detection device proposed conventionally.

FIG. 12 is a block diagram showing a main part of still another information detection device proposed conventionally.

[Explanation of symbols]

Reference Signs List 101 reproduction signal 102 adder 103 phase correction circuit 104, 129, 155 divider 107 pulse generator 109 filter 113, 148 subtractor 116, 122, 151 integrator 123 clock pulse 132, 141, 142, 154, 159, 174, 1
79, 184, 185, 194 Latch circuit 144, 175 Timing generation circuit 171 First integrator 172 Second integrator 201 Viterbi detector 211 Branch metric generation circuit 213 ACS circuit 215 Path memory

Claims (5)

(57) [Claims] 1. An adder for adding an offset amount to a reproduction signal detected from a disk medium, a pulsing circuit for receiving an output of the adder and outputting binary information, and an output from the pulsing circuit. A filter for inputting binary information and changing the frequency characteristic thereof; a phase correction circuit for correcting the phase of the reproduction signal to the same phase as the output of the filter; and an output of the phase correction circuit and an output of the filter. A subtractor that generates a difference between the two, a finite time constant integrator that inputs the output of the subtractor, a divider circuit that divides the output of the integrator and feeds back the result to the adder as the offset amount. An information detection device, comprising: 2. An adder for adding an offset amount to a reproduced signal detected from a disk medium, a pulsing circuit for receiving an output of the adder and outputting binary information, and an output from the pulsing circuit. A filter for inputting binary information and changing the frequency characteristic thereof; a phase correction circuit for correcting the phase of the reproduction signal to the same phase as the output of the filter; and an output of the phase correction circuit and an output of the filter. A subtractor that generates the difference between the two; an integrator that receives the output of the subtractor as an input; a divider circuit that divides the output of the integrator; an output of the divider circuit that is latched; A latch circuit that feeds back as an offset amount, and a timing generation circuit that receives a reproduction clock and generates a clear timing of the integrator and a latch timing of the latch circuit, respectively. Information detecting apparatus characterized by comprising a. 3. An adder for adding an offset amount to a reproduced signal detected from a disk medium, a pulsing circuit for inputting an output of the adder and outputting binary information, and an output from the pulsing circuit. A filter for inputting binary information to change the frequency characteristic thereof, a first latch circuit for holding a level of the reproduction signal, and a second latch circuit for holding an output of the filter. A subtractor that generates a difference between the outputs of the first and second latch circuits; an integrator that receives the output of the subtractor as an input; a division circuit that divides the output of the integrator; A third latch circuit that latches an output and feeds it back to the adder as the offset amount; and inputs a reproduced clock to clear the integrator and determine the clear timing of the integrator. And a timing generation circuit for generating a latch timing of each of the latch circuits. 4. An adder for adding an offset amount to a reproduction signal detected from a disk medium, a pulsing circuit for inputting an output of the adder and outputting binary information, and an output from the pulsing circuit. A filter for inputting binary information and changing its frequency characteristic, a first integrator receiving the reproduced signal, a second integrator receiving an output of the filter, and a first integrator. A first latch circuit for holding the output of the integrator, a second latch circuit for holding the output of the second integrator, and a difference between the outputs of the first and second latch circuits. A divider circuit that divides the output of the subtractor; a third latch circuit that latches the output of the divider circuit and feeds it back to the adder as the offset amount; Input An information detecting apparatus comprising: a clear timing of the first and second latch circuits in the integrator; and a timing generating circuit that generates latch timings of the first, second, and third latch circuits, respectively. . 5. The information detecting device according to claim 1, wherein a Viterbi detector is used as said pulse generating circuit.