JP2883364B2 - Timer system for quality control - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention is applied to a coffee brewer for extracting coffee and a dispenser for supplying various beverages, and is a quality which is convenient for controlling the quality of the extracted beverage. It relates to a timer system for management.

(B) Conventional technology In general, coffee, which is in high demand as a favorite beverage, is said to have the best taste immediately after extraction, and it is necessary to extract coffee every time in order to provide delicious coffee. However, when actually providing coffee at a restaurant or the like, a method is generally employed in which a large amount of coffee is extracted into a decanter at a time. At this time, if all of the extracted coffee cannot be provided immediately after extraction, the taste deteriorates (oxidizes) over time and the commercial value is impaired. Operation. The operator manages the time related to the quality while watching the clock one by one, and throws away any unsold after the above-mentioned fixed time (30 minutes).

(C) Problems to be Solved by the Invention However, according to the above-described conventional method, the operator must judge the elapsed time after the extraction while always watching the clock, and the time management is not easy. In particular, in the case of an unspecified number of operators, it has actually been said that it may not be possible to sufficiently manage when extraction is performed. In addition, it is possible to obtain more accurate time management and its easiness by using a timer, but also in this case, it is necessary to press the coffee brewing switch and the start switch of the timer at the same time, which is still insufficient for operation. I couldn't say.

The present invention has been made in view of the above points, and enables a plurality of timers to be sequentially operated in conjunction with an extraction function, and the elapsed time is automatically switched and displayed on one display. Accordingly, an object of the present invention is to provide a quality control timer system that facilitates coffee management and the like by an operator.

(D) Means for Solving the Problems The quality control timer system according to the present invention sequentially starts each time there is a sales signal generated in connection with the extraction operation, and the elapsed time after the extraction reaches a predetermined set time. At least two timers that operate until counting, a single indicator for displaying the elapsed time, and a corresponding indicator such that only the timer that has started earlier always displays the elapsed time. A conversion circuit that performs connection conversion with the timer, and when all the timers are operating, when the sales signal is further input, the earliest start timer is reset, and the timer is used for counting the elapsed time related to the last extraction And a display switch that operates so as to act on the conversion circuit section to switch and display the elapsed time of the next start timer on the display. And a warning means activated when the set time is reached.

(E) Operation The first timer starts upon receiving a sales signal by operating the extraction switch, and counts the elapsed time from the time of extraction. At the same time, the display unit displays the count time of this timer. When there is a sales signal again by the second extraction, the second timer starts and similarly counts the elapsed time. At this time, the elapsed time is not displayed.

In this way, the timer is sequentially started every time a sales signal is received, and the elapsed time from each extraction time is counted independently.
Then, the elapsed time of the timer started earlier is displayed on the display, and when the elapsed time reaches a preset time, an alarm means such as a buzzer is operated, and the operator is reminded and the unsold coffee is rejected. Urge you to

In addition, extraction is performed continuously, all timers are activated, and when further extraction is performed, the earliest start is started by the sales signal, that is, the timer currently displayed on the display is automatically reset, and the timer is terminated. The function is switched for counting the elapsed time related to the extraction. At the same time, the elapsed time counted by the timer started after the switched timer is displayed on this display instead of the reset timer. In this way, the sequential start operation of a plurality of timers in conjunction with the extraction operation,
The switching of the display of the timer elapsed time to the display can be sequentially shifted.

(F) Example The present invention will be described below with reference to the drawings.

As shown in FIG. 1, the coffee blower includes a main body 1A containing a hot water tank, a coffee extractor 100, and a decanter 101.
And the upper and lower heat retaining heater plates 102 and 103 on which the
When the upper heat retaining heater plate 102 is extracted into a second decanter, the former decanter 101 is replaced. Reference numeral 104 denotes a power switch, and reference numerals 105 and 106 denote ON and OFF switches of the heat retention heater plates 102 and 103, respectively. An operation panel 110 is provided in front of the upper body 1A.
As shown in FIG. 2, the extraction switch 111 having a different extraction amount, the lamp 107 in the operation table, and the hot water temperature display lamp 1
08 and a timer display section 9 that displays the elapsed time after extraction
, A reset button 14 for clearing the timer operation, and a display switching button 15 for temporarily calling the measurement time of the back timer to the timer display unit 9 as described later.

The present invention makes it possible to know how long the coffee after extraction has been kept warm and how long it has been kept warm, so that quality control of the coffee can be properly performed. That is, at least two or more timers are used, the timers are sequentially started by the extraction switch, and the timer time of the timer that has been operated earlier is displayed, and the limit time (normally 30 minutes) at which the coffee deteriorates is reached. Then, the timer display section is controlled to display an alarm by blinking, notifying by a buzzer, turning on a time-up indicator, and the like. FIG. 3 shows a basic block configuration diagram for performing the above control operation, and FIG. 4 shows a specific control circuit diagram thereof.

First, in FIG. 3, both the timer AI and the timer BII count the minute time based on the reference frequency from the second oscillator 5, and have an internal configuration including a 60-times minute oscillator and a minute time counting unit. Timer AI for convenience of explanation here
Are abbreviated as timer A and timer BII as timer B, and the description will be continued. And timer A and timer B are
The set time is arbitrarily set by the timer setting circuit 6. That is, the set time is a limit time for the coffee after extraction not to be deteriorated, and is usually about 30 minutes. Then, the set time is compared with the elapsed time of the timers A and B, and the counting is stopped when the time is up.

On the other hand, a timer switching circuit 8 is provided so that the two timers A and B start sequentially in the sales signal circuit 7 that generates an extraction signal generated in conjunction with the extraction switch, that is, the sales signal A. . The count content of the timer (elapsed time after extraction) is displayed on the display 9, and in this case, only the one that has been started first is displayed on the display 9. That is, if the timer displayed on the display 9 is a front timer, and the timer that is performing the count operation of the timer (the timer elapsed time of a timer extracted later) but not displayed on the display 9 is a back timer, , A timer A and a timer B are provided with a conversion circuit 10 for converting the display 9 so that only the front timer is always connected. When the count time of the front timer reaches the set time, the front timer issues a buzzer generation circuit 11 to sound an alarm, and the time displayed on the display 9, that is, the set time blinks. Then, the time is over and the operator is urged to reject the coffee in the decanter.

By the way, the timer is switched by the sales signal A,
The manner in which the timers A and B start sequentially will be described in detail in connection with the sequential operation of the extraction switch.
When the power is turned on, both the timer A and the timer B are automatically reset to an initial state. Then, a display of "00" is input to the display 9 from one of the timers A and B. In this case, for example, it is assumed that the timer B corresponds to the display 9, and the first sales signal A
Is obtained, the sales signal A switches the timer so that the timer A starts. Timer A starts counting the elapsed time after the extraction. At the same time, conversion of display switching is performed by the conversion circuit 10 so that the elapsed time is displayed on the display 9. That is, the timer A is a front timer. Then, when the amount of the first extracted coffee decreases, the decanter 101 is moved to the above-mentioned heat retaining heater plate 102, a new decanter 101 is set on the lower heat retaining heater plate 103, and the extrusion switch 111 is pressed to perform the second coffee extraction. Thus, when there is a second sales signal, the timer is switched and the timer B is started. At this time, the timer B starts as a back timer that independently counts the elapsed time after the second extraction switch operation, but the content is not displayed on the display 9. Of course, the table timer (timer A) continues the count operation. In this way, both timers A and B operate, and when the front timer (timer A) reaches the set time, an alarm by the buzzer circuit and a blinking display of the display 9 are displayed.

Thus, the first coffee extract disappears within the set time, and a new decanter 10 is used in order to perform a new third extraction.
1 is set again on the lower heater plate 103, and the extraction switch 11
When 1 is pressed and a third sales signal A is generated, a control signal (dotted arrow A ') is output so as to immediately reset the front timer (timer A) by the sales signal A, and the reset circuit 12 operates. At the same time as the reset, the control signal (dotted arrow A ″) is also input to the timer display switching circuit 13 and the display switching signal from the timer display switching circuit 13 that is generated after a predetermined time delay causes the back timer (timer) to become the front timer. The conversion circuit 10 is controlled as described above, and after the transfer, the timer A is switched from the front timer to the back timer to start counting the elapsed time after the third extraction. The elapsed time since the second extraction is displayed, and the timer B continues to operate as the front timer and the timer A continues to operate as the back timer. 4 and subsequent reset operation is performed automatically.

The manual timer switch 14 resets the table timer.
It is also performed in That is, the display 9
Flashes and the buzzer sounds, and the manual reset switch 14 is pressed when the timer count is canceled within the set time. In the former case, only the back timer receives the reset signal and immediately enters the initial state ("00" display and sales signal can be received). At the same time, the display is switched after a certain time, the back timer becomes the front timer, and the elapsed time extracted later is displayed on the display 9. If later extraction has not been performed, "00"
Is displayed. In the latter case, the manual reset switch
When 14 is pressed, if there is one decanter 101, the table timer is reset and the display becomes "00". Decanter 101 is 2
In the case of the number, after the front timer is reset, the back timer becomes the front timer and the elapsed time extracted later is displayed. The manual display changeover switch 15 is pressed when confirming the elapsed time of the back timer. While the switch is kept pressed, the display switching circuit is operated to enable the timer elapsed time of the back timer to be displayed on the display 9. .

FIG. 4 shows a specific control circuit diagram of the block diagram of FIG. 3 described above. In this figure, components equivalent to those in FIG. 3 are shown by surrounding each with a dotted frame.

The timers A and B receive the oscillation output from the second oscillator 5 via the analog switches 20 and 21 together, and
A, 2B and the minute / hour counting units 3A, 3B are operated. twenty two
Is a time setting device for the timers A and B, which arbitrarily sets the maximum time (usually 30 minutes) at which the elapsed time of the coffee after extraction is determined to be unsuitable for drinking. 23,24
Is a comparator which compares the time T ₀ set by the time setting device 22 with the elapsed time T counted by each of the timers A and B,
= T ₀ become the H-level time up output P, and outputs the P. The H-level time-up outputs P and P turn on the light-emitting diodes 25 and 26 connected via resistors to indicate the time-up, and indicate that the inverters 27 and 28
To the L level, and the analog switches
20 and 21 are turned off, and the counting operation of timer A and timer B is stopped. The time-up outputs P and P are input to one of the inputs of the AND circuits 90 and 91, respectively, and are also input to the OR circuit 30 of the buzzer generation circuit 11. Therefore, when either of the timers A or B reaches the set time, the buzzer is output. BZ sounds. In the buzzer BZ, the transistor Tr performs a switching operation via the buzzer continuous sound oscillating section 31 and the driver section 32 to continuously sound and inform of the time up. r ₁ is a buzzer
BZ volume control resistor. By the way, each of the timers A,
The elapsed time (minutes) T counted by B is displayed on the display unit 9. In this case, the elapsed time T displayed on the display unit 9 is determined by the timer started earlier, that is, the timer of the front timer. It is necessary to input the count output to the decoder 33. Since the timer A and the timer B become the front timer or the back timer B, the output relation to the decoder 33 must be converted according to the change. The analog switches 34 and 35 perform the conversion. As for the analog switches 34 and 35, the one corresponding to the front timer is turned on, and the one corresponding to the back timer is turned off. Therefore, the analog switches 34 and 35 are supplied with positive and negative signals, that is, one is supplied with an H-level signal to make it conductive, and the other is supplied with an L-level signal to make it non-conductive. The analog switch 34 on the timer A side and the analog switch 35 on the timer B side output the output before and after the inversion via the inverter 36 of the timer display switching circuit 13 so that the above-described control is established. Have given. That is, if the A timer is a front timer, the analog switch 34 receives the inverted H-level output, while the analog switch 34 receives the L-level output before the inversion. The elapsed time T counted by the timer A is displayed on the display 9 via the decoder 33. Conversely, when the B timer becomes the front timer, the same operation is performed in reverse, and only the B timer displays the elapsed time counted. The inverted output of the inverter 36 is input to the AND circuit 90, while the output before the inversion is input to the AND circuit 91. Accordingly, in the table timer in which the count output of the timer is input to the decoder 33 and the elapsed time T is displayed on the display 9, when the elapsed time T reaches the set time T ₀ , each of the comparators 23 and 24 outputs the time. Since the up outputs P and P are output, the AND outputs of the AND circuits 90 and 91 can be obtained at that time, and O
An H level signal is supplied to the analog switch 38 via the R circuit 37.
And the switch 38 is turned on. Then second oscillator 5
Is input to the blacking terminal BI of the decoder 33, and the elapsed time being displayed on the display 9, that is, the set time T ₀
Flashes. In this way, the blinking of the display also informs that the time is up. Reference numeral 40 denotes a light emitting diode for displaying the time in seconds, and the oscillation output from the second oscillator 5 is blinked through the inverter 41. Reference numeral 42 denotes a power-on reset circuit, which outputs one H-level pulse via the inverter 43 when the power is turned on. This pulse is input to the reset terminals R of the frequency dividers 2A and 2B of the timer A and the timer B via OR circuits 44 and 45, which are components of the timer switching circuit 8, and the respective frequency dividers 2A and 2B are inputted. At the same time as resetting, the signals are also input to the preset terminals PE of the minute / hour counter units 3A and 3B to set the minute / hour counter units 3A and 3B to an initial state where the count is zero. Meanwhile Furthermore, the 1 pulse from the power ON reset circuit 42, the reset terminal of the flip-flop FF ₁ 46 that is input to sell signal C from the sale signal generating circuit 7 to the clock terminal CL (hereinafter abbreviated drawing number 46) enter the R, an output terminal Q to L level of the flip-flop FF _1, and sets the output terminal to an initial state to an H level (abbreviated below drawing number 47) flip-flop FF ₂ 47 and flip-flop FF ₃ Input to each reset terminal R of 48 (hereinafter abbreviated as 48) via OR circuits 49 and 50, and set each output terminal Q to L level and set each output terminal to H level to the initial state. I do. The flip-flop FF ₂ clock terminal CL
The connecting one of the input and output terminals of the flip-flop FF ₂ itself, an AND circuit 51 to the other input and output terminal Q of the flip-flop FF ₁ directly. Similarly the flip-flop FF ₃ clock terminal CL
, The one of the input and output terminals of the flip-flop FF ₃ itself, said other input flip-flop FF ₁
The AND circuit 52 that is the output terminal of
The connection is delayed by an R delay circuit 53. This delay circuit 5
3 is the case where the ADN circuit 52 is alive when the power is turned on and the flip-flop FF
₃ is to prevent malfunction. The output terminals Q of the flip-flops FF ₂ and FF ₃ are connected to the inverters 54 and 5 respectively.
Therefore, when each output terminal Q changes from L level to H level, an inverted output of L level is obtained, and each OR circuit 4
4 and 45, the frequency divider circuits 2A and 2B of the timer A and the timer B and the reset terminals R of the minute time counters 3A and 3B,
And a preset terminal PE, respectively, so that the count can be started from the initial state. As described above, each of the timers A and B is a timer that is preset by an H level signal output from the OR circuits 44 and 45 and is in a count operation state by an L level signal. In addition, the OR circuits 44 and 45 have AND circuits
Although there are inputs from 56 and 57, the functions of the AND circuits 56 and 57 will be described later.

Next, in the sales signal generation circuit 7, the extraction switch 111
When is pressed, the signal is transmitted via photocoupler 58 and OR
In addition to the input to the circuit 59, a test signal generated by the test switch TS pressed instead of the extraction switch 111 during the sales test is input to the OR circuit 59 via the inverter 60. While matching the extraction time (e.g. 3 minutes), the sale signal A output from the OR circuit 59 at the H-level state via a delay circuit 61 including the resistor R _A and capacitor C _A is input to the inverter 62, inverted L-level sales signal B further clock terminal CL of said been inverted a sale signal C of the original H level by the inverter 63 the flip-flop FF ₁ of
To enter. The flip-flop FF ₁ is connected to this clock terminal C
The operation is performed by the rising edge of the pulse input to L, and the output terminal Q is at H level and the output terminal is at L level. Thereafter, each time the next sales signal C is input, the output states of the output terminal Q and the output terminal sequentially change.

Therefore, the flip-flop is generated by the first sales signal C.
FF ₁ is operated, then the flip-flop FF ₂ is operated in its output terminal Q "H" level output inverter 54, OR circuit
The "L" level output is output via 44, and the A timer becomes a front timer and performs a counting operation. If there is a next sale signals C, it operates the flip-flop FF ₁ again, then FF ₃ operates, becomes its output terminal Q to "H" level, as well via an inverter 55, OR circuit 45 "L" When the level output is generated, the B timer starts the counting operation, and becomes the back timer. At this time, the flip-flop FF ₂ and the AND circuit 64 is operated by the "H" level of the Q output operation of the flip-flop FF _3, wherein the indicator of the input 7 segment configuration that AND output is Dp terminal of the decoder 33 9 A dot display at the lower right of is displayed to indicate that the back timer has operated. Thus, under the conditions of the operation of both the front timer and the back timer, when the sales signal (third signal) C is further input, the sales signal A and the sales signal B and the AND output from the AND circuit 64 are connected to the resistor Rc.
The signal D, which is delayed by the delay circuit 59 including the capacitor Rc and the capacitor Dc, is input to the AND circuit 65 to generate a reset signal E. As will be described in detail later, after the first extraction, the reset signal E has a second extraction within the set time T ₀ , both timers A and B operate, and the third extraction is performed as described above. automatically output when performed within the set time T _0, resets the timer which started earlier, i.e. the table timer is in the display.

Next, in the reset circuit 12, when the reset signal E is automatically output from the AND circuit 65 at the H level, the OR circuit 66,
The output is transmitted to the reset signal line RL via the analog switch 67 and is input to one of the input terminals of the AND circuits 56 and 57, respectively. However, the other input terminal of the AND circuit 56 has
Because the inverted output via the inverter 36 and the output before inversion are input to the other input terminal of the AND circuit 57, when the inverted output or the output before inversion is at the H level,
An AND output is obtained from the AND circuits 56 and 57 with the reset signal E, and the H level reset signal E is output through the OR circuits 44 and 45.
To the reset terminals R of the frequency dividers 2A and 2B in each of the timers A and B and the preset terminals PE of the minute time counters 3A and 3B.
To reset. In other words, this means that only the currently displayed timer (front timer) receives the reset. The timer being displayed can be reset manually or arbitrarily. When the manual reset switch 14 is closed in the manual reset section 68, one pulse of H level is output via the inverter 69 to become a reset signal, and the same operation is performed.

Incidentally, the automatic reset signal E and one pulse due to the manual reset also serve as an operation signal of the timer display switching circuit 13. The timer display switching circuit 13 having the automatic reset signal E and a reset pulse due to manual reset as input signals has the following configuration. That is, the reset signal is output from the power ON reset circuit 42 to the reset terminal R.
A receiving output terminal Q to L level, the flip-flop FF ₄ 70 (hereinafter figure number 70, which is initially set to the output terminal to the H level
The clock terminal CL of the flip-flop FF ₄ is provided with an automatic reset signal E (equivalent to a reset pulse by manual reset) according to the time constants Rc and Cc of the delay circuit 71, The inverted signal F is used as one input, and the other input is an OR circuit 73 when one of the flip-flops FF ₂ and FF ₃ is operating.
An AND circuit 74 for outputting a signal G is connected. The output of the output terminal Q of the flip-flop FF ₄ is inverted by the inverter 75 resistors, analogue switches
One is input to the inverter 36 via the other, the other is directly input as an ON / OFF control signal for the analog switch 35 on the timer B side, and the AND circuit
Input to one of 91. The inverted output via the inverter 36 is turned on for the analog switch 34 on the timer A side,
It is input as an OFF control signal and is also one input of the AND circuit 90.

Therefore, the flip-flop FF is generated by the first sales signal A.
_{When the} signal G is output from the OR circuit 73 through the operations of ₁ and FF ₂ , the signal a is ANDed with the signal F that is normally input to one of the AND circuits 74 in the “H” level state. AND circuit
Flip-flop FF ₄ operates the rising signal I from 74, further via the inverter 36 via the inverter 75 "
An H ″ level signal is output from the timer display switching circuit 13. The output from the display switching circuit 13, ie, the inverter 36
"H" level output from the analog switch 34 is ON,
The analog switch 35 is turned off by the "L" level output before the input to the inverter 36, and the timer A becomes the front timer and the timer B becomes the back timer. Then there is a second sale signal A when the count operation of the back timer (timer B) is started, but the display switching circuit 13, since the rising signal I is not through an AND circuit 74, flip-flop FF ₄ is not work Therefore, the output before and after the inverter 36 does not change. Therefore, the timer A still keeps the front timer and the timer B keeps the back timer. Thus, both timers A,
When B operates and there is a third sales signal A, an automatic reset signal E is output and the timer A is reset. Then, the automatic reset signal E is generated for a certain time (time constant).
RcCc) After the delay, the AND condition of the AND circuit 74 is satisfied,
Generating a rising signal I, operates the flip-flop FF ₄ is the same signal I, resulting longitudinal output of inverter 36 is reversed. That is, the output through the inverter 36 changes from H to L,
The output immediately before input to the inverter 36 changes from L to H.

Therefore, analog switch 34 is OFF, analog switch 3
When 5 is turned on, the timer B becomes a front timer whose elapsed time T is displayed on the display 9 via the decoder 33.

On the other hand, the reset timer A becomes the back timer,
The counting of the elapsed time T required for the third extraction operation is started.

In this way, the timer display switching signal output from the timer display switching circuit 13 is generated by the third extraction operation because two timers are used in this case, and the timer display is switched. Therefore, if the number of commonly used timers is N, the earliest start timer is reset by the (N + 1) th sales signal, and the timer is caused to count the elapsed time associated with the last extraction. The switching of the front timer and the back timer for displaying the elapsed time on the display as a timer is performed sequentially.

In this way, the output before and after the inverter 36 indicates the A timer as the front timer (the B timer is the back timer at this time).
Or a timer display switching signal indicating whether the B timer is a front timer (the A timer is a back timer at this time).

By the way, if the analog switch 34 on the front timer side has an H level signal and the analog switch 35 on the rear timer side has an L level signal,
As the input state of the level signal, the front timer is counted and displayed on the display unit 9 and when the back timer is performing the count operation, the output relation is forcibly reversed and the analog switch on the back timer side is temporarily set. When set to ON, the elapsed time of the back timer is checked. That is,
Operate the manual display changeover switch 15 to confirm this.
When the switch 15 is pressed, the two inverters 78, 7
An L level signal is input to the analog switch 76 via 9 and the analog switch 76 is turned off. On the other hand, another analog switch 80 is set to H by the third inverter 81.
Turns on when the level is inverted. This analog switch 80
The ON, the output from the output terminal Q of the flip-flop FF _4, since the output through the inverter 75 and the inverter 82, the output relationship of the front and rear with respect to the inverter 36 is reversed. Therefore, the back timer temporarily becomes the front timer, and the elapsed time of the count is displayed on the display 9. The display is performed while the manual display changeover switch 15 is kept pressed. When the manual display changeover switch 15 is pressed, an L-level output from the inverter 79 is input to the analog switch 67 so that the manual reset is prohibited.
OFF. When the manual display changeover switch 15 is OFF, the output of the inverter 78 is L, and the output from the inverter 79 is H.
Since this is an output, the analog switch 76 is ON. The output from the inverter 81 is L and the analog switch 80 is OFF.

Next, the operation of the above configuration will be described for each functional operation item and with reference to the time chart of FIG.

(A) Automatic reset operation at power-on When power is turned on, one pulse is generated by the inverter 43 of the power-on reset circuit 42 and the flip-flops FF ₁ , FF ₂ ,
FF ₃ , FF ₄ and each divider 2A of timer A and timer B,
Initialize 2B and minute / hour counter units 3A and 3B.

(B) Timer priority operation In order to display the two timers A and B on one display 9, it is necessary to start the timer displaying the first timer operation, that is, the front timer. Therefore, in the initial state, the output terminal Q (hereinafter Q sale signal generating circuit 7 flip-flop FF ₁ by the rising edge of sale signal C after a slight delay when selling signal A is outputted from (hereinafter abbreviated as FF ₁₎ Abbreviated as "H").
At this time, the AND of the AND circuit 51 is established, and the output becomes “H”, and the output terminal Q of the flip-flop FF ₂ (hereinafter abbreviated as FF ₂ ).
(Hereinafter abbreviated as Q) becomes L → H output. Same "H"
The output is inverted by the inverter 54 to become "L" output and OR
Input to the frequency divider 2A and the minute time counting unit 3A via the circuit 44, the timer A starts counting operation.

Then, the output of the activated FF ₂ changes from H → L, so A
The sales signal is not accepted during the timer operation by the ND circuit 51. Also, since the output of FF ₂ changes from L to H, the OR circuit 7
3 and the "H" input to the other side of the AND circuit 74, an AND is established and the flip-flop F
Because F ₄ (hereinafter abbreviated as FF ₄₎ providing a rising signal to the clock terminal CL of the output terminal Q (hereinafter abbreviated as Q) becomes L → H. Therefore, it is inverted by the inverter 75,
Further, the signal is inverted by the inverter 36 through the analog switch 76 which is in the conductive state, and the output becomes "H". The analog switch 34 becomes conductive and the count content of the timer A is displayed on the display 9 through the decoder 33.

When the sales signal is input again, the output of FF ₁ changes from L to H, so that the flip-flop FF ₃ (hereinafter referred to as FF ₃ )
FF ₃ ) is changed from L → H. The "H"
The "L" output of the Q output from the inverter 55 and the OR circuit 45 is input to the frequency divider 2B and the minute time counter 3B of the B timer, and the timer enters the count state. However, AND
Since the H output does not change while inputting to the circuit 74,
Since the signal I does not rise and the output state of the FF ₄ does not change, no display switching signal is generated. Therefore, the display unit 9 does not display the elapsed time of the count of the B timer. That is, the B timer becomes a back timer.

(C) Display and confirmation operation at the time of the back timer operation At the time of the back timer operation, the lower right dot of the display 9 composed of 7 segments is displayed. (Timer operation is FF ₂ and F
Since the Q output of F ₃ becomes “H”, both become “H”.
Detected by AND circuit 64. In order to check the elapsed time of the back timer, since the inverter 36 is inverted while the manual display changeover switch 15 is pressed, it can be easily checked. When the back timer is checked, the analog switch 67 is turned off so that manual reset is not accepted.

(D) Manual reset operation (alarm stop and timer stop) When the manual reset switch 14 is pressed, the inverter 69 generates one pulse. Then, only the front timer receives this reset signal via the reset signal line RL via the AND circuit 56 or 57, and immediately enters the initial state ("00" display and sales signal can be received). At the same time, a display switching pulse is input to FF ₄ with a delay of a fixed time (determined by Rc and Cc), so that FF ₄ inverts and the output before and after via inverter 36 reverses, and as a result, the back timer and the front timer (Automatic display switching). However, when the back timer is not operating, the reset operation is performed but the AND circuit 74
, Display consistency is ensured by preventing display switching. The consistency of the display means that when a sales signal is input,-When the table timer is "00", only the table timer always starts.

-When the front timer is operating, the front timer must start and the back timer starts.

・ When both are working, the table timer is reset,
Next, the back timer switches to the front timer and the back timer starts.

-Manual reset is accepted only for the front timer.

・ The table timer must always be the timer that started first.

Means

(E) Automatic reset operation When the back timer is operating on the front timer and a sales signal is further input, the front timer is reset,
This is an operation to start the back timer after moving the back timer to the front timer.

 The operation will be described with reference to the time chart of FIG.

(I) Initial operation When the sales signal A (normally "H" during the coffee extraction time) is input, the C signal and the I signal operate as a rising edge timer after a delay time determined by R _A and C _A. .

(II) Second Operation Although the C signal rises, the I signal does not change, so it starts as a back timer. Since A, B and D do not become "H" at the same time, no reset signal is generated.

(III) Third operation When the sales signal A rises, A, B and D are simultaneously set to "H".
Therefore, the automatic reset signal E resets the rising edge timer. The reset pulse width is determined by R _B and C _B.

At the same time, after the time determined by Rc and Cc has elapsed, the signal F rises, so that the display is switched and the back timer becomes the front timer.

The sales signal C delayed by R _A and C _A during the time when the above operation is completed is started after the display is switched, and thus starts as a back timer.

Since the front timer and back timer operate again, waveform D
Also becomes "H". For this reason, the automatic reset circuit operates similarly in the fourth and subsequent times, so that there is no need to reset the timer to the initial state by manual reset.

(F) Alarm action setting time (usually 30 minutes after coffee extraction)
When the signal reaches "H", an "H" signal is output by the comparator of FIG.
The clock input is stopped by 0 and 21. An LED is provided for output display to facilitate inspection on the board.

Only the front timer turns on the analog switch 38 via the AND circuit 90 (or AND circuit 91), and outputs the second oscillation signal to the decoder 33.
To the BI (Blanking) terminal to blink the display to indicate that the display time has been reached.

Further, in order to draw attention by sound, a set time reaching signal is guided to a buzzer oscillation circuit 11 to sound a buzzer BZ. Although the buzzer which will make the volume control by the resistance r ₁ may be further provided a buzzer stop switch.

It is as described above. Although the count-up method is used in the embodiment, the count-down method can be easily configured. In the embodiment, two timers, a front timer and a back timer, are displayed on one display.
It is also applicable to more than three cases.

(G) Effects of the Invention As described above, according to the present invention, a plurality of timers for counting elapsed time after the extraction, such as coffee extraction, are sequentially started in conjunction with the extraction operation.
The operation required for the timer operation can be omitted, and the burden on the quality control of the operator can be reduced.

Further, since one display is used and the display is automatically switched to the oldest one (the one that has been extracted first), the elapsed time is automatically switched in sequence in conjunction with the extraction operation. Attention should be paid to pre-extracted coffee and the like, and quality control becomes easier. Then, when a certain period of time is reached, a warning is issued, and many unspecified operators can easily perform the rejection of the corresponding coffee, and have many effects.

[Brief description of the drawings]

1 shows a coffee brewer equipped with a timer system for quality control according to the present invention, wherein (a) is a front view thereof, (b) is a side view thereof, and FIG. 2 is a front view of an operation panel relating to coffee extraction operation. FIG. 3 is a block diagram of a timer system for quality control of the present invention, FIG. 4 is an electric circuit diagram embodying FIG. 3, and FIG. 5 is a time chart diagram. 1 ... Coffee brewer, I ... Timer A, II ...
Timer B, 5: Second oscillator, 6: Timer set circuit, 7, Sales signal generation circuit, 8, Timer switching circuit, 9, Display, 10 Conversion circuit, 11 Buzzer generation circuit, 12 reset circuit, 13 timer display switching circuit, 14 manual reset switch, 15 manual display switching switch.

Claims (1)

(57) [Claims] 1. At least two or more timers, each of which starts sequentially in response to a sales signal generated in connection with an extraction operation and counts an elapsed time after extraction until a predetermined set time is reached; A single display for displaying the time, a conversion circuit for making a connection conversion with the corresponding timer so that only the timer that started earlier always displays the elapsed time, and a display for all the timers. During operation, when a sales signal is further input, the earliest start timer is reset, and the timer is made to function as an elapsed time count for the last extraction, and is acted on to the conversion circuit unit to perform the next operation. A timer display switching circuit that operates so as to display the elapsed time related to the previous start timer on the display, and an alarm unit that operates when the set time is reached. Timer system for quality control, characterized in that.